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#
# README -- the short version
#

The top level makefile handles the host code and FX2 firmware.

Besides the normal gcc suite and all the auto tools, you'll need
the SDCC free C compiler to build the firmware.  You MUST
USE VERSION 2.4.0 or VERSION 2.5.0 due to some problems with variable
initialization.  http://sdcc.sourceforge.net


The high level interface to the USRP using our standard FPGA bitstram
is contained in usrp/host/lib/usrp_standard.h

If you've got doxygen installed, there are html docs in
usrp/doc/html/index.html


# Compiling the verilog (not required unless you're modifying it)

If you want to build the FPGA .rbf file from source (not required; we
provide pre-compiled .rbf files in usrp/fpga/rbf directory), you'll
need Altera's no cost Quartus II development tools.  We're currently
building with Quartus II 5.1sp1 Web Edition.  The project file is
usrp/fpga/toplevel/usrp_std/usrp_std.qpf.  The toplevel verilog file
is usrp/fpga/toplevel/usrp_std/usrp_std.v.  The bulk of the verilog
modules are contained in usrp/fpga/sdr_lib