URL
https://opencores.org/ocsvn/gecko3/gecko3/trunk
Subversion Repositories gecko3
[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [GECKO3COM_simple.xise] - Rev 25
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="GECKO3COM_defines.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator/coregenerator_fifo_dualclock.xco" xil_pn:type="FILE_COREGEN"/>
<file xil_pn:name="fifo_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="gpif_com.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="gpif_com_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="gpif_com_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="message_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="gpif_com_test_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
<file xil_pn:name="gecko3com_test_chipscope.cdc" xil_pn:type="FILE_CDC">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="GECKO3COM_simple.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator/coregenerator_fifo_receive.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator/coregenerator_fifo_send.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="fifo_receive.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="fifo_send.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="GECKO3COM_simple_datapath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="GECKO3COM_simple_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="GECKO3COM_simple_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="GECKO3main_v1.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator/coregenerator_fifo_dualclock.ise" xil_pn:type="FILE_COREGENISE"/>
<file xil_pn:name="coregenerator/coregenerator_fifo_receive.ise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator/coregenerator_fifo_send.ise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
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<property xil_pn:name="Auto Implementation Top" xil_pn:value="false"/>
<property xil_pn:name="Command line syntax" xil_pn:value="emacsclient +$2 $1"/>
<property xil_pn:name="Compiled Library Directory" xil_pn:value="lib"/>
<property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
<property xil_pn:name="Device" xil_pn:value="xc3s4000"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
<property xil_pn:name="Editor" xil_pn:value="Custom"/>
<property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|gpif_com_test|behaviour"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/gpif_com_test"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="Soft"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="true"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|GECKO3COM_simple|Behavioral"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="usb_tmc_com"/>
<property xil_pn:name="PROP_mapSmartGuideFileName" xil_pn:value=""/>
<property xil_pn:name="PROP_parSmartGuideFileName" xil_pn:value=""/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs"/>
<property xil_pn:name="Package" xil_pn:value="fg676"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="false"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="false"/>
<property xil_pn:name="Report Type" xil_pn:value="Error Report"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Error Report"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="Yes"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Architecture|GECKO3COM_simple|Behavioral"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="1 ns"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="2000ns"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
<property xil_pn:name="Simulator Path" xil_pn:value="/opt/mentorGraphics/modeltech/bin/"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
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<property xil_pn:name="iMPACT Project File" xil_pn:value="GECKO3COM.ipf"/>
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<bindings>
<binding xil_pn:location="/gpif_com_test" xil_pn:name="gecko3com_test_chipscope.cdc"/>
<binding xil_pn:location="/gpif_com_test" xil_pn:name="GECKO3main_v1.ucf"/>
</bindings>
<libraries/>
<partitions>
<partition xil_pn:name="/gpif_com_test"/>
</partitions>
</project>
Go to most recent revision | Compare with Previous | Blame | View Log