Subversion Repositories gecko3

    ____  ____
   /   /\/   /
  /___/  \  /    VENDOR      : Xilinx Inc.
  \   \   \/     VERSION     : 9.1.03i (J.33)
   \   \         APPLICATION : compxlib
   /   /         CONTENTS    : Compilation Log
  /___/   /\     FILENAME    : compxlib.log
  \   \  /  \    CREATED ON  : Mon Jun 15 17:50:03 2009
   \___\/\___\

XILINX = '/opt/xilinx/ise_91i'
Library Source => '/opt/xilinx/ise_91i'

Compilation Mode = FAST
Scheduling library compilation for SPARTAN-3 

Signature:-
------------------------------------------------------------------------------
compxlib -s mti_se
         -arch spartan3
         -lib unisim
         -lib simprim
         -lib xilinxcorelib
         -l vhdl
         -dir /home/habea2/Geccko3com/gecko3com_v04/lib
         -log compxlib.log
         -w
         -p /opt/mentorGraphics/modeltech/bin/
------------------------------------------------------------------------------
Compiling Xilinx HDL Libraries for ModelSim SE Simulator
Language => vhdl
Backing up setup files if any...
Output directory => '/home/habea2/Geccko3com/gecko3com_v04/lib'

--> Compiling vhdl unisim library
    > Unisim compiled to /home/habea2/Geccko3com/gecko3com_v04/lib/unisim

==============================================================================
START_COMPILE unisim


Copying /opt/mentorGraphics/modeltech/linux/../modelsim.ini to modelsim.ini
Modifying modelsim.ini

Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling package vcomponents

Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
-- Loading package standard
-- Loading package textio
-- Loading package std_logic_1164
-- Loading package vital_timing
-- Loading package vital_primitives
-- Compiling package vpkg
-- Compiling package body vpkg
-- Loading package vpkg

Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity and2
-- Compiling architecture and2_v of and2
-- Compiling entity and2b1
-- Compiling architecture and2b1_v of and2b1
-- Compiling entity and2b2
-- Compiling architecture and2b2_v of and2b2
-- Compiling entity and3
-- Compiling architecture and3_v of and3
-- Compiling entity and3b1
-- Compiling architecture and3b1_v of and3b1
-- Compiling entity and3b2
-- Compiling architecture and3b2_v of and3b2
-- Compiling entity and3b3
-- Compiling architecture and3b3_v of and3b3
-- Compiling entity and4
-- Compiling architecture and4_v of and4
-- Compiling entity and4b1
-- Compiling architecture and4b1_v of and4b1
-- Compiling entity and4b2
-- Compiling architecture and4b2_v of and4b2
-- Compiling entity and4b3
-- Compiling architecture and4b3_v of and4b3
-- Compiling entity and4b4
-- Compiling architecture and4b4_v of and4b4
-- Compiling entity and5
-- Compiling architecture and5_v of and5
-- Compiling entity and5b1
-- Compiling architecture and5b1_v of and5b1
-- Compiling entity and5b2
-- Compiling architecture and5b2_v of and5b2
-- Compiling entity and5b3
-- Compiling architecture and5b3_v of and5b3
-- Compiling entity and5b4
-- Compiling architecture and5b4_v of and5b4
-- Compiling entity and5b5
-- Compiling architecture and5b5_v of and5b5
-- Compiling entity bscan_fpgacore
-- Compiling architecture bscan_fpgacore_v of bscan_fpgacore
-- Compiling entity bscan_spartan2
-- Compiling architecture bscan_spartan2_v of bscan_spartan2
-- Compiling entity bscan_spartan3
-- Compiling architecture bscan_spartan3_v of bscan_spartan3
-- Compiling entity bscan_virtex
-- Compiling architecture bscan_virtex_v of bscan_virtex
-- Compiling entity bscan_virtex2
-- Compiling architecture bscan_virtex2_v of bscan_virtex2
-- Compiling entity buf
-- Compiling architecture buf_v of buf
-- Compiling entity bufcf
-- Compiling architecture bufcf_v of bufcf
-- Compiling entity bufe
-- Compiling architecture bufe_v of bufe
-- Compiling entity bufg
-- Compiling architecture bufg_v of bufg
-- Loading package vcomponents
-- Compiling entity bufgce
-- Compiling architecture bufgce_v of bufgce
-- Compiling entity bufgce_1
-- Compiling architecture bufgce_1_v of bufgce_1
-- Compiling entity bufgdll
-- Compiling architecture bufgdll_v of bufgdll
-- Loading package vital_timing
-- Loading package vital_primitives
-- Compiling entity bufgmux
-- Compiling architecture bufgmux_v of bufgmux
-- Compiling entity bufgmux_1
-- Compiling architecture bufgmux_1_v of bufgmux_1
-- Compiling entity bufgp
-- Compiling architecture bufgp_v of bufgp
-- Compiling entity buft
-- Compiling architecture buft_v of buft
-- Compiling entity capture_fpgacore
-- Compiling architecture capture_fpgacore_v of capture_fpgacore
-- Compiling entity capture_spartan2
-- Compiling architecture capture_spartan2_v of capture_spartan2
-- Compiling entity capture_spartan3
-- Compiling architecture capture_spartan3_v of capture_spartan3
-- Compiling entity capture_virtex
-- Compiling architecture capture_virtex_v of capture_virtex
-- Compiling entity capture_virtex2
-- Compiling architecture capture_virtex2_v of capture_virtex2
-- Loading package textio
-- Compiling entity clkdll_maximum_period_check
-- Compiling architecture clkdll_maximum_period_check_v of clkdll_maximum_period_check
-- Loading package vpkg
-- Compiling entity clkdll
-- Compiling architecture clkdll_v of clkdll
-- Compiling entity clkdlle_maximum_period_check
-- Compiling architecture clkdlle_maximum_period_check_v of clkdlle_maximum_period_check
-- Compiling entity clkdlle
-- Compiling architecture clkdlle_v of clkdlle
-- Compiling entity clkdllhf_maximum_period_check
-- Compiling architecture clkdllhf_maximum_period_check_v of clkdllhf_maximum_period_check
-- Compiling entity clkdllhf
-- Compiling architecture clkdllhf_v of clkdllhf
-- Compiling entity config
-- Compiling architecture config_v of config
-- Compiling entity dcm_clock_divide_by_2
-- Compiling architecture dcm_clock_divide_by_2_v of dcm_clock_divide_by_2
-- Compiling entity dcm_maximum_period_check
-- Compiling architecture dcm_maximum_period_check_v of dcm_maximum_period_check
-- Compiling entity dcm_clock_lost
-- Compiling architecture dcm_clock_lost_v of dcm_clock_lost
-- Compiling entity dcm
-- Compiling architecture new_dcm_v of dcm
-- Compiling architecture dcm_v of dcm
-- Loading entity dcm
-- Compiling entity dcm_sp_clock_divide_by_2
-- Compiling architecture dcm_sp_clock_divide_by_2_v of dcm_sp_clock_divide_by_2
-- Compiling entity dcm_sp_maximum_period_check
-- Compiling architecture dcm_sp_maximum_period_check_v of dcm_sp_maximum_period_check
-- Compiling entity dcm_sp_clock_lost
-- Compiling architecture dcm_sp_clock_lost_v of dcm_sp_clock_lost
-- Compiling entity dcm_sp
-- Compiling architecture dcm_sp_v of dcm_sp
-- Compiling entity fd
-- Compiling architecture fd_v of fd
-- Compiling entity fd_1
-- Compiling architecture fd_1_v of fd_1
-- Compiling entity fdc
-- Compiling architecture fdc_v of fdc
-- Compiling entity fdc_1
-- Compiling architecture fdc_1_v of fdc_1
-- Compiling entity fdce
-- Compiling architecture fdce_v of fdce
-- Compiling entity fdce_1
-- Compiling architecture fdce_1_v of fdce_1
-- Compiling entity fdcp
-- Compiling architecture fdcp_v of fdcp
-- Compiling entity fdcp_1
-- Compiling architecture fdcp_1_v of fdcp_1
-- Compiling entity fdcpe
-- Compiling architecture fdcpe_v of fdcpe
-- Compiling entity fdcpe_1
-- Compiling architecture fdcpe_1_v of fdcpe_1
-- Compiling entity fddrcpe
-- Compiling architecture fddrcpe_v of fddrcpe
-- Compiling entity fddrrse
-- Compiling architecture fddrrse_v of fddrrse
-- Compiling entity fde
-- Compiling architecture fde_v of fde
-- Compiling entity fde_1
-- Compiling architecture fde_1_v of fde_1
-- Compiling entity fdp
-- Compiling architecture fdp_v of fdp
-- Compiling entity fdp_1
-- Compiling architecture fdp_1_v of fdp_1
-- Compiling entity fdpe
-- Compiling architecture fdpe_v of fdpe
-- Compiling entity fdpe_1
-- Compiling architecture fdpe_1_v of fdpe_1
-- Compiling entity fdr
-- Compiling architecture fdr_v of fdr
-- Compiling entity fdr_1
-- Compiling architecture fdr_1_v of fdr_1
-- Compiling entity fdre
-- Compiling architecture fdre_v of fdre
-- Compiling entity fdre_1
-- Compiling architecture fdre_1_v of fdre_1
-- Compiling entity fdrs
-- Compiling architecture fdrs_v of fdrs
-- Compiling entity fdrs_1
-- Compiling architecture fdrs_1_v of fdrs_1
-- Compiling entity fdrse
-- Compiling architecture fdrse_v of fdrse
-- Compiling entity fdrse_1
-- Compiling architecture fdrse_1_v of fdrse_1
-- Compiling entity fds
-- Compiling architecture fds_v of fds
-- Compiling entity fds_1
-- Compiling architecture fds_1_v of fds_1
-- Compiling entity fdse
-- Compiling architecture fdse_v of fdse
-- Compiling entity fdse_1
-- Compiling architecture fdse_1_v of fdse_1
-- Compiling entity fmap
-- Compiling architecture fmap_v of fmap
-- Compiling entity gnd
-- Compiling architecture gnd_v of gnd
-- Compiling entity ibuf
-- Compiling architecture ibuf_v of ibuf
-- Compiling entity ibuf_agp
-- Compiling architecture ibuf_agp_v of ibuf_agp
-- Compiling entity ibuf_ctt
-- Compiling architecture ibuf_ctt_v of ibuf_ctt
-- Compiling entity ibuf_gtl
-- Compiling architecture ibuf_gtl_v of ibuf_gtl
-- Compiling entity ibuf_gtl_dci
-- Compiling architecture ibuf_gtl_dci_v of ibuf_gtl_dci
-- Compiling entity ibuf_gtlp
-- Compiling architecture ibuf_gtlp_v of ibuf_gtlp
-- Compiling entity ibuf_gtlp_dci
-- Compiling architecture ibuf_gtlp_dci_v of ibuf_gtlp_dci
-- Compiling entity ibuf_hstl_i
-- Compiling architecture ibuf_hstl_i_v of ibuf_hstl_i
-- Compiling entity ibuf_hstl_i_18
-- Compiling architecture ibuf_hstl_i_18_v of ibuf_hstl_i_18
-- Compiling entity ibuf_hstl_i_dci
-- Compiling architecture ibuf_hstl_i_dci_v of ibuf_hstl_i_dci
-- Compiling entity ibuf_hstl_i_dci_18
-- Compiling architecture ibuf_hstl_i_dci_18_v of ibuf_hstl_i_dci_18
-- Compiling entity ibuf_hstl_ii
-- Compiling architecture ibuf_hstl_ii_v of ibuf_hstl_ii
-- Compiling entity ibuf_hstl_ii_18
-- Compiling architecture ibuf_hstl_ii_18_v of ibuf_hstl_ii_18
-- Compiling entity ibuf_hstl_ii_dci
-- Compiling architecture ibuf_hstl_ii_dci_v of ibuf_hstl_ii_dci
-- Compiling entity ibuf_hstl_ii_dci_18
-- Compiling architecture ibuf_hstl_ii_dci_18_v of ibuf_hstl_ii_dci_18
-- Compiling entity ibuf_hstl_iii
-- Compiling architecture ibuf_hstl_iii_v of ibuf_hstl_iii
-- Compiling entity ibuf_hstl_iii_18
-- Compiling architecture ibuf_hstl_iii_18_v of ibuf_hstl_iii_18
-- Compiling entity ibuf_hstl_iii_dci
-- Compiling architecture ibuf_hstl_iii_dci_v of ibuf_hstl_iii_dci
-- Compiling entity ibuf_hstl_iii_dci_18
-- Compiling architecture ibuf_hstl_iii_dci_18_v of ibuf_hstl_iii_dci_18
-- Compiling entity ibuf_hstl_iv
-- Compiling architecture ibuf_hstl_iv_v of ibuf_hstl_iv
-- Compiling entity ibuf_hstl_iv_18
-- Compiling architecture ibuf_hstl_iv_18_v of ibuf_hstl_iv_18
-- Compiling entity ibuf_hstl_iv_dci
-- Compiling architecture ibuf_hstl_iv_dci_v of ibuf_hstl_iv_dci
-- Compiling entity ibuf_hstl_iv_dci_18
-- Compiling architecture ibuf_hstl_iv_dci_18_v of ibuf_hstl_iv_dci_18
-- Compiling entity ibuf_lvcmos12
-- Compiling architecture ibuf_lvcmos12_v of ibuf_lvcmos12
-- Compiling entity ibuf_lvcmos15
-- Compiling architecture ibuf_lvcmos15_v of ibuf_lvcmos15
-- Compiling entity ibuf_lvcmos18
-- Compiling architecture ibuf_lvcmos18_v of ibuf_lvcmos18
-- Compiling entity ibuf_lvcmos2
-- Compiling architecture ibuf_lvcmos2_v of ibuf_lvcmos2
-- Compiling entity ibuf_lvcmos25
-- Compiling architecture ibuf_lvcmos25_v of ibuf_lvcmos25
-- Compiling entity ibuf_lvcmos33
-- Compiling architecture ibuf_lvcmos33_v of ibuf_lvcmos33
-- Compiling entity ibuf_lvdci_15
-- Compiling architecture ibuf_lvdci_15_v of ibuf_lvdci_15
-- Compiling entity ibuf_lvdci_18
-- Compiling architecture ibuf_lvdci_18_v of ibuf_lvdci_18
-- Compiling entity ibuf_lvdci_25
-- Compiling architecture ibuf_lvdci_25_v of ibuf_lvdci_25
-- Compiling entity ibuf_lvdci_33
-- Compiling architecture ibuf_lvdci_33_v of ibuf_lvdci_33
-- Compiling entity ibuf_lvdci_dv2_15
-- Compiling architecture ibuf_lvdci_dv2_15_v of ibuf_lvdci_dv2_15
-- Compiling entity ibuf_lvdci_dv2_18
-- Compiling architecture ibuf_lvdci_dv2_18_v of ibuf_lvdci_dv2_18
-- Compiling entity ibuf_lvdci_dv2_25
-- Compiling architecture ibuf_lvdci_dv2_25_v of ibuf_lvdci_dv2_25
-- Compiling entity ibuf_lvdci_dv2_33
-- Compiling architecture ibuf_lvdci_dv2_33_v of ibuf_lvdci_dv2_33
-- Compiling entity ibuf_lvds
-- Compiling architecture ibuf_lvds_v of ibuf_lvds
-- Compiling entity ibuf_lvpecl
-- Compiling architecture ibuf_lvpecl_v of ibuf_lvpecl
-- Compiling entity ibuf_lvttl
-- Compiling architecture ibuf_lvttl_v of ibuf_lvttl
-- Compiling entity ibuf_pci33_3
-- Compiling architecture ibuf_pci33_3_v of ibuf_pci33_3
-- Compiling entity ibuf_pci33_5
-- Compiling architecture ibuf_pci33_5_v of ibuf_pci33_5
-- Compiling entity ibuf_pci66_3
-- Compiling architecture ibuf_pci66_3_v of ibuf_pci66_3
-- Compiling entity ibuf_pcix
-- Compiling architecture ibuf_pcix_v of ibuf_pcix
-- Compiling entity ibuf_pcix66_3
-- Compiling architecture ibuf_pcix66_3_v of ibuf_pcix66_3
-- Compiling entity ibuf_sstl18_i
-- Compiling architecture ibuf_sstl18_i_v of ibuf_sstl18_i
-- Compiling entity ibuf_sstl18_i_dci
-- Compiling architecture ibuf_sstl18_i_dci_v of ibuf_sstl18_i_dci
-- Compiling entity ibuf_sstl18_ii
-- Compiling architecture ibuf_sstl18_ii_v of ibuf_sstl18_ii
-- Compiling entity ibuf_sstl18_ii_dci
-- Compiling architecture ibuf_sstl18_ii_dci_v of ibuf_sstl18_ii_dci
-- Compiling entity ibuf_sstl2_i
-- Compiling architecture ibuf_sstl2_i_v of ibuf_sstl2_i
-- Compiling entity ibuf_sstl2_i_dci
-- Compiling architecture ibuf_sstl2_i_dci_v of ibuf_sstl2_i_dci
-- Compiling entity ibuf_sstl2_ii
-- Compiling architecture ibuf_sstl2_ii_v of ibuf_sstl2_ii
-- Compiling entity ibuf_sstl2_ii_dci
-- Compiling architecture ibuf_sstl2_ii_dci_v of ibuf_sstl2_ii_dci
-- Compiling entity ibuf_sstl3_i
-- Compiling architecture ibuf_sstl3_i_v of ibuf_sstl3_i
-- Compiling entity ibuf_sstl3_i_dci
-- Compiling architecture ibuf_sstl3_i_dci_v of ibuf_sstl3_i_dci
-- Compiling entity ibuf_sstl3_ii
-- Compiling architecture ibuf_sstl3_ii_v of ibuf_sstl3_ii
-- Compiling entity ibuf_sstl3_ii_dci
-- Compiling architecture ibuf_sstl3_ii_dci_v of ibuf_sstl3_ii_dci
-- Compiling entity ibufds
-- Compiling architecture ibufds_v of ibufds
-- Compiling entity ibufds_blvds_25
-- Compiling architecture ibufds_blvds_25_v of ibufds_blvds_25
-- Compiling entity ibufds_diff_out
-- Compiling architecture ibufds_diff_out_v of ibufds_diff_out
-- Compiling entity ibufds_ldt_25
-- Compiling architecture ibufds_ldt_25_v of ibufds_ldt_25
-- Compiling entity ibufds_lvds_25
-- Compiling architecture ibufds_lvds_25_v of ibufds_lvds_25
-- Compiling entity ibufds_lvds_25_dci
-- Compiling architecture ibufds_lvds_25_dci_v of ibufds_lvds_25_dci
-- Compiling entity ibufds_lvds_33
-- Compiling architecture ibufds_lvds_33_v of ibufds_lvds_33
-- Compiling entity ibufds_lvds_33_dci
-- Compiling architecture ibufds_lvds_33_dci_v of ibufds_lvds_33_dci
-- Compiling entity ibufds_lvdsext_25
-- Compiling architecture ibufds_lvdsext_25_v of ibufds_lvdsext_25
-- Compiling entity ibufds_lvdsext_25_dci
-- Compiling architecture ibufds_lvdsext_25_dci_v of ibufds_lvdsext_25_dci
-- Compiling entity ibufds_lvdsext_33
-- Compiling architecture ibufds_lvdsext_33_v of ibufds_lvdsext_33
-- Compiling entity ibufds_lvdsext_33_dci
-- Compiling architecture ibufds_lvdsext_33_dci_v of ibufds_lvdsext_33_dci
-- Compiling entity ibufds_lvpecl_25
-- Compiling architecture ibufds_lvpecl_25_v of ibufds_lvpecl_25
-- Compiling entity ibufds_lvpecl_33
-- Compiling architecture ibufds_lvpecl_33_v of ibufds_lvpecl_33
-- Compiling entity ibufds_ulvds_25
-- Compiling architecture ibufds_ulvds_25_v of ibufds_ulvds_25
-- Compiling entity ibufg
-- Compiling architecture ibufg_v of ibufg
-- Compiling entity ibufg_agp
-- Compiling architecture ibufg_agp_v of ibufg_agp
-- Compiling entity ibufg_ctt
-- Compiling architecture ibufg_ctt_v of ibufg_ctt
-- Compiling entity ibufg_gtl
-- Compiling architecture ibufg_gtl_v of ibufg_gtl
-- Compiling entity ibufg_gtl_dci
-- Compiling architecture ibufg_gtl_dci_v of ibufg_gtl_dci
-- Compiling entity ibufg_gtlp
-- Compiling architecture ibufg_gtlp_v of ibufg_gtlp
-- Compiling entity ibufg_gtlp_dci
-- Compiling architecture ibufg_gtlp_dci_v of ibufg_gtlp_dci
-- Compiling entity ibufg_hstl_i
-- Compiling architecture ibufg_hstl_i_v of ibufg_hstl_i
-- Compiling entity ibufg_hstl_i_18
-- Compiling architecture ibufg_hstl_i_18_v of ibufg_hstl_i_18
-- Compiling entity ibufg_hstl_i_dci
-- Compiling architecture ibufg_hstl_i_dci_v of ibufg_hstl_i_dci
-- Compiling entity ibufg_hstl_i_dci_18
-- Compiling architecture ibufg_hstl_i_dci_18_v of ibufg_hstl_i_dci_18
-- Compiling entity ibufg_hstl_ii
-- Compiling architecture ibufg_hstl_ii_v of ibufg_hstl_ii
-- Compiling entity ibufg_hstl_ii_18
-- Compiling architecture ibufg_hstl_ii_18_v of ibufg_hstl_ii_18
-- Compiling entity ibufg_hstl_ii_dci
-- Compiling architecture ibufg_hstl_ii_dci_v of ibufg_hstl_ii_dci
-- Compiling entity ibufg_hstl_ii_dci_18
-- Compiling architecture ibufg_hstl_ii_dci_18_v of ibufg_hstl_ii_dci_18
-- Compiling entity ibufg_hstl_iii
-- Compiling architecture ibufg_hstl_iii_v of ibufg_hstl_iii
-- Compiling entity ibufg_hstl_iii_18
-- Compiling architecture ibufg_hstl_iii_18_v of ibufg_hstl_iii_18
-- Compiling entity ibufg_hstl_iii_dci
-- Compiling architecture ibufg_hstl_iii_dci_v of ibufg_hstl_iii_dci
-- Compiling entity ibufg_hstl_iii_dci_18
-- Compiling architecture ibufg_hstl_iii_dci_18_v of ibufg_hstl_iii_dci_18
-- Compiling entity ibufg_hstl_iv
-- Compiling architecture ibufg_hstl_iv_v of ibufg_hstl_iv
-- Compiling entity ibufg_hstl_iv_18
-- Compiling architecture ibufg_hstl_iv_18_v of ibufg_hstl_iv_18
-- Compiling entity ibufg_hstl_iv_dci
-- Compiling architecture ibufg_hstl_iv_dci_v of ibufg_hstl_iv_dci
-- Compiling entity ibufg_hstl_iv_dci_18
-- Compiling architecture ibufg_hstl_iv_dci_18_v of ibufg_hstl_iv_dci_18
-- Compiling entity ibufg_lvcmos12
-- Compiling architecture ibufg_lvcmos12_v of ibufg_lvcmos12
-- Compiling entity ibufg_lvcmos15
-- Compiling architecture ibufg_lvcmos15_v of ibufg_lvcmos15
-- Compiling entity ibufg_lvcmos18
-- Compiling architecture ibufg_lvcmos18_v of ibufg_lvcmos18
-- Compiling entity ibufg_lvcmos2
-- Compiling architecture ibufg_lvcmos2_v of ibufg_lvcmos2
-- Compiling entity ibufg_lvcmos25
-- Compiling architecture ibufg_lvcmos25_v of ibufg_lvcmos25
-- Compiling entity ibufg_lvcmos33
-- Compiling architecture ibufg_lvcmos33_v of ibufg_lvcmos33
-- Compiling entity ibufg_lvdci_15
-- Compiling architecture ibufg_lvdci_15_v of ibufg_lvdci_15
-- Compiling entity ibufg_lvdci_18
-- Compiling architecture ibufg_lvdci_18_v of ibufg_lvdci_18
-- Compiling entity ibufg_lvdci_25
-- Compiling architecture ibufg_lvdci_25_v of ibufg_lvdci_25
-- Compiling entity ibufg_lvdci_33
-- Compiling architecture ibufg_lvdci_33_v of ibufg_lvdci_33
-- Compiling entity ibufg_lvdci_dv2_15
-- Compiling architecture ibufg_lvdci_dv2_15_v of ibufg_lvdci_dv2_15
-- Compiling entity ibufg_lvdci_dv2_18
-- Compiling architecture ibufg_lvdci_dv2_18_v of ibufg_lvdci_dv2_18
-- Compiling entity ibufg_lvdci_dv2_25
-- Compiling architecture ibufg_lvdci_dv2_25_v of ibufg_lvdci_dv2_25
-- Compiling entity ibufg_lvdci_dv2_33
-- Compiling architecture ibufg_lvdci_dv2_33_v of ibufg_lvdci_dv2_33
-- Compiling entity ibufg_lvds
-- Compiling architecture ibufg_lvds_v of ibufg_lvds
-- Compiling entity ibufg_lvpecl
-- Compiling architecture ibufg_lvpecl_v of ibufg_lvpecl
-- Compiling entity ibufg_lvttl
-- Compiling architecture ibufg_lvttl_v of ibufg_lvttl
-- Compiling entity ibufg_pci33_3
-- Compiling architecture ibufg_pci33_3_v of ibufg_pci33_3
-- Compiling entity ibufg_pci33_5
-- Compiling architecture ibufg_pci33_5_v of ibufg_pci33_5
-- Compiling entity ibufg_pci66_3
-- Compiling architecture ibufg_pci66_3_v of ibufg_pci66_3
-- Compiling entity ibufg_pcix
-- Compiling architecture ibufg_pcix_v of ibufg_pcix
-- Compiling entity ibufg_pcix66_3
-- Compiling architecture ibufg_pcix66_3_v of ibufg_pcix66_3
-- Compiling entity ibufg_sstl18_i
-- Compiling architecture ibufg_sstl18_i_v of ibufg_sstl18_i
-- Compiling entity ibufg_sstl18_i_dci
-- Compiling architecture ibufg_sstl18_i_dci_v of ibufg_sstl18_i_dci
-- Compiling entity ibufg_sstl18_ii
-- Compiling architecture ibufg_sstl18_ii_v of ibufg_sstl18_ii
-- Compiling entity ibufg_sstl18_ii_dci
-- Compiling architecture ibufg_sstl18_ii_dci_v of ibufg_sstl18_ii_dci
-- Compiling entity ibufg_sstl2_i
-- Compiling architecture ibufg_sstl2_i_v of ibufg_sstl2_i
-- Compiling entity ibufg_sstl2_i_dci
-- Compiling architecture ibufg_sstl2_i_dci_v of ibufg_sstl2_i_dci
-- Compiling entity ibufg_sstl2_ii
-- Compiling architecture ibufg_sstl2_ii_v of ibufg_sstl2_ii
-- Compiling entity ibufg_sstl2_ii_dci
-- Compiling architecture ibufg_sstl2_ii_dci_v of ibufg_sstl2_ii_dci
-- Compiling entity ibufg_sstl3_i
-- Compiling architecture ibufg_sstl3_i_v of ibufg_sstl3_i
-- Compiling entity ibufg_sstl3_i_dci
-- Compiling architecture ibufg_sstl3_i_dci_v of ibufg_sstl3_i_dci
-- Compiling entity ibufg_sstl3_ii
-- Compiling architecture ibufg_sstl3_ii_v of ibufg_sstl3_ii
-- Compiling entity ibufg_sstl3_ii_dci
-- Compiling architecture ibufg_sstl3_ii_dci_v of ibufg_sstl3_ii_dci
-- Compiling entity ibufgds
-- Compiling architecture ibufgds_v of ibufgds
-- Compiling entity ibufgds_blvds_25
-- Compiling architecture ibufgds_blvds_25_v of ibufgds_blvds_25
-- Compiling entity ibufgds_diff_out
-- Compiling architecture ibufgds_diff_out_v of ibufgds_diff_out
-- Compiling entity ibufgds_ldt_25
-- Compiling architecture ibufgds_ldt_25_v of ibufgds_ldt_25
-- Compiling entity ibufgds_lvds_25
-- Compiling architecture ibufgds_lvds_25_v of ibufgds_lvds_25
-- Compiling entity ibufgds_lvds_25_dci
-- Compiling architecture ibufgds_lvds_25_dci_v of ibufgds_lvds_25_dci
-- Compiling entity ibufgds_lvds_33
-- Compiling architecture ibufgds_lvds_33_v of ibufgds_lvds_33
-- Compiling entity ibufgds_lvds_33_dci
-- Compiling architecture ibufgds_lvds_33_dci_v of ibufgds_lvds_33_dci
-- Compiling entity ibufgds_lvdsext_25
-- Compiling architecture ibufgds_lvdsext_25_v of ibufgds_lvdsext_25
-- Compiling entity ibufgds_lvdsext_25_dci
-- Compiling architecture ibufgds_lvdsext_25_dci_v of ibufgds_lvdsext_25_dci
-- Compiling entity ibufgds_lvdsext_33
-- Compiling architecture ibufgds_lvdsext_33_v of ibufgds_lvdsext_33
-- Compiling entity ibufgds_lvdsext_33_dci
-- Compiling architecture ibufgds_lvdsext_33_dci_v of ibufgds_lvdsext_33_dci
-- Compiling entity ibufgds_lvpecl_25
-- Compiling architecture ibufgds_lvpecl_25_v of ibufgds_lvpecl_25
-- Compiling entity ibufgds_lvpecl_33
-- Compiling architecture ibufgds_lvpecl_33_v of ibufgds_lvpecl_33
-- Compiling entity ibufgds_ulvds_25
-- Compiling architecture ibufgds_ulvds_25_v of ibufgds_ulvds_25
-- Compiling entity icap_virtex2
-- Compiling architecture icap_virtex2_v of icap_virtex2
-- Compiling entity ifddrcpe
-- Compiling architecture ifddrcpe_v of ifddrcpe
-- Compiling entity ifddrrse
-- Compiling architecture ifddrrse_v of ifddrrse
-- Compiling entity inv
-- Compiling architecture inv_v of inv
-- Compiling entity iobuf
-- Compiling architecture iobuf_v of iobuf
-- Compiling entity iobuf_agp
-- Compiling architecture iobuf_agp_v of iobuf_agp
-- Compiling entity iobuf_ctt
-- Compiling architecture iobuf_ctt_v of iobuf_ctt
-- Compiling entity iobuf_f_12
-- Compiling architecture iobuf_f_12_v of iobuf_f_12
-- Compiling entity iobuf_f_16
-- Compiling architecture iobuf_f_16_v of iobuf_f_16
-- Compiling entity iobuf_f_2
-- Compiling architecture iobuf_f_2_v of iobuf_f_2
-- Compiling entity iobuf_f_24
-- Compiling architecture iobuf_f_24_v of iobuf_f_24
-- Compiling entity iobuf_f_4
-- Compiling architecture iobuf_f_4_v of iobuf_f_4
-- Compiling entity iobuf_f_6
-- Compiling architecture iobuf_f_6_v of iobuf_f_6
-- Compiling entity iobuf_f_8
-- Compiling architecture iobuf_f_8_v of iobuf_f_8
-- Compiling entity iobuf_gtl
-- Compiling architecture iobuf_gtl_v of iobuf_gtl
-- Compiling entity iobuf_gtl_dci
-- Compiling architecture iobuf_gtl_dci_v of iobuf_gtl_dci
-- Compiling entity iobuf_gtlp
-- Compiling architecture iobuf_gtlp_v of iobuf_gtlp
-- Compiling entity iobuf_gtlp_dci
-- Compiling architecture iobuf_gtlp_dci_v of iobuf_gtlp_dci
-- Compiling entity iobuf_hstl_i
-- Compiling architecture iobuf_hstl_i_v of iobuf_hstl_i
-- Compiling entity iobuf_hstl_i_18
-- Compiling architecture iobuf_hstl_i_18_v of iobuf_hstl_i_18
-- Compiling entity iobuf_hstl_ii
-- Compiling architecture iobuf_hstl_ii_v of iobuf_hstl_ii
-- Compiling entity iobuf_hstl_ii_18
-- Compiling architecture iobuf_hstl_ii_18_v of iobuf_hstl_ii_18
-- Compiling entity iobuf_hstl_ii_dci
-- Compiling architecture iobuf_hstl_ii_dci_v of iobuf_hstl_ii_dci
-- Compiling entity iobuf_hstl_ii_dci_18
-- Compiling architecture iobuf_hstl_ii_dci_18_v of iobuf_hstl_ii_dci_18
-- Compiling entity iobuf_hstl_iii
-- Compiling architecture iobuf_hstl_iii_v of iobuf_hstl_iii
-- Compiling entity iobuf_hstl_iii_18
-- Compiling architecture iobuf_hstl_iii_18_v of iobuf_hstl_iii_18
-- Compiling entity iobuf_hstl_iv
-- Compiling architecture iobuf_hstl_iv_v of iobuf_hstl_iv
-- Compiling entity iobuf_hstl_iv_18
-- Compiling architecture iobuf_hstl_iv_18_v of iobuf_hstl_iv_18
-- Compiling entity iobuf_hstl_iv_dci
-- Compiling architecture iobuf_hstl_iv_dci_v of iobuf_hstl_iv_dci
-- Compiling entity iobuf_hstl_iv_dci_18
-- Compiling architecture iobuf_hstl_iv_dci_18_v of iobuf_hstl_iv_dci_18
-- Compiling entity iobuf_lvcmos12
-- Compiling architecture iobuf_lvcmos12_v of iobuf_lvcmos12
-- Compiling entity iobuf_lvcmos12_f_2
-- Compiling architecture iobuf_lvcmos12_f_2_v of iobuf_lvcmos12_f_2
-- Compiling entity iobuf_lvcmos12_f_4
-- Compiling architecture iobuf_lvcmos12_f_4_v of iobuf_lvcmos12_f_4
-- Compiling entity iobuf_lvcmos12_f_6
-- Compiling architecture iobuf_lvcmos12_f_6_v of iobuf_lvcmos12_f_6
-- Compiling entity iobuf_lvcmos12_f_8
-- Compiling architecture iobuf_lvcmos12_f_8_v of iobuf_lvcmos12_f_8
-- Compiling entity iobuf_lvcmos12_s_2
-- Compiling architecture iobuf_lvcmos12_s_2_v of iobuf_lvcmos12_s_2
-- Compiling entity iobuf_lvcmos12_s_4
-- Compiling architecture iobuf_lvcmos12_s_4_v of iobuf_lvcmos12_s_4
-- Compiling entity iobuf_lvcmos12_s_6
-- Compiling architecture iobuf_lvcmos12_s_6_v of iobuf_lvcmos12_s_6
-- Compiling entity iobuf_lvcmos12_s_8
-- Compiling architecture iobuf_lvcmos12_s_8_v of iobuf_lvcmos12_s_8
-- Compiling entity iobuf_lvcmos15
-- Compiling architecture iobuf_lvcmos15_v of iobuf_lvcmos15
-- Compiling entity iobuf_lvcmos15_f_12
-- Compiling architecture iobuf_lvcmos15_f_12_v of iobuf_lvcmos15_f_12
-- Compiling entity iobuf_lvcmos15_f_16
-- Compiling architecture iobuf_lvcmos15_f_16_v of iobuf_lvcmos15_f_16
-- Compiling entity iobuf_lvcmos15_f_2
-- Compiling architecture iobuf_lvcmos15_f_2_v of iobuf_lvcmos15_f_2
-- Compiling entity iobuf_lvcmos15_f_4
-- Compiling architecture iobuf_lvcmos15_f_4_v of iobuf_lvcmos15_f_4
-- Compiling entity iobuf_lvcmos15_f_6
-- Compiling architecture iobuf_lvcmos15_f_6_v of iobuf_lvcmos15_f_6
-- Compiling entity iobuf_lvcmos15_f_8
-- Compiling architecture iobuf_lvcmos15_f_8_v of iobuf_lvcmos15_f_8
-- Compiling entity iobuf_lvcmos15_s_12
-- Compiling architecture iobuf_lvcmos15_s_12_v of iobuf_lvcmos15_s_12
-- Compiling entity iobuf_lvcmos15_s_16
-- Compiling architecture iobuf_lvcmos15_s_16_v of iobuf_lvcmos15_s_16
-- Compiling entity iobuf_lvcmos15_s_2
-- Compiling architecture iobuf_lvcmos15_s_2_v of iobuf_lvcmos15_s_2
-- Compiling entity iobuf_lvcmos15_s_4
-- Compiling architecture iobuf_lvcmos15_s_4_v of iobuf_lvcmos15_s_4
-- Compiling entity iobuf_lvcmos15_s_6
-- Compiling architecture iobuf_lvcmos15_s_6_v of iobuf_lvcmos15_s_6
-- Compiling entity iobuf_lvcmos15_s_8
-- Compiling architecture iobuf_lvcmos15_s_8_v of iobuf_lvcmos15_s_8
-- Compiling entity iobuf_lvcmos18
-- Compiling architecture iobuf_lvcmos18_v of iobuf_lvcmos18
-- Compiling entity iobuf_lvcmos18_f_12
-- Compiling architecture iobuf_lvcmos18_f_12_v of iobuf_lvcmos18_f_12
-- Compiling entity iobuf_lvcmos18_f_16
-- Compiling architecture iobuf_lvcmos18_f_16_v of iobuf_lvcmos18_f_16
-- Compiling entity iobuf_lvcmos18_f_2
-- Compiling architecture iobuf_lvcmos18_f_2_v of iobuf_lvcmos18_f_2
-- Compiling entity iobuf_lvcmos18_f_4
-- Compiling architecture iobuf_lvcmos18_f_4_v of iobuf_lvcmos18_f_4
-- Compiling entity iobuf_lvcmos18_f_6
-- Compiling architecture iobuf_lvcmos18_f_6_v of iobuf_lvcmos18_f_6
-- Compiling entity iobuf_lvcmos18_f_8
-- Compiling architecture iobuf_lvcmos18_f_8_v of iobuf_lvcmos18_f_8
-- Compiling entity iobuf_lvcmos18_s_12
-- Compiling architecture iobuf_lvcmos18_s_12_v of iobuf_lvcmos18_s_12
-- Compiling entity iobuf_lvcmos18_s_16
-- Compiling architecture iobuf_lvcmos18_s_16_v of iobuf_lvcmos18_s_16
-- Compiling entity iobuf_lvcmos18_s_2
-- Compiling architecture iobuf_lvcmos18_s_2_v of iobuf_lvcmos18_s_2
-- Compiling entity iobuf_lvcmos18_s_4
-- Compiling architecture iobuf_lvcmos18_s_4_v of iobuf_lvcmos18_s_4
-- Compiling entity iobuf_lvcmos18_s_6
-- Compiling architecture iobuf_lvcmos18_s_6_v of iobuf_lvcmos18_s_6
-- Compiling entity iobuf_lvcmos18_s_8
-- Compiling architecture iobuf_lvcmos18_s_8_v of iobuf_lvcmos18_s_8
-- Compiling entity iobuf_lvcmos2
-- Compiling architecture iobuf_lvcmos2_v of iobuf_lvcmos2
-- Compiling entity iobuf_lvcmos25
-- Compiling architecture iobuf_lvcmos25_v of iobuf_lvcmos25
-- Compiling entity iobuf_lvcmos25_f_12
-- Compiling architecture iobuf_lvcmos25_f_12_v of iobuf_lvcmos25_f_12
-- Compiling entity iobuf_lvcmos25_f_16
-- Compiling architecture iobuf_lvcmos25_f_16_v of iobuf_lvcmos25_f_16
-- Compiling entity iobuf_lvcmos25_f_2
-- Compiling architecture iobuf_lvcmos25_f_2_v of iobuf_lvcmos25_f_2
-- Compiling entity iobuf_lvcmos25_f_24
-- Compiling architecture iobuf_lvcmos25_f_24_v of iobuf_lvcmos25_f_24
-- Compiling entity iobuf_lvcmos25_f_4
-- Compiling architecture iobuf_lvcmos25_f_4_v of iobuf_lvcmos25_f_4
-- Compiling entity iobuf_lvcmos25_f_6
-- Compiling architecture iobuf_lvcmos25_f_6_v of iobuf_lvcmos25_f_6
-- Compiling entity iobuf_lvcmos25_f_8
-- Compiling architecture iobuf_lvcmos25_f_8_v of iobuf_lvcmos25_f_8
-- Compiling entity iobuf_lvcmos25_s_12
-- Compiling architecture iobuf_lvcmos25_s_12_v of iobuf_lvcmos25_s_12
-- Compiling entity iobuf_lvcmos25_s_16
-- Compiling architecture iobuf_lvcmos25_s_16_v of iobuf_lvcmos25_s_16
-- Compiling entity iobuf_lvcmos25_s_2
-- Compiling architecture iobuf_lvcmos25_s_2_v of iobuf_lvcmos25_s_2
-- Compiling entity iobuf_lvcmos25_s_24
-- Compiling architecture iobuf_lvcmos25_s_24_v of iobuf_lvcmos25_s_24
-- Compiling entity iobuf_lvcmos25_s_4
-- Compiling architecture iobuf_lvcmos25_s_4_v of iobuf_lvcmos25_s_4
-- Compiling entity iobuf_lvcmos25_s_6
-- Compiling architecture iobuf_lvcmos25_s_6_v of iobuf_lvcmos25_s_6
-- Compiling entity iobuf_lvcmos25_s_8
-- Compiling architecture iobuf_lvcmos25_s_8_v of iobuf_lvcmos25_s_8
-- Compiling entity iobuf_lvcmos33
-- Compiling architecture iobuf_lvcmos33_v of iobuf_lvcmos33
-- Compiling entity iobuf_lvcmos33_f_12
-- Compiling architecture iobuf_lvcmos33_f_12_v of iobuf_lvcmos33_f_12
-- Compiling entity iobuf_lvcmos33_f_16
-- Compiling architecture iobuf_lvcmos33_f_16_v of iobuf_lvcmos33_f_16
-- Compiling entity iobuf_lvcmos33_f_2
-- Compiling architecture iobuf_lvcmos33_f_2_v of iobuf_lvcmos33_f_2
-- Compiling entity iobuf_lvcmos33_f_24
-- Compiling architecture iobuf_lvcmos33_f_24_v of iobuf_lvcmos33_f_24
-- Compiling entity iobuf_lvcmos33_f_4
-- Compiling architecture iobuf_lvcmos33_f_4_v of iobuf_lvcmos33_f_4
-- Compiling entity iobuf_lvcmos33_f_6
-- Compiling architecture iobuf_lvcmos33_f_6_v of iobuf_lvcmos33_f_6
-- Compiling entity iobuf_lvcmos33_f_8
-- Compiling architecture iobuf_lvcmos33_f_8_v of iobuf_lvcmos33_f_8
-- Compiling entity iobuf_lvcmos33_s_12
-- Compiling architecture iobuf_lvcmos33_s_12_v of iobuf_lvcmos33_s_12
-- Compiling entity iobuf_lvcmos33_s_16
-- Compiling architecture iobuf_lvcmos33_s_16_v of iobuf_lvcmos33_s_16
-- Compiling entity iobuf_lvcmos33_s_2
-- Compiling architecture iobuf_lvcmos33_s_2_v of iobuf_lvcmos33_s_2
-- Compiling entity iobuf_lvcmos33_s_24
-- Compiling architecture iobuf_lvcmos33_s_24_v of iobuf_lvcmos33_s_24
-- Compiling entity iobuf_lvcmos33_s_4
-- Compiling architecture iobuf_lvcmos33_s_4_v of iobuf_lvcmos33_s_4
-- Compiling entity iobuf_lvcmos33_s_6
-- Compiling architecture iobuf_lvcmos33_s_6_v of iobuf_lvcmos33_s_6
-- Compiling entity iobuf_lvcmos33_s_8
-- Compiling architecture iobuf_lvcmos33_s_8_v of iobuf_lvcmos33_s_8
-- Compiling entity iobuf_lvdci_15
-- Compiling architecture iobuf_lvdci_15_v of iobuf_lvdci_15
-- Compiling entity iobuf_lvdci_18
-- Compiling architecture iobuf_lvdci_18_v of iobuf_lvdci_18
-- Compiling entity iobuf_lvdci_25
-- Compiling architecture iobuf_lvdci_25_v of iobuf_lvdci_25
-- Compiling entity iobuf_lvdci_33
-- Compiling architecture iobuf_lvdci_33_v of iobuf_lvdci_33
-- Compiling entity iobuf_lvdci_dv2_15
-- Compiling architecture iobuf_lvdci_dv2_15_v of iobuf_lvdci_dv2_15
-- Compiling entity iobuf_lvdci_dv2_18
-- Compiling architecture iobuf_lvdci_dv2_18_v of iobuf_lvdci_dv2_18
-- Compiling entity iobuf_lvdci_dv2_25
-- Compiling architecture iobuf_lvdci_dv2_25_v of iobuf_lvdci_dv2_25
-- Compiling entity iobuf_lvdci_dv2_33
-- Compiling architecture iobuf_lvdci_dv2_33_v of iobuf_lvdci_dv2_33
-- Compiling entity iobuf_lvds
-- Compiling architecture iobuf_lvds_v of iobuf_lvds
-- Compiling entity iobuf_lvpecl
-- Compiling architecture iobuf_lvpecl_v of iobuf_lvpecl
-- Compiling entity iobuf_lvttl
-- Compiling architecture iobuf_lvttl_v of iobuf_lvttl
-- Compiling entity iobuf_lvttl_f_12
-- Compiling architecture iobuf_lvttl_f_12_v of iobuf_lvttl_f_12
-- Compiling entity iobuf_lvttl_f_16
-- Compiling architecture iobuf_lvttl_f_16_v of iobuf_lvttl_f_16
-- Compiling entity iobuf_lvttl_f_2
-- Compiling architecture iobuf_lvttl_f_2_v of iobuf_lvttl_f_2
-- Compiling entity iobuf_lvttl_f_24
-- Compiling architecture iobuf_lvttl_f_24_v of iobuf_lvttl_f_24
-- Compiling entity iobuf_lvttl_f_4
-- Compiling architecture iobuf_lvttl_f_4_v of iobuf_lvttl_f_4
-- Compiling entity iobuf_lvttl_f_6
-- Compiling architecture iobuf_lvttl_f_6_v of iobuf_lvttl_f_6
-- Compiling entity iobuf_lvttl_f_8
-- Compiling architecture iobuf_lvttl_f_8_v of iobuf_lvttl_f_8
-- Compiling entity iobuf_lvttl_s_12
-- Compiling architecture iobuf_lvttl_s_12_v of iobuf_lvttl_s_12
-- Compiling entity iobuf_lvttl_s_16
-- Compiling architecture iobuf_lvttl_s_16_v of iobuf_lvttl_s_16
-- Compiling entity iobuf_lvttl_s_2
-- Compiling architecture iobuf_lvttl_s_2_v of iobuf_lvttl_s_2
-- Compiling entity iobuf_lvttl_s_24
-- Compiling architecture iobuf_lvttl_s_24_v of iobuf_lvttl_s_24
-- Compiling entity iobuf_lvttl_s_4
-- Compiling architecture iobuf_lvttl_s_4_v of iobuf_lvttl_s_4
-- Compiling entity iobuf_lvttl_s_6
-- Compiling architecture iobuf_lvttl_s_6_v of iobuf_lvttl_s_6
-- Compiling entity iobuf_lvttl_s_8
-- Compiling architecture iobuf_lvttl_s_8_v of iobuf_lvttl_s_8
-- Compiling entity iobuf_pci33_3
-- Compiling architecture iobuf_pci33_3_v of iobuf_pci33_3
-- Compiling entity iobuf_pci33_5
-- Compiling architecture iobuf_pci33_5_v of iobuf_pci33_5
-- Compiling entity iobuf_pci66_3
-- Compiling architecture iobuf_pci66_3_v of iobuf_pci66_3
-- Compiling entity iobuf_pcix
-- Compiling architecture iobuf_pcix_v of iobuf_pcix
-- Compiling entity iobuf_pcix66_3
-- Compiling architecture iobuf_pcix66_3_v of iobuf_pcix66_3
-- Compiling entity iobuf_s_12
-- Compiling architecture iobuf_s_12_v of iobuf_s_12
-- Compiling entity iobuf_s_16
-- Compiling architecture iobuf_s_16_v of iobuf_s_16
-- Compiling entity iobuf_s_2
-- Compiling architecture iobuf_s_2_v of iobuf_s_2
-- Compiling entity iobuf_s_24
-- Compiling architecture iobuf_s_24_v of iobuf_s_24
-- Compiling entity iobuf_s_4
-- Compiling architecture iobuf_s_4_v of iobuf_s_4
-- Compiling entity iobuf_s_6
-- Compiling architecture iobuf_s_6_v of iobuf_s_6
-- Compiling entity iobuf_s_8
-- Compiling architecture iobuf_s_8_v of iobuf_s_8
-- Compiling entity iobuf_sstl18_i
-- Compiling architecture iobuf_sstl18_i_v of iobuf_sstl18_i
-- Compiling entity iobuf_sstl18_ii
-- Compiling architecture iobuf_sstl18_ii_v of iobuf_sstl18_ii
-- Compiling entity iobuf_sstl18_ii_dci
-- Compiling architecture iobuf_sstl18_ii_dci_v of iobuf_sstl18_ii_dci
-- Compiling entity iobuf_sstl2_i
-- Compiling architecture iobuf_sstl2_i_v of iobuf_sstl2_i
-- Compiling entity iobuf_sstl2_ii
-- Compiling architecture iobuf_sstl2_ii_v of iobuf_sstl2_ii
-- Compiling entity iobuf_sstl2_ii_dci
-- Compiling architecture iobuf_sstl2_ii_dci_v of iobuf_sstl2_ii_dci
-- Compiling entity iobuf_sstl3_i
-- Compiling architecture iobuf_sstl3_i_v of iobuf_sstl3_i
-- Compiling entity iobuf_sstl3_ii
-- Compiling architecture iobuf_sstl3_ii_v of iobuf_sstl3_ii
-- Compiling entity iobuf_sstl3_ii_dci
-- Compiling architecture iobuf_sstl3_ii_dci_v of iobuf_sstl3_ii_dci
-- Compiling entity iobufds
-- Compiling architecture iobufds_v of iobufds
-- Compiling entity iobufds_blvds_25
-- Compiling architecture iobufds_blvds_25_v of iobufds_blvds_25
-- Compiling entity keeper
-- Compiling architecture keeper_v of keeper
-- Compiling entity ld
-- Compiling architecture ld_v of ld
-- Compiling entity ld_1
-- Compiling architecture ld_1_v of ld_1
-- Compiling entity ldc
-- Compiling architecture ldc_v of ldc
-- Compiling entity ldc_1
-- Compiling architecture ldc_1_v of ldc_1
-- Compiling entity ldce
-- Compiling architecture ldce_v of ldce
-- Compiling entity ldce_1
-- Compiling architecture ldce_1_v of ldce_1
-- Compiling entity ldcp
-- Compiling architecture ldcp_v of ldcp
-- Compiling entity ldcp_1
-- Compiling architecture ldcp_1_v of ldcp_1
-- Compiling entity ldcpe
-- Compiling architecture ldcpe_v of ldcpe
-- Compiling entity ldcpe_1
-- Compiling architecture ldcpe_1_v of ldcpe_1
-- Compiling entity lde
-- Compiling architecture lde_v of lde
-- Compiling entity lde_1
-- Compiling architecture lde_1_v of lde_1
-- Compiling entity ldp
-- Compiling architecture ldp_v of ldp
-- Compiling entity ldp_1
-- Compiling architecture ldp_1_v of ldp_1
-- Compiling entity ldpe
-- Compiling architecture ldpe_v of ldpe
-- Compiling entity ldpe_1
-- Compiling architecture ldpe_1_v of ldpe_1
-- Compiling entity lut1
-- Compiling architecture lut1_v of lut1
-- Compiling entity lut1_d
-- Compiling architecture lut1_d_v of lut1_d
-- Compiling entity lut1_l
-- Compiling architecture lut1_l_v of lut1_l
-- Compiling entity lut2
-- Compiling architecture lut2_v of lut2
-- Compiling entity lut2_d
-- Compiling architecture lut2_d_v of lut2_d
-- Compiling entity lut2_l
-- Compiling architecture lut2_l_v of lut2_l
-- Compiling entity lut3
-- Compiling architecture lut3_v of lut3
-- Compiling entity lut3_d
-- Compiling architecture lut3_d_v of lut3_d
-- Compiling entity lut3_l
-- Compiling architecture lut3_l_v of lut3_l
-- Compiling entity lut4
-- Compiling architecture lut4_v of lut4
-- Compiling entity lut4_d
-- Compiling architecture lut4_d_v of lut4_d
-- Compiling entity lut4_l
-- Compiling architecture lut4_l_v of lut4_l
-- Compiling entity mult18x18
-- Compiling architecture mult18x18_v of mult18x18
-- Compiling entity mult18x18s
-- Compiling architecture mult18x18s_v of mult18x18s
-- Compiling entity mult_and
-- Compiling architecture mult_and_v of mult_and
-- Compiling entity muxcy
-- Compiling architecture muxcy_v of muxcy
-- Compiling entity muxcy_d
-- Compiling architecture muxcy_d_v of muxcy_d
-- Compiling entity muxcy_l
-- Compiling architecture muxcy_l_v of muxcy_l
-- Compiling entity muxf5
-- Compiling architecture muxf5_v of muxf5
-- Compiling entity muxf5_d
-- Compiling architecture muxf5_d_v of muxf5_d
-- Compiling entity muxf5_l
-- Compiling architecture muxf5_l_v of muxf5_l
-- Compiling entity muxf6
-- Compiling architecture muxf6_v of muxf6
-- Compiling entity muxf6_d
-- Compiling architecture muxf6_d_v of muxf6_d
-- Compiling entity muxf6_l
-- Compiling architecture muxf6_l_v of muxf6_l
-- Compiling entity muxf7
-- Compiling architecture muxf7_v of muxf7
-- Compiling entity muxf7_d
-- Compiling architecture muxf7_d_v of muxf7_d
-- Compiling entity muxf7_l
-- Compiling architecture muxf7_l_v of muxf7_l
-- Compiling entity muxf8
-- Compiling architecture muxf8_v of muxf8
-- Compiling entity muxf8_d
-- Compiling architecture muxf8_d_v of muxf8_d
-- Compiling entity muxf8_l
-- Compiling architecture muxf8_l_v of muxf8_l
-- Compiling entity nand2
-- Compiling architecture nand2_v of nand2
-- Compiling entity nand2b1
-- Compiling architecture nand2b1_v of nand2b1
-- Compiling entity nand2b2
-- Compiling architecture nand2b2_v of nand2b2
-- Compiling entity nand3
-- Compiling architecture nand3_v of nand3
-- Compiling entity nand3b1
-- Compiling architecture nand3b1_v of nand3b1
-- Compiling entity nand3b2
-- Compiling architecture nand3b2_v of nand3b2
-- Compiling entity nand3b3
-- Compiling architecture nand3b3_v of nand3b3
-- Compiling entity nand4
-- Compiling architecture nand4_v of nand4
-- Compiling entity nand4b1
-- Compiling architecture nand4b1_v of nand4b1
-- Compiling entity nand4b2
-- Compiling architecture nand4b2_v of nand4b2
-- Compiling entity nand4b3
-- Compiling architecture nand4b3_v of nand4b3
-- Compiling entity nand4b4
-- Compiling architecture nand4b4_v of nand4b4
-- Compiling entity nand5
-- Compiling architecture nand5_v of nand5
-- Compiling entity nand5b1
-- Compiling architecture nand5b1_v of nand5b1
-- Compiling entity nand5b2
-- Compiling architecture nand5b2_v of nand5b2
-- Compiling entity nand5b3
-- Compiling architecture nand5b3_v of nand5b3
-- Compiling entity nand5b4
-- Compiling architecture nand5b4_v of nand5b4
-- Compiling entity nand5b5
-- Compiling architecture nand5b5_v of nand5b5
-- Compiling entity nor2
-- Compiling architecture nor2_v of nor2
-- Compiling entity nor2b1
-- Compiling architecture nor2b1_v of nor2b1
-- Compiling entity nor2b2
-- Compiling architecture nor2b2_v of nor2b2
-- Compiling entity nor3
-- Compiling architecture nor3_v of nor3
-- Compiling entity nor3b1
-- Compiling architecture nor3b1_v of nor3b1
-- Compiling entity nor3b2
-- Compiling architecture nor3b2_v of nor3b2
-- Compiling entity nor3b3
-- Compiling architecture nor3b3_v of nor3b3
-- Compiling entity nor4
-- Compiling architecture nor4_v of nor4
-- Compiling entity nor4b1
-- Compiling architecture nor4b1_v of nor4b1
-- Compiling entity nor4b2
-- Compiling architecture nor4b2_v of nor4b2
-- Compiling entity nor4b3
-- Compiling architecture nor4b3_v of nor4b3
-- Compiling entity nor4b4
-- Compiling architecture nor4b4_v of nor4b4
-- Compiling entity nor5
-- Compiling architecture nor5_v of nor5
-- Compiling entity nor5b1
-- Compiling architecture nor5b1_v of nor5b1
-- Compiling entity nor5b2
-- Compiling architecture nor5b2_v of nor5b2
-- Compiling entity nor5b3
-- Compiling architecture nor5b3_v of nor5b3
-- Compiling entity nor5b4
-- Compiling architecture nor5b4_v of nor5b4
-- Compiling entity nor5b5
-- Compiling architecture nor5b5_v of nor5b5
-- Compiling entity obuf
-- Compiling architecture obuf_v of obuf
-- Compiling entity obuf_agp
-- Compiling architecture obuf_agp_v of obuf_agp
-- Compiling entity obuf_ctt
-- Compiling architecture obuf_ctt_v of obuf_ctt
-- Compiling entity obuf_f_12
-- Compiling architecture obuf_f_12_v of obuf_f_12
-- Compiling entity obuf_f_16
-- Compiling architecture obuf_f_16_v of obuf_f_16
-- Compiling entity obuf_f_2
-- Compiling architecture obuf_f_2_v of obuf_f_2
-- Compiling entity obuf_f_24
-- Compiling architecture obuf_f_24_v of obuf_f_24
-- Compiling entity obuf_f_4
-- Compiling architecture obuf_f_4_v of obuf_f_4
-- Compiling entity obuf_f_6
-- Compiling architecture obuf_f_6_v of obuf_f_6
-- Compiling entity obuf_f_8
-- Compiling architecture obuf_f_8_v of obuf_f_8
-- Compiling entity obuf_gtl
-- Compiling architecture obuf_gtl_v of obuf_gtl
-- Compiling entity obuf_gtl_dci
-- Compiling architecture obuf_gtl_dci_v of obuf_gtl_dci
-- Compiling entity obuf_gtlp
-- Compiling architecture obuf_gtlp_v of obuf_gtlp
-- Compiling entity obuf_gtlp_dci
-- Compiling architecture obuf_gtlp_dci_v of obuf_gtlp_dci
-- Compiling entity obuf_hstl_i
-- Compiling architecture obuf_hstl_i_v of obuf_hstl_i
-- Compiling entity obuf_hstl_i_18
-- Compiling architecture obuf_hstl_i_18_v of obuf_hstl_i_18
-- Compiling entity obuf_hstl_i_dci
-- Compiling architecture obuf_hstl_i_dci_v of obuf_hstl_i_dci
-- Compiling entity obuf_hstl_i_dci_18
-- Compiling architecture obuf_hstl_i_dci_18_v of obuf_hstl_i_dci_18
-- Compiling entity obuf_hstl_ii
-- Compiling architecture obuf_hstl_ii_v of obuf_hstl_ii
-- Compiling entity obuf_hstl_ii_18
-- Compiling architecture obuf_hstl_ii_18_v of obuf_hstl_ii_18
-- Compiling entity obuf_hstl_ii_dci
-- Compiling architecture obuf_hstl_ii_dci_v of obuf_hstl_ii_dci
-- Compiling entity obuf_hstl_ii_dci_18
-- Compiling architecture obuf_hstl_ii_dci_18_v of obuf_hstl_ii_dci_18
-- Compiling entity obuf_hstl_iii
-- Compiling architecture obuf_hstl_iii_v of obuf_hstl_iii
-- Compiling entity obuf_hstl_iii_18
-- Compiling architecture obuf_hstl_iii_18_v of obuf_hstl_iii_18
-- Compiling entity obuf_hstl_iii_dci
-- Compiling architecture obuf_hstl_iii_dci_v of obuf_hstl_iii_dci
-- Compiling entity obuf_hstl_iii_dci_18
-- Compiling architecture obuf_hstl_iii_dci_18_v of obuf_hstl_iii_dci_18
-- Compiling entity obuf_hstl_iv
-- Compiling architecture obuf_hstl_iv_v of obuf_hstl_iv
-- Compiling entity obuf_hstl_iv_18
-- Compiling architecture obuf_hstl_iv_18_v of obuf_hstl_iv_18
-- Compiling entity obuf_hstl_iv_dci
-- Compiling architecture obuf_hstl_iv_dci_v of obuf_hstl_iv_dci
-- Compiling entity obuf_hstl_iv_dci_18
-- Compiling architecture obuf_hstl_iv_dci_18_v of obuf_hstl_iv_dci_18
-- Compiling entity obuf_lvcmos12
-- Compiling architecture obuf_lvcmos12_v of obuf_lvcmos12
-- Compiling entity obuf_lvcmos12_f_2
-- Compiling architecture obuf_lvcmos12_f_2_v of obuf_lvcmos12_f_2
-- Compiling entity obuf_lvcmos12_f_4
-- Compiling architecture obuf_lvcmos12_f_4_v of obuf_lvcmos12_f_4
-- Compiling entity obuf_lvcmos12_f_6
-- Compiling architecture obuf_lvcmos12_f_6_v of obuf_lvcmos12_f_6
-- Compiling entity obuf_lvcmos12_f_8
-- Compiling architecture obuf_lvcmos12_f_8_v of obuf_lvcmos12_f_8
-- Compiling entity obuf_lvcmos12_s_2
-- Compiling architecture obuf_lvcmos12_s_2_v of obuf_lvcmos12_s_2
-- Compiling entity obuf_lvcmos12_s_4
-- Compiling architecture obuf_lvcmos12_s_4_v of obuf_lvcmos12_s_4
-- Compiling entity obuf_lvcmos12_s_6
-- Compiling architecture obuf_lvcmos12_s_6_v of obuf_lvcmos12_s_6
-- Compiling entity obuf_lvcmos12_s_8
-- Compiling architecture obuf_lvcmos12_s_8_v of obuf_lvcmos12_s_8
-- Compiling entity obuf_lvcmos15
-- Compiling architecture obuf_lvcmos15_v of obuf_lvcmos15
-- Compiling entity obuf_lvcmos15_f_12
-- Compiling architecture obuf_lvcmos15_f_12_v of obuf_lvcmos15_f_12
-- Compiling entity obuf_lvcmos15_f_16
-- Compiling architecture obuf_lvcmos15_f_16_v of obuf_lvcmos15_f_16
-- Compiling entity obuf_lvcmos15_f_2
-- Compiling architecture obuf_lvcmos15_f_2_v of obuf_lvcmos15_f_2
-- Compiling entity obuf_lvcmos15_f_4
-- Compiling architecture obuf_lvcmos15_f_4_v of obuf_lvcmos15_f_4
-- Compiling entity obuf_lvcmos15_f_6
-- Compiling architecture obuf_lvcmos15_f_6_v of obuf_lvcmos15_f_6
-- Compiling entity obuf_lvcmos15_f_8
-- Compiling architecture obuf_lvcmos15_f_8_v of obuf_lvcmos15_f_8
-- Compiling entity obuf_lvcmos15_s_12
-- Compiling architecture obuf_lvcmos15_s_12_v of obuf_lvcmos15_s_12
-- Compiling entity obuf_lvcmos15_s_16
-- Compiling architecture obuf_lvcmos15_s_16_v of obuf_lvcmos15_s_16
-- Compiling entity obuf_lvcmos15_s_2
-- Compiling architecture obuf_lvcmos15_s_2_v of obuf_lvcmos15_s_2
-- Compiling entity obuf_lvcmos15_s_4
-- Compiling architecture obuf_lvcmos15_s_4_v of obuf_lvcmos15_s_4
-- Compiling entity obuf_lvcmos15_s_6
-- Compiling architecture obuf_lvcmos15_s_6_v of obuf_lvcmos15_s_6
-- Compiling entity obuf_lvcmos15_s_8
-- Compiling architecture obuf_lvcmos15_s_8_v of obuf_lvcmos15_s_8
-- Compiling entity obuf_lvcmos18
-- Compiling architecture obuf_lvcmos18_v of obuf_lvcmos18
-- Compiling entity obuf_lvcmos18_f_12
-- Compiling architecture obuf_lvcmos18_f_12_v of obuf_lvcmos18_f_12
-- Compiling entity obuf_lvcmos18_f_16
-- Compiling architecture obuf_lvcmos18_f_16_v of obuf_lvcmos18_f_16
-- Compiling entity obuf_lvcmos18_f_2
-- Compiling architecture obuf_lvcmos18_f_2_v of obuf_lvcmos18_f_2
-- Compiling entity obuf_lvcmos18_f_4
-- Compiling architecture obuf_lvcmos18_f_4_v of obuf_lvcmos18_f_4
-- Compiling entity obuf_lvcmos18_f_6
-- Compiling architecture obuf_lvcmos18_f_6_v of obuf_lvcmos18_f_6
-- Compiling entity obuf_lvcmos18_f_8
-- Compiling architecture obuf_lvcmos18_f_8_v of obuf_lvcmos18_f_8
-- Compiling entity obuf_lvcmos18_s_12
-- Compiling architecture obuf_lvcmos18_s_12_v of obuf_lvcmos18_s_12
-- Compiling entity obuf_lvcmos18_s_16
-- Compiling architecture obuf_lvcmos18_s_16_v of obuf_lvcmos18_s_16
-- Compiling entity obuf_lvcmos18_s_2
-- Compiling architecture obuf_lvcmos18_s_2_v of obuf_lvcmos18_s_2
-- Compiling entity obuf_lvcmos18_s_4
-- Compiling architecture obuf_lvcmos18_s_4_v of obuf_lvcmos18_s_4
-- Compiling entity obuf_lvcmos18_s_6
-- Compiling architecture obuf_lvcmos18_s_6_v of obuf_lvcmos18_s_6
-- Compiling entity obuf_lvcmos18_s_8
-- Compiling architecture obuf_lvcmos18_s_8_v of obuf_lvcmos18_s_8
-- Compiling entity obuf_lvcmos2
-- Compiling architecture obuf_lvcmos2_v of obuf_lvcmos2
-- Compiling entity obuf_lvcmos25
-- Compiling architecture obuf_lvcmos25_v of obuf_lvcmos25
-- Compiling entity obuf_lvcmos25_f_12
-- Compiling architecture obuf_lvcmos25_f_12_v of obuf_lvcmos25_f_12
-- Compiling entity obuf_lvcmos25_f_16
-- Compiling architecture obuf_lvcmos25_f_16_v of obuf_lvcmos25_f_16
-- Compiling entity obuf_lvcmos25_f_2
-- Compiling architecture obuf_lvcmos25_f_2_v of obuf_lvcmos25_f_2
-- Compiling entity obuf_lvcmos25_f_24
-- Compiling architecture obuf_lvcmos25_f_24_v of obuf_lvcmos25_f_24
-- Compiling entity obuf_lvcmos25_f_4
-- Compiling architecture obuf_lvcmos25_f_4_v of obuf_lvcmos25_f_4
-- Compiling entity obuf_lvcmos25_f_6
-- Compiling architecture obuf_lvcmos25_f_6_v of obuf_lvcmos25_f_6
-- Compiling entity obuf_lvcmos25_f_8
-- Compiling architecture obuf_lvcmos25_f_8_v of obuf_lvcmos25_f_8
-- Compiling entity obuf_lvcmos25_s_12
-- Compiling architecture obuf_lvcmos25_s_12_v of obuf_lvcmos25_s_12
-- Compiling entity obuf_lvcmos25_s_16
-- Compiling architecture obuf_lvcmos25_s_16_v of obuf_lvcmos25_s_16
-- Compiling entity obuf_lvcmos25_s_2
-- Compiling architecture obuf_lvcmos25_s_2_v of obuf_lvcmos25_s_2
-- Compiling entity obuf_lvcmos25_s_24
-- Compiling architecture obuf_lvcmos25_s_24_v of obuf_lvcmos25_s_24
-- Compiling entity obuf_lvcmos25_s_4
-- Compiling architecture obuf_lvcmos25_s_4_v of obuf_lvcmos25_s_4
-- Compiling entity obuf_lvcmos25_s_6
-- Compiling architecture obuf_lvcmos25_s_6_v of obuf_lvcmos25_s_6
-- Compiling entity obuf_lvcmos25_s_8
-- Compiling architecture obuf_lvcmos25_s_8_v of obuf_lvcmos25_s_8
-- Compiling entity obuf_lvcmos33
-- Compiling architecture obuf_lvcmos33_v of obuf_lvcmos33
-- Compiling entity obuf_lvcmos33_f_12
-- Compiling architecture obuf_lvcmos33_f_12_v of obuf_lvcmos33_f_12
-- Compiling entity obuf_lvcmos33_f_16
-- Compiling architecture obuf_lvcmos33_f_16_v of obuf_lvcmos33_f_16
-- Compiling entity obuf_lvcmos33_f_2
-- Compiling architecture obuf_lvcmos33_f_2_v of obuf_lvcmos33_f_2
-- Compiling entity obuf_lvcmos33_f_24
-- Compiling architecture obuf_lvcmos33_f_24_v of obuf_lvcmos33_f_24
-- Compiling entity obuf_lvcmos33_f_4
-- Compiling architecture obuf_lvcmos33_f_4_v of obuf_lvcmos33_f_4
-- Compiling entity obuf_lvcmos33_f_6
-- Compiling architecture obuf_lvcmos33_f_6_v of obuf_lvcmos33_f_6
-- Compiling entity obuf_lvcmos33_f_8
-- Compiling architecture obuf_lvcmos33_f_8_v of obuf_lvcmos33_f_8
-- Compiling entity obuf_lvcmos33_s_12
-- Compiling architecture obuf_lvcmos33_s_12_v of obuf_lvcmos33_s_12
-- Compiling entity obuf_lvcmos33_s_16
-- Compiling architecture obuf_lvcmos33_s_16_v of obuf_lvcmos33_s_16
-- Compiling entity obuf_lvcmos33_s_2
-- Compiling architecture obuf_lvcmos33_s_2_v of obuf_lvcmos33_s_2
-- Compiling entity obuf_lvcmos33_s_24
-- Compiling architecture obuf_lvcmos33_s_24_v of obuf_lvcmos33_s_24
-- Compiling entity obuf_lvcmos33_s_4
-- Compiling architecture obuf_lvcmos33_s_4_v of obuf_lvcmos33_s_4
-- Compiling entity obuf_lvcmos33_s_6
-- Compiling architecture obuf_lvcmos33_s_6_v of obuf_lvcmos33_s_6
-- Compiling entity obuf_lvcmos33_s_8
-- Compiling architecture obuf_lvcmos33_s_8_v of obuf_lvcmos33_s_8
-- Compiling entity obuf_lvdci_15
-- Compiling architecture obuf_lvdci_15_v of obuf_lvdci_15
-- Compiling entity obuf_lvdci_18
-- Compiling architecture obuf_lvdci_18_v of obuf_lvdci_18
-- Compiling entity obuf_lvdci_25
-- Compiling architecture obuf_lvdci_25_v of obuf_lvdci_25
-- Compiling entity obuf_lvdci_33
-- Compiling architecture obuf_lvdci_33_v of obuf_lvdci_33
-- Compiling entity obuf_lvdci_dv2_15
-- Compiling architecture obuf_lvdci_dv2_15_v of obuf_lvdci_dv2_15
-- Compiling entity obuf_lvdci_dv2_18
-- Compiling architecture obuf_lvdci_dv2_18_v of obuf_lvdci_dv2_18
-- Compiling entity obuf_lvdci_dv2_25
-- Compiling architecture obuf_lvdci_dv2_25_v of obuf_lvdci_dv2_25
-- Compiling entity obuf_lvdci_dv2_33
-- Compiling architecture obuf_lvdci_dv2_33_v of obuf_lvdci_dv2_33
-- Compiling entity obuf_lvds
-- Compiling architecture obuf_lvds_v of obuf_lvds
-- Compiling entity obuf_lvpecl
-- Compiling architecture obuf_lvpecl_v of obuf_lvpecl
-- Compiling entity obuf_lvttl
-- Compiling architecture obuf_lvttl_v of obuf_lvttl
-- Compiling entity obuf_lvttl_f_12
-- Compiling architecture obuf_lvttl_f_12_v of obuf_lvttl_f_12
-- Compiling entity obuf_lvttl_f_16
-- Compiling architecture obuf_lvttl_f_16_v of obuf_lvttl_f_16
-- Compiling entity obuf_lvttl_f_2
-- Compiling architecture obuf_lvttl_f_2_v of obuf_lvttl_f_2
-- Compiling entity obuf_lvttl_f_24
-- Compiling architecture obuf_lvttl_f_24_v of obuf_lvttl_f_24
-- Compiling entity obuf_lvttl_f_4
-- Compiling architecture obuf_lvttl_f_4_v of obuf_lvttl_f_4
-- Compiling entity obuf_lvttl_f_6
-- Compiling architecture obuf_lvttl_f_6_v of obuf_lvttl_f_6
-- Compiling entity obuf_lvttl_f_8
-- Compiling architecture obuf_lvttl_f_8_v of obuf_lvttl_f_8
-- Compiling entity obuf_lvttl_s_12
-- Compiling architecture obuf_lvttl_s_12_v of obuf_lvttl_s_12
-- Compiling entity obuf_lvttl_s_16
-- Compiling architecture obuf_lvttl_s_16_v of obuf_lvttl_s_16
-- Compiling entity obuf_lvttl_s_2
-- Compiling architecture obuf_lvttl_s_2_v of obuf_lvttl_s_2
-- Compiling entity obuf_lvttl_s_24
-- Compiling architecture obuf_lvttl_s_24_v of obuf_lvttl_s_24
-- Compiling entity obuf_lvttl_s_4
-- Compiling architecture obuf_lvttl_s_4_v of obuf_lvttl_s_4
-- Compiling entity obuf_lvttl_s_6
-- Compiling architecture obuf_lvttl_s_6_v of obuf_lvttl_s_6
-- Compiling entity obuf_lvttl_s_8
-- Compiling architecture obuf_lvttl_s_8_v of obuf_lvttl_s_8
-- Compiling entity obuf_pci33_3
-- Compiling architecture obuf_pci33_3_v of obuf_pci33_3
-- Compiling entity obuf_pci33_5
-- Compiling architecture obuf_pci33_5_v of obuf_pci33_5
-- Compiling entity obuf_pci66_3
-- Compiling architecture obuf_pci66_3_v of obuf_pci66_3
-- Compiling entity obuf_pcix
-- Compiling architecture obuf_pcix_v of obuf_pcix
-- Compiling entity obuf_pcix66_3
-- Compiling architecture obuf_pcix66_3_v of obuf_pcix66_3
-- Compiling entity obuf_s_12
-- Compiling architecture obuf_s_12_v of obuf_s_12
-- Compiling entity obuf_s_16
-- Compiling architecture obuf_s_16_v of obuf_s_16
-- Compiling entity obuf_s_2
-- Compiling architecture obuf_s_2_v of obuf_s_2
-- Compiling entity obuf_s_24
-- Compiling architecture obuf_s_24_v of obuf_s_24
-- Compiling entity obuf_s_4
-- Compiling architecture obuf_s_4_v of obuf_s_4
-- Compiling entity obuf_s_6
-- Compiling architecture obuf_s_6_v of obuf_s_6
-- Compiling entity obuf_s_8
-- Compiling architecture obuf_s_8_v of obuf_s_8
-- Compiling entity obuf_sstl18_i
-- Compiling architecture obuf_sstl18_i_v of obuf_sstl18_i
-- Compiling entity obuf_sstl18_i_dci
-- Compiling architecture obuf_sstl18_i_dci_v of obuf_sstl18_i_dci
-- Compiling entity obuf_sstl18_ii
-- Compiling architecture obuf_sstl18_ii_v of obuf_sstl18_ii
-- Compiling entity obuf_sstl18_ii_dci
-- Compiling architecture obuf_sstl18_ii_dci_v of obuf_sstl18_ii_dci
-- Compiling entity obuf_sstl2_i
-- Compiling architecture obuf_sstl2_i_v of obuf_sstl2_i
-- Compiling entity obuf_sstl2_i_dci
-- Compiling architecture obuf_sstl2_i_dci_v of obuf_sstl2_i_dci
-- Compiling entity obuf_sstl2_ii
-- Compiling architecture obuf_sstl2_ii_v of obuf_sstl2_ii
-- Compiling entity obuf_sstl2_ii_dci
-- Compiling architecture obuf_sstl2_ii_dci_v of obuf_sstl2_ii_dci
-- Compiling entity obuf_sstl3_i
-- Compiling architecture obuf_sstl3_i_v of obuf_sstl3_i
-- Compiling entity obuf_sstl3_i_dci
-- Compiling architecture obuf_sstl3_i_dci_v of obuf_sstl3_i_dci
-- Compiling entity obuf_sstl3_ii
-- Compiling architecture obuf_sstl3_ii_v of obuf_sstl3_ii
-- Compiling entity obuf_sstl3_ii_dci
-- Compiling architecture obuf_sstl3_ii_dci_v of obuf_sstl3_ii_dci
-- Compiling entity obufds
-- Compiling architecture obufds_v of obufds
-- Compiling entity obufds_blvds_25
-- Compiling architecture obufds_blvds_25_v of obufds_blvds_25
-- Compiling entity obufds_ldt_25
-- Compiling architecture obufds_ldt_25_v of obufds_ldt_25
-- Compiling entity obufds_lvds_25
-- Compiling architecture obufds_lvds_25_v of obufds_lvds_25
-- Compiling entity obufds_lvds_33
-- Compiling architecture obufds_lvds_33_v of obufds_lvds_33
-- Compiling entity obufds_lvdsext_25
-- Compiling architecture obufds_lvdsext_25_v of obufds_lvdsext_25
-- Compiling entity obufds_lvdsext_33
-- Compiling architecture obufds_lvdsext_33_v of obufds_lvdsext_33
-- Compiling entity obufds_lvpecl_25
-- Compiling architecture obufds_lvpecl_25_v of obufds_lvpecl_25
-- Compiling entity obufds_lvpecl_33
-- Compiling architecture obufds_lvpecl_33_v of obufds_lvpecl_33
-- Compiling entity obufds_ulvds_25
-- Compiling architecture obufds_ulvds_25_v of obufds_ulvds_25
-- Compiling entity obuft
-- Compiling architecture obuft_v of obuft
-- Compiling entity obuft_agp
-- Compiling architecture obuft_agp_v of obuft_agp
-- Compiling entity obuft_ctt
-- Compiling architecture obuft_ctt_v of obuft_ctt
-- Compiling entity obuft_f_12
-- Compiling architecture obuft_f_12_v of obuft_f_12
-- Compiling entity obuft_f_16
-- Compiling architecture obuft_f_16_v of obuft_f_16
-- Compiling entity obuft_f_2
-- Compiling architecture obuft_f_2_v of obuft_f_2
-- Compiling entity obuft_f_24
-- Compiling architecture obuft_f_24_v of obuft_f_24
-- Compiling entity obuft_f_4
-- Compiling architecture obuft_f_4_v of obuft_f_4
-- Compiling entity obuft_f_6
-- Compiling architecture obuft_f_6_v of obuft_f_6
-- Compiling entity obuft_f_8
-- Compiling architecture obuft_f_8_v of obuft_f_8
-- Compiling entity obuft_gtl
-- Compiling architecture obuft_gtl_v of obuft_gtl
-- Compiling entity obuft_gtl_dci
-- Compiling architecture obuft_gtl_dci_v of obuft_gtl_dci
-- Compiling entity obuft_gtlp
-- Compiling architecture obuft_gtlp_v of obuft_gtlp
-- Compiling entity obuft_gtlp_dci
-- Compiling architecture obuft_gtlp_dci_v of obuft_gtlp_dci
-- Compiling entity obuft_hstl_i
-- Compiling architecture obuft_hstl_i_v of obuft_hstl_i
-- Compiling entity obuft_hstl_i_18
-- Compiling architecture obuft_hstl_i_18_v of obuft_hstl_i_18
-- Compiling entity obuft_hstl_i_dci
-- Compiling architecture obuft_hstl_i_dci_v of obuft_hstl_i_dci
-- Compiling entity obuft_hstl_i_dci_18
-- Compiling architecture obuft_hstl_i_dci_18_v of obuft_hstl_i_dci_18
-- Compiling entity obuft_hstl_ii
-- Compiling architecture obuft_hstl_ii_v of obuft_hstl_ii
-- Compiling entity obuft_hstl_ii_18
-- Compiling architecture obuft_hstl_ii_18_v of obuft_hstl_ii_18
-- Compiling entity obuft_hstl_ii_dci
-- Compiling architecture obuft_hstl_ii_dci_v of obuft_hstl_ii_dci
-- Compiling entity obuft_hstl_ii_dci_18
-- Compiling architecture obuft_hstl_ii_dci_18_v of obuft_hstl_ii_dci_18
-- Compiling entity obuft_hstl_iii
-- Compiling architecture obuft_hstl_iii_v of obuft_hstl_iii
-- Compiling entity obuft_hstl_iii_18
-- Compiling architecture obuft_hstl_iii_18_v of obuft_hstl_iii_18
-- Compiling entity obuft_hstl_iii_dci
-- Compiling architecture obuft_hstl_iii_dci_v of obuft_hstl_iii_dci
-- Compiling entity obuft_hstl_iii_dci_18
-- Compiling architecture obuft_hstl_iii_dci_18_v of obuft_hstl_iii_dci_18
-- Compiling entity obuft_hstl_iv
-- Compiling architecture obuft_hstl_iv_v of obuft_hstl_iv
-- Compiling entity obuft_hstl_iv_18
-- Compiling architecture obuft_hstl_iv_18_v of obuft_hstl_iv_18
-- Compiling entity obuft_hstl_iv_dci
-- Compiling architecture obuft_hstl_iv_dci_v of obuft_hstl_iv_dci
-- Compiling entity obuft_hstl_iv_dci_18
-- Compiling architecture obuft_hstl_iv_dci_18_v of obuft_hstl_iv_dci_18
-- Compiling entity obuft_lvcmos12
-- Compiling architecture obuft_lvcmos12_v of obuft_lvcmos12
-- Compiling entity obuft_lvcmos12_f_2
-- Compiling architecture obuft_lvcmos12_f_2_v of obuft_lvcmos12_f_2
-- Compiling entity obuft_lvcmos12_f_4
-- Compiling architecture obuft_lvcmos12_f_4_v of obuft_lvcmos12_f_4
-- Compiling entity obuft_lvcmos12_f_6
-- Compiling architecture obuft_lvcmos12_f_6_v of obuft_lvcmos12_f_6
-- Compiling entity obuft_lvcmos12_f_8
-- Compiling architecture obuft_lvcmos12_f_8_v of obuft_lvcmos12_f_8
-- Compiling entity obuft_lvcmos12_s_2
-- Compiling architecture obuft_lvcmos12_s_2_v of obuft_lvcmos12_s_2
-- Compiling entity obuft_lvcmos12_s_4
-- Compiling architecture obuft_lvcmos12_s_4_v of obuft_lvcmos12_s_4
-- Compiling entity obuft_lvcmos12_s_6
-- Compiling architecture obuft_lvcmos12_s_6_v of obuft_lvcmos12_s_6
-- Compiling entity obuft_lvcmos12_s_8
-- Compiling architecture obuft_lvcmos12_s_8_v of obuft_lvcmos12_s_8
-- Compiling entity obuft_lvcmos15
-- Compiling architecture obuft_lvcmos15_v of obuft_lvcmos15
-- Compiling entity obuft_lvcmos15_f_12
-- Compiling architecture obuft_lvcmos15_f_12_v of obuft_lvcmos15_f_12
-- Compiling entity obuft_lvcmos15_f_16
-- Compiling architecture obuft_lvcmos15_f_16_v of obuft_lvcmos15_f_16
-- Compiling entity obuft_lvcmos15_f_2
-- Compiling architecture obuft_lvcmos15_f_2_v of obuft_lvcmos15_f_2
-- Compiling entity obuft_lvcmos15_f_4
-- Compiling architecture obuft_lvcmos15_f_4_v of obuft_lvcmos15_f_4
-- Compiling entity obuft_lvcmos15_f_6
-- Compiling architecture obuft_lvcmos15_f_6_v of obuft_lvcmos15_f_6
-- Compiling entity obuft_lvcmos15_f_8
-- Compiling architecture obuft_lvcmos15_f_8_v of obuft_lvcmos15_f_8
-- Compiling entity obuft_lvcmos15_s_12
-- Compiling architecture obuft_lvcmos15_s_12_v of obuft_lvcmos15_s_12
-- Compiling entity obuft_lvcmos15_s_16
-- Compiling architecture obuft_lvcmos15_s_16_v of obuft_lvcmos15_s_16
-- Compiling entity obuft_lvcmos15_s_2
-- Compiling architecture obuft_lvcmos15_s_2_v of obuft_lvcmos15_s_2
-- Compiling entity obuft_lvcmos15_s_4
-- Compiling architecture obuft_lvcmos15_s_4_v of obuft_lvcmos15_s_4
-- Compiling entity obuft_lvcmos15_s_6
-- Compiling architecture obuft_lvcmos15_s_6_v of obuft_lvcmos15_s_6
-- Compiling entity obuft_lvcmos15_s_8
-- Compiling architecture obuft_lvcmos15_s_8_v of obuft_lvcmos15_s_8
-- Compiling entity obuft_lvcmos18
-- Compiling architecture obuft_lvcmos18_v of obuft_lvcmos18
-- Compiling entity obuft_lvcmos18_f_12
-- Compiling architecture obuft_lvcmos18_f_12_v of obuft_lvcmos18_f_12
-- Compiling entity obuft_lvcmos18_f_16
-- Compiling architecture obuft_lvcmos18_f_16_v of obuft_lvcmos18_f_16
-- Compiling entity obuft_lvcmos18_f_2
-- Compiling architecture obuft_lvcmos18_f_2_v of obuft_lvcmos18_f_2
-- Compiling entity obuft_lvcmos18_f_4
-- Compiling architecture obuft_lvcmos18_f_4_v of obuft_lvcmos18_f_4
-- Compiling entity obuft_lvcmos18_f_6
-- Compiling architecture obuft_lvcmos18_f_6_v of obuft_lvcmos18_f_6
-- Compiling entity obuft_lvcmos18_f_8
-- Compiling architecture obuft_lvcmos18_f_8_v of obuft_lvcmos18_f_8
-- Compiling entity obuft_lvcmos18_s_12
-- Compiling architecture obuft_lvcmos18_s_12_v of obuft_lvcmos18_s_12
-- Compiling entity obuft_lvcmos18_s_16
-- Compiling architecture obuft_lvcmos18_s_16_v of obuft_lvcmos18_s_16
-- Compiling entity obuft_lvcmos18_s_2
-- Compiling architecture obuft_lvcmos18_s_2_v of obuft_lvcmos18_s_2
-- Compiling entity obuft_lvcmos18_s_4
-- Compiling architecture obuft_lvcmos18_s_4_v of obuft_lvcmos18_s_4
-- Compiling entity obuft_lvcmos18_s_6
-- Compiling architecture obuft_lvcmos18_s_6_v of obuft_lvcmos18_s_6
-- Compiling entity obuft_lvcmos18_s_8
-- Compiling architecture obuft_lvcmos18_s_8_v of obuft_lvcmos18_s_8
-- Compiling entity obuft_lvcmos2
-- Compiling architecture obuft_lvcmos2_v of obuft_lvcmos2
-- Compiling entity obuft_lvcmos25
-- Compiling architecture obuft_lvcmos25_v of obuft_lvcmos25
-- Compiling entity obuft_lvcmos25_f_12
-- Compiling architecture obuft_lvcmos25_f_12_v of obuft_lvcmos25_f_12
-- Compiling entity obuft_lvcmos25_f_16
-- Compiling architecture obuft_lvcmos25_f_16_v of obuft_lvcmos25_f_16
-- Compiling entity obuft_lvcmos25_f_2
-- Compiling architecture obuft_lvcmos25_f_2_v of obuft_lvcmos25_f_2
-- Compiling entity obuft_lvcmos25_f_24
-- Compiling architecture obuft_lvcmos25_f_24_v of obuft_lvcmos25_f_24
-- Compiling entity obuft_lvcmos25_f_4
-- Compiling architecture obuft_lvcmos25_f_4_v of obuft_lvcmos25_f_4
-- Compiling entity obuft_lvcmos25_f_6
-- Compiling architecture obuft_lvcmos25_f_6_v of obuft_lvcmos25_f_6
-- Compiling entity obuft_lvcmos25_f_8
-- Compiling architecture obuft_lvcmos25_f_8_v of obuft_lvcmos25_f_8
-- Compiling entity obuft_lvcmos25_s_12
-- Compiling architecture obuft_lvcmos25_s_12_v of obuft_lvcmos25_s_12
-- Compiling entity obuft_lvcmos25_s_16
-- Compiling architecture obuft_lvcmos25_s_16_v of obuft_lvcmos25_s_16
-- Compiling entity obuft_lvcmos25_s_2
-- Compiling architecture obuft_lvcmos25_s_2_v of obuft_lvcmos25_s_2
-- Compiling entity obuft_lvcmos25_s_24
-- Compiling architecture obuft_lvcmos25_s_24_v of obuft_lvcmos25_s_24
-- Compiling entity obuft_lvcmos25_s_4
-- Compiling architecture obuft_lvcmos25_s_4_v of obuft_lvcmos25_s_4
-- Compiling entity obuft_lvcmos25_s_6
-- Compiling architecture obuft_lvcmos25_s_6_v of obuft_lvcmos25_s_6
-- Compiling entity obuft_lvcmos25_s_8
-- Compiling architecture obuft_lvcmos25_s_8_v of obuft_lvcmos25_s_8
-- Compiling entity obuft_lvcmos33
-- Compiling architecture obuft_lvcmos33_v of obuft_lvcmos33
-- Compiling entity obuft_lvcmos33_f_12
-- Compiling architecture obuft_lvcmos33_f_12_v of obuft_lvcmos33_f_12
-- Compiling entity obuft_lvcmos33_f_16
-- Compiling architecture obuft_lvcmos33_f_16_v of obuft_lvcmos33_f_16
-- Compiling entity obuft_lvcmos33_f_2
-- Compiling architecture obuft_lvcmos33_f_2_v of obuft_lvcmos33_f_2
-- Compiling entity obuft_lvcmos33_f_24
-- Compiling architecture obuft_lvcmos33_f_24_v of obuft_lvcmos33_f_24
-- Compiling entity obuft_lvcmos33_f_4
-- Compiling architecture obuft_lvcmos33_f_4_v of obuft_lvcmos33_f_4
-- Compiling entity obuft_lvcmos33_f_6
-- Compiling architecture obuft_lvcmos33_f_6_v of obuft_lvcmos33_f_6
-- Compiling entity obuft_lvcmos33_f_8
-- Compiling architecture obuft_lvcmos33_f_8_v of obuft_lvcmos33_f_8
-- Compiling entity obuft_lvcmos33_s_12
-- Compiling architecture obuft_lvcmos33_s_12_v of obuft_lvcmos33_s_12
-- Compiling entity obuft_lvcmos33_s_16
-- Compiling architecture obuft_lvcmos33_s_16_v of obuft_lvcmos33_s_16
-- Compiling entity obuft_lvcmos33_s_2
-- Compiling architecture obuft_lvcmos33_s_2_v of obuft_lvcmos33_s_2
-- Compiling entity obuft_lvcmos33_s_24
-- Compiling architecture obuft_lvcmos33_s_24_v of obuft_lvcmos33_s_24
-- Compiling entity obuft_lvcmos33_s_4
-- Compiling architecture obuft_lvcmos33_s_4_v of obuft_lvcmos33_s_4
-- Compiling entity obuft_lvcmos33_s_6
-- Compiling architecture obuft_lvcmos33_s_6_v of obuft_lvcmos33_s_6
-- Compiling entity obuft_lvcmos33_s_8
-- Compiling architecture obuft_lvcmos33_s_8_v of obuft_lvcmos33_s_8
-- Compiling entity obuft_lvdci_15
-- Compiling architecture obuft_lvdci_15_v of obuft_lvdci_15
-- Compiling entity obuft_lvdci_18
-- Compiling architecture obuft_lvdci_18_v of obuft_lvdci_18
-- Compiling entity obuft_lvdci_25
-- Compiling architecture obuft_lvdci_25_v of obuft_lvdci_25
-- Compiling entity obuft_lvdci_33
-- Compiling architecture obuft_lvdci_33_v of obuft_lvdci_33
-- Compiling entity obuft_lvdci_dv2_15
-- Compiling architecture obuft_lvdci_dv2_15_v of obuft_lvdci_dv2_15
-- Compiling entity obuft_lvdci_dv2_18
-- Compiling architecture obuft_lvdci_dv2_18_v of obuft_lvdci_dv2_18
-- Compiling entity obuft_lvdci_dv2_25
-- Compiling architecture obuft_lvdci_dv2_25_v of obuft_lvdci_dv2_25
-- Compiling entity obuft_lvdci_dv2_33
-- Compiling architecture obuft_lvdci_dv2_33_v of obuft_lvdci_dv2_33
-- Compiling entity obuft_lvds
-- Compiling architecture obuft_lvds_v of obuft_lvds
-- Compiling entity obuft_lvpecl
-- Compiling architecture obuft_lvpecl_v of obuft_lvpecl
-- Compiling entity obuft_lvttl
-- Compiling architecture obuft_lvttl_v of obuft_lvttl
-- Compiling entity obuft_lvttl_f_12
-- Compiling architecture obuft_lvttl_f_12_v of obuft_lvttl_f_12
-- Compiling entity obuft_lvttl_f_16
-- Compiling architecture obuft_lvttl_f_16_v of obuft_lvttl_f_16
-- Compiling entity obuft_lvttl_f_2
-- Compiling architecture obuft_lvttl_f_2_v of obuft_lvttl_f_2
-- Compiling entity obuft_lvttl_f_24
-- Compiling architecture obuft_lvttl_f_24_v of obuft_lvttl_f_24
-- Compiling entity obuft_lvttl_f_4
-- Compiling architecture obuft_lvttl_f_4_v of obuft_lvttl_f_4
-- Compiling entity obuft_lvttl_f_6
-- Compiling architecture obuft_lvttl_f_6_v of obuft_lvttl_f_6
-- Compiling entity obuft_lvttl_f_8
-- Compiling architecture obuft_lvttl_f_8_v of obuft_lvttl_f_8
-- Compiling entity obuft_lvttl_s_12
-- Compiling architecture obuft_lvttl_s_12_v of obuft_lvttl_s_12
-- Compiling entity obuft_lvttl_s_16
-- Compiling architecture obuft_lvttl_s_16_v of obuft_lvttl_s_16
-- Compiling entity obuft_lvttl_s_2
-- Compiling architecture obuft_lvttl_s_2_v of obuft_lvttl_s_2
-- Compiling entity obuft_lvttl_s_24
-- Compiling architecture obuft_lvttl_s_24_v of obuft_lvttl_s_24
-- Compiling entity obuft_lvttl_s_4
-- Compiling architecture obuft_lvttl_s_4_v of obuft_lvttl_s_4
-- Compiling entity obuft_lvttl_s_6
-- Compiling architecture obuft_lvttl_s_6_v of obuft_lvttl_s_6
-- Compiling entity obuft_lvttl_s_8
-- Compiling architecture obuft_lvttl_s_8_v of obuft_lvttl_s_8
-- Compiling entity obuft_pci33_3
-- Compiling architecture obuft_pci33_3_v of obuft_pci33_3
-- Compiling entity obuft_pci33_5
-- Compiling architecture obuft_pci33_5_v of obuft_pci33_5
-- Compiling entity obuft_pci66_3
-- Compiling architecture obuft_pci66_3_v of obuft_pci66_3
-- Compiling entity obuft_pcix
-- Compiling architecture obuft_pcix_v of obuft_pcix
-- Compiling entity obuft_pcix66_3
-- Compiling architecture obuft_pcix66_3_v of obuft_pcix66_3
-- Compiling entity obuft_s_12
-- Compiling architecture obuft_s_12_v of obuft_s_12
-- Compiling entity obuft_s_16
-- Compiling architecture obuft_s_16_v of obuft_s_16
-- Compiling entity obuft_s_2
-- Compiling architecture obuft_s_2_v of obuft_s_2
-- Compiling entity obuft_s_24
-- Compiling architecture obuft_s_24_v of obuft_s_24
-- Compiling entity obuft_s_4
-- Compiling architecture obuft_s_4_v of obuft_s_4
-- Compiling entity obuft_s_6
-- Compiling architecture obuft_s_6_v of obuft_s_6
-- Compiling entity obuft_s_8
-- Compiling architecture obuft_s_8_v of obuft_s_8
-- Compiling entity obuft_sstl18_i
-- Compiling architecture obuft_sstl18_i_v of obuft_sstl18_i
-- Compiling entity obuft_sstl18_i_dci
-- Compiling architecture obuft_sstl18_i_dci_v of obuft_sstl18_i_dci
-- Compiling entity obuft_sstl18_ii
-- Compiling architecture obuft_sstl18_ii_v of obuft_sstl18_ii
-- Compiling entity obuft_sstl18_ii_dci
-- Compiling architecture obuft_sstl18_ii_dci_v of obuft_sstl18_ii_dci
-- Compiling entity obuft_sstl2_i
-- Compiling architecture obuft_sstl2_i_v of obuft_sstl2_i
-- Compiling entity obuft_sstl2_i_dci
-- Compiling architecture obuft_sstl2_i_dci_v of obuft_sstl2_i_dci
-- Compiling entity obuft_sstl2_ii
-- Compiling architecture obuft_sstl2_ii_v of obuft_sstl2_ii
-- Compiling entity obuft_sstl2_ii_dci
-- Compiling architecture obuft_sstl2_ii_dci_v of obuft_sstl2_ii_dci
-- Compiling entity obuft_sstl3_i
-- Compiling architecture obuft_sstl3_i_v of obuft_sstl3_i
-- Compiling entity obuft_sstl3_i_dci
-- Compiling architecture obuft_sstl3_i_dci_v of obuft_sstl3_i_dci
-- Compiling entity obuft_sstl3_ii
-- Compiling architecture obuft_sstl3_ii_v of obuft_sstl3_ii
-- Compiling entity obuft_sstl3_ii_dci
-- Compiling architecture obuft_sstl3_ii_dci_v of obuft_sstl3_ii_dci
-- Compiling entity obuftds
-- Compiling architecture obuftds_v of obuftds
-- Compiling entity obuftds_blvds_25
-- Compiling architecture obuftds_blvds_25_v of obuftds_blvds_25
-- Compiling entity obuftds_ldt_25
-- Compiling architecture obuftds_ldt_25_v of obuftds_ldt_25
-- Compiling entity obuftds_lvds_25
-- Compiling architecture obuftds_lvds_25_v of obuftds_lvds_25
-- Compiling entity obuftds_lvds_33
-- Compiling architecture obuftds_lvds_33_v of obuftds_lvds_33
-- Compiling entity obuftds_lvdsext_25
-- Compiling architecture obuftds_lvdsext_25_v of obuftds_lvdsext_25
-- Compiling entity obuftds_lvdsext_33
-- Compiling architecture obuftds_lvdsext_33_v of obuftds_lvdsext_33
-- Compiling entity obuftds_lvpecl_25
-- Compiling architecture obuftds_lvpecl_25_v of obuftds_lvpecl_25
-- Compiling entity obuftds_lvpecl_33
-- Compiling architecture obuftds_lvpecl_33_v of obuftds_lvpecl_33
-- Compiling entity obuftds_ulvds_25
-- Compiling architecture obuftds_ulvds_25_v of obuftds_ulvds_25
-- Compiling entity ofddrcpe
-- Compiling architecture ofddrcpe_v of ofddrcpe
-- Compiling entity ofddrrse
-- Compiling architecture ofddrrse_v of ofddrrse
-- Compiling entity ofddrtcpe
-- Compiling architecture ofddrtcpe_v of ofddrtcpe
-- Compiling entity ofddrtrse
-- Compiling architecture ofddrtrse_v of ofddrtrse
-- Compiling entity or2
-- Compiling architecture or2_v of or2
-- Compiling entity or2b1
-- Compiling architecture or2b1_v of or2b1
-- Compiling entity or2b2
-- Compiling architecture or2b2_v of or2b2
-- Compiling entity or3
-- Compiling architecture or3_v of or3
-- Compiling entity or3b1
-- Compiling architecture or3b1_v of or3b1
-- Compiling entity or3b2
-- Compiling architecture or3b2_v of or3b2
-- Compiling entity or3b3
-- Compiling architecture or3b3_v of or3b3
-- Compiling entity or4
-- Compiling architecture or4_v of or4
-- Compiling entity or4b1
-- Compiling architecture or4b1_v of or4b1
-- Compiling entity or4b2
-- Compiling architecture or4b2_v of or4b2
-- Compiling entity or4b3
-- Compiling architecture or4b3_v of or4b3
-- Compiling entity or4b4
-- Compiling architecture or4b4_v of or4b4
-- Compiling entity or5
-- Compiling architecture or5_v of or5
-- Compiling entity or5b1
-- Compiling architecture or5b1_v of or5b1
-- Compiling entity or5b2
-- Compiling architecture or5b2_v of or5b2
-- Compiling entity or5b3
-- Compiling architecture or5b3_v of or5b3
-- Compiling entity or5b4
-- Compiling architecture or5b4_v of or5b4
-- Compiling entity or5b5
-- Compiling architecture or5b5_v of or5b5
-- Compiling entity orcy
-- Compiling architecture orcy_v of orcy
-- Compiling entity pulldown
-- Compiling architecture pulldown_v of pulldown
-- Compiling entity pullup
-- Compiling architecture pullup_v of pullup
-- Compiling entity ram128x1s
-- Compiling architecture ram128x1s_v of ram128x1s
-- Compiling entity ram128x1s_1
-- Compiling architecture ram128x1s_1_v of ram128x1s_1
-- Compiling entity ram16x1d
-- Compiling architecture ram16x1d_v of ram16x1d
-- Compiling entity ram16x1d_1
-- Compiling architecture ram16x1d_1_v of ram16x1d_1
-- Compiling entity ram16x1s
-- Compiling architecture ram16x1s_v of ram16x1s
-- Compiling entity ram16x1s_1
-- Compiling architecture ram16x1s_1_v of ram16x1s_1
-- Compiling entity ram16x2s
-- Compiling architecture ram16x2s_v of ram16x2s
-- Compiling entity ram16x4s
-- Compiling architecture ram16x4s_v of ram16x4s
-- Compiling entity ram16x8s
-- Compiling architecture ram16x8s_v of ram16x8s
-- Compiling entity ram32x1d
-- Compiling architecture ram32x1d_v of ram32x1d
-- Compiling entity ram32x1d_1
-- Compiling architecture ram32x1d_1_v of ram32x1d_1
-- Compiling entity ram32x1s
-- Compiling architecture ram32x1s_v of ram32x1s
-- Compiling entity ram32x1s_1
-- Compiling architecture ram32x1s_1_v of ram32x1s_1
-- Compiling entity ram32x2s
-- Compiling architecture ram32x2s_v of ram32x2s
-- Compiling entity ram32x4s
-- Compiling architecture ram32x4s_v of ram32x4s
-- Compiling entity ram32x8s
-- Compiling architecture ram32x8s_v of ram32x8s
-- Compiling entity ram64x1d
-- Compiling architecture ram64x1d_v of ram64x1d
-- Compiling entity ram64x1d_1
-- Compiling architecture ram64x1d_1_v of ram64x1d_1
-- Compiling entity ram64x1s
-- Compiling architecture ram64x1s_v of ram64x1s
-- Compiling entity ram64x1s_1
-- Compiling architecture ram64x1s_1_v of ram64x1s_1
-- Compiling entity ram64x2s
-- Compiling architecture ram64x2s_v of ram64x2s
-- Compiling entity ramb16_s1
-- Compiling architecture ramb16_s1_v of ramb16_s1
-- Compiling entity ramb16_s18
-- Compiling architecture ramb16_s18_v of ramb16_s18
-- Compiling entity ramb16_s18_s18
-- Compiling architecture ramb16_s18_s18_v of ramb16_s18_s18
-- Compiling entity ramb16_s18_s36
-- Compiling architecture ramb16_s18_s36_v of ramb16_s18_s36
-- Compiling entity ramb16_s1_s1
-- Compiling architecture ramb16_s1_s1_v of ramb16_s1_s1
-- Compiling entity ramb16_s1_s18
-- Compiling architecture ramb16_s1_s18_v of ramb16_s1_s18
-- Compiling entity ramb16_s1_s2
-- Compiling architecture ramb16_s1_s2_v of ramb16_s1_s2
-- Compiling entity ramb16_s1_s36
-- Compiling architecture ramb16_s1_s36_v of ramb16_s1_s36
-- Compiling entity ramb16_s1_s4
-- Compiling architecture ramb16_s1_s4_v of ramb16_s1_s4
-- Compiling entity ramb16_s1_s9
-- Compiling architecture ramb16_s1_s9_v of ramb16_s1_s9
-- Compiling entity ramb16_s2
-- Compiling architecture ramb16_s2_v of ramb16_s2
-- Compiling entity ramb16_s2_s18
-- Compiling architecture ramb16_s2_s18_v of ramb16_s2_s18
-- Compiling entity ramb16_s2_s2
-- Compiling architecture ramb16_s2_s2_v of ramb16_s2_s2
-- Compiling entity ramb16_s2_s36
-- Compiling architecture ramb16_s2_s36_v of ramb16_s2_s36
-- Compiling entity ramb16_s2_s4
-- Compiling architecture ramb16_s2_s4_v of ramb16_s2_s4
-- Compiling entity ramb16_s2_s9
-- Compiling architecture ramb16_s2_s9_v of ramb16_s2_s9
-- Compiling entity ramb16_s36
-- Compiling architecture ramb16_s36_v of ramb16_s36
-- Compiling entity ramb16_s36_s36
-- Compiling architecture ramb16_s36_s36_v of ramb16_s36_s36
-- Compiling entity ramb16_s4
-- Compiling architecture ramb16_s4_v of ramb16_s4
-- Compiling entity ramb16_s4_s18
-- Compiling architecture ramb16_s4_s18_v of ramb16_s4_s18
-- Compiling entity ramb16_s4_s36
-- Compiling architecture ramb16_s4_s36_v of ramb16_s4_s36
-- Compiling entity ramb16_s4_s4
-- Compiling architecture ramb16_s4_s4_v of ramb16_s4_s4
-- Compiling entity ramb16_s4_s9
-- Compiling architecture ramb16_s4_s9_v of ramb16_s4_s9
-- Compiling entity ramb16_s9
-- Compiling architecture ramb16_s9_v of ramb16_s9
-- Compiling entity ramb16_s9_s18
-- Compiling architecture ramb16_s9_s18_v of ramb16_s9_s18
-- Compiling entity ramb16_s9_s36
-- Compiling architecture ramb16_s9_s36_v of ramb16_s9_s36
-- Compiling entity ramb16_s9_s9
-- Compiling architecture ramb16_s9_s9_v of ramb16_s9_s9
-- Compiling entity ramb4_s1
-- Compiling architecture ramb4_s1_v of ramb4_s1
-- Compiling entity ramb4_s16
-- Compiling architecture ramb4_s16_v of ramb4_s16
-- Compiling entity ramb4_s16_s16
-- Compiling architecture ramb4_s16_s16_v of ramb4_s16_s16
-- Compiling entity ramb4_s1_s1
-- Compiling architecture ramb4_s1_s1_v of ramb4_s1_s1
-- Compiling entity ramb4_s1_s16
-- Compiling architecture ramb4_s1_s16_v of ramb4_s1_s16
-- Compiling entity ramb4_s1_s2
-- Compiling architecture ramb4_s1_s2_v of ramb4_s1_s2
-- Compiling entity ramb4_s1_s4
-- Compiling architecture ramb4_s1_s4_v of ramb4_s1_s4
-- Compiling entity ramb4_s1_s8
-- Compiling architecture ramb4_s1_s8_v of ramb4_s1_s8
-- Compiling entity ramb4_s2
-- Compiling architecture ramb4_s2_v of ramb4_s2
-- Compiling entity ramb4_s2_s16
-- Compiling architecture ramb4_s2_s16_v of ramb4_s2_s16
-- Compiling entity ramb4_s2_s2
-- Compiling architecture ramb4_s2_s2_v of ramb4_s2_s2
-- Compiling entity ramb4_s2_s4
-- Compiling architecture ramb4_s2_s4_v of ramb4_s2_s4
-- Compiling entity ramb4_s2_s8
-- Compiling architecture ramb4_s2_s8_v of ramb4_s2_s8
-- Compiling entity ramb4_s4
-- Compiling architecture ramb4_s4_v of ramb4_s4
-- Compiling entity ramb4_s4_s16
-- Compiling architecture ramb4_s4_s16_v of ramb4_s4_s16
-- Compiling entity ramb4_s4_s4
-- Compiling architecture ramb4_s4_s4_v of ramb4_s4_s4
-- Compiling entity ramb4_s4_s8
-- Compiling architecture ramb4_s4_s8_v of ramb4_s4_s8
-- Compiling entity ramb4_s8
-- Compiling architecture ramb4_s8_v of ramb4_s8
-- Compiling entity ramb4_s8_s16
-- Compiling architecture ramb4_s8_s16_v of ramb4_s8_s16
-- Compiling entity ramb4_s8_s8
-- Compiling architecture ramb4_s8_s8_v of ramb4_s8_s8
-- Compiling entity roc
-- Compiling architecture roc_v of roc
-- Compiling entity rocbuf
-- Compiling architecture rocbuf_v of rocbuf
-- Compiling entity rom128x1
-- Compiling architecture rom128x1_v of rom128x1
-- Compiling entity rom16x1
-- Compiling architecture rom16x1_v of rom16x1
-- Compiling entity rom256x1
-- Compiling architecture rom256x1_v of rom256x1
-- Compiling entity rom32x1
-- Compiling architecture rom32x1_v of rom32x1
-- Compiling entity rom64x1
-- Compiling architecture rom64x1_v of rom64x1
-- Compiling entity srl16
-- Compiling architecture srl16_v of srl16
-- Compiling entity srl16_1
-- Compiling architecture srl16_1_v of srl16_1
-- Compiling entity srl16e
-- Compiling architecture srl16e_v of srl16e
-- Compiling entity srl16e_1
-- Compiling architecture srl16e_1_v of srl16e_1
-- Compiling entity srlc16
-- Compiling architecture srlc16_v of srlc16
-- Compiling entity srlc16_1
-- Compiling architecture srlc16_1_v of srlc16_1
-- Compiling entity srlc16e
-- Compiling architecture srlc16e_v of srlc16e
-- Compiling entity srlc16e_1
-- Compiling architecture srlc16e_1_v of srlc16e_1
-- Compiling entity startbuf_fpgacore
-- Compiling architecture startbuf_fpgacore_v of startbuf_fpgacore
-- Compiling entity startbuf_spartan2
-- Compiling architecture startbuf_spartan2_v of startbuf_spartan2
-- Compiling entity startbuf_spartan3
-- Compiling architecture startbuf_spartan3_v of startbuf_spartan3
-- Compiling entity startbuf_virtex
-- Compiling architecture startbuf_virtex_v of startbuf_virtex
-- Compiling entity startbuf_virtex2
-- Compiling architecture startbuf_virtex2_v of startbuf_virtex2
-- Compiling entity startup_fpgacore
-- Compiling architecture startup_fpgacore_v of startup_fpgacore
-- Compiling entity startup_spartan2
-- Compiling architecture startup_spartan2_v of startup_spartan2
-- Compiling entity startup_spartan3
-- Compiling architecture startup_spartan3_v of startup_spartan3
-- Compiling entity startup_virtex
-- Compiling architecture startup_virtex_v of startup_virtex
-- Compiling entity startup_virtex2
-- Compiling architecture startup_virtex2_v of startup_virtex2
-- Compiling entity tblock
-- Compiling architecture tblock_v of tblock
-- Compiling entity timegrp
-- Compiling architecture timegrp_v of timegrp
-- Compiling entity timespec
-- Compiling architecture timespec_v of timespec
-- Compiling entity toc
-- Compiling architecture toc_v of toc
-- Compiling entity tocbuf
-- Compiling architecture tocbuf_v of tocbuf
-- Compiling entity vcc
-- Compiling architecture vcc_v of vcc
-- Compiling entity xnor2
-- Compiling architecture xnor2_v of xnor2
-- Compiling entity xnor3
-- Compiling architecture xnor3_v of xnor3
-- Compiling entity xnor4
-- Compiling architecture xnor4_v of xnor4
-- Compiling entity xnor5
-- Compiling architecture xnor5_v of xnor5
-- Compiling entity xor2
-- Compiling architecture xor2_v of xor2
-- Compiling entity xor3
-- Compiling architecture xor3_v of xor3
-- Compiling entity xor4
-- Compiling architecture xor4_v of xor4
-- Compiling entity xor5
-- Compiling architecture xor5_v of xor5
-- Compiling entity xorcy
-- Compiling architecture xorcy_v of xorcy
-- Compiling entity xorcy_d
-- Compiling architecture xorcy_d_v of xorcy_d
-- Compiling entity xorcy_l
-- Compiling architecture xorcy_l_v of xorcy_l
-- Compiling entity and6
-- Compiling architecture and6_v of and6
-- Compiling entity and7
-- Compiling architecture and7_v of and7
-- Compiling entity and8
-- Compiling architecture and8_v of and8
-- Compiling entity buffoe
-- Compiling architecture buffoe_v of buffoe
-- Compiling entity bufgsr
-- Compiling architecture bufgsr_v of bufgsr
-- Compiling entity bufgts
-- Compiling architecture bufgts_v of bufgts
-- Compiling entity clk_div10
-- Compiling architecture clk_div10_v of clk_div10
-- Compiling entity clk_div10r
-- Compiling architecture clk_div10r_v of clk_div10r
-- Compiling entity clk_div10rsd
-- Compiling architecture clk_div10rsd_v of clk_div10rsd
-- Compiling entity clk_div10sd
-- Compiling architecture clk_div10sd_v of clk_div10sd
-- Compiling entity clk_div12
-- Compiling architecture clk_div12_v of clk_div12
-- Compiling entity clk_div12r
-- Compiling architecture clk_div12r_v of clk_div12r
-- Compiling entity clk_div12rsd
-- Compiling architecture clk_div12rsd_v of clk_div12rsd
-- Compiling entity clk_div12sd
-- Compiling architecture clk_div12sd_v of clk_div12sd
-- Compiling entity clk_div14
-- Compiling architecture clk_div14_v of clk_div14
-- Compiling entity clk_div14r
-- Compiling architecture clk_div14r_v of clk_div14r
-- Compiling entity clk_div14rsd
-- Compiling architecture clk_div14rsd_v of clk_div14rsd
-- Compiling entity clk_div14sd
-- Compiling architecture clk_div14sd_v of clk_div14sd
-- Compiling entity clk_div16
-- Compiling architecture clk_div16_v of clk_div16
-- Compiling entity clk_div16r
-- Compiling architecture clk_div16r_v of clk_div16r
-- Compiling entity clk_div16rsd
-- Compiling architecture clk_div16rsd_v of clk_div16rsd
-- Compiling entity clk_div16sd
-- Compiling architecture clk_div16sd_v of clk_div16sd
-- Compiling entity clk_div2
-- Compiling architecture clk_div2_v of clk_div2
-- Compiling entity clk_div2r
-- Compiling architecture clk_div2r_v of clk_div2r
-- Compiling entity clk_div2rsd
-- Compiling architecture clk_div2rsd_v of clk_div2rsd
-- Compiling entity clk_div2sd
-- Compiling architecture clk_div2sd_v of clk_div2sd
-- Compiling entity clk_div4
-- Compiling architecture clk_div4_v of clk_div4
-- Compiling entity clk_div4r
-- Compiling architecture clk_div4r_v of clk_div4r
-- Compiling entity clk_div4rsd
-- Compiling architecture clk_div4rsd_v of clk_div4rsd
-- Compiling entity clk_div4sd
-- Compiling architecture clk_div4sd_v of clk_div4sd
-- Compiling entity clk_div6
-- Compiling architecture clk_div6_v of clk_div6
-- Compiling entity clk_div6r
-- Compiling architecture clk_div6r_v of clk_div6r
-- Compiling entity clk_div6rsd
-- Compiling architecture clk_div6rsd_v of clk_div6rsd
-- Compiling entity clk_div6sd
-- Compiling architecture clk_div6sd_v of clk_div6sd
-- Compiling entity clk_div8
-- Compiling architecture clk_div8_v of clk_div8
-- Compiling entity clk_div8r
-- Compiling architecture clk_div8r_v of clk_div8r
-- Compiling entity clk_div8rsd
-- Compiling architecture clk_div8rsd_v of clk_div8rsd
-- Compiling entity clk_div8sd
-- Compiling architecture clk_div8sd_v of clk_div8sd
-- Compiling entity fdcpx1
-- Compiling architecture fdcpx1_v of fdcpx1
-- Compiling entity fdd
-- Compiling architecture fdd_v of fdd
-- Compiling entity fddc
-- Compiling architecture fddc_v of fddc
-- Compiling entity fddce
-- Compiling architecture fddce_v of fddce
-- Compiling entity fddcp
-- Compiling architecture fddcp_v of fddcp
-- Compiling entity fddcpe
-- Compiling architecture fddcpe_v of fddcpe
-- Compiling entity fddp
-- Compiling architecture fddp_v of fddp
-- Compiling entity fddpe
-- Compiling architecture fddpe_v of fddpe
-- Compiling entity ftc
-- Compiling architecture ftc_v of ftc
-- Compiling entity ftcp
-- Compiling architecture ftcp_v of ftcp
-- Compiling entity ftp
-- Compiling architecture ftp_v of ftp
-- Compiling entity ild
-- Compiling architecture ild_v of ild
-- Compiling entity iobufe
-- Compiling architecture iobufe_v of iobufe
-- Compiling entity iobufe_f
-- Compiling architecture iobufe_f_v of iobufe_f
-- Compiling entity iobufe_s
-- Compiling architecture iobufe_s_v of iobufe_s
-- Compiling entity keep
-- Compiling architecture keep_v of keep
-- Compiling entity ldg
-- Compiling architecture ldg_v of ldg
-- Compiling entity merge
-- Compiling architecture merge_v of merge
-- Compiling entity min_off
-- Compiling architecture min_off_v of min_off
-- Compiling entity obufe
-- Compiling architecture obufe_v of obufe
-- Compiling entity opt_off
-- Compiling architecture opt_off_v of opt_off
-- Compiling entity opt_uim
-- Compiling architecture opt_uim_v of opt_uim
-- Compiling entity or6
-- Compiling architecture or6_v of or6
-- Compiling entity or7
-- Compiling architecture or7_v of or7
-- Compiling entity or8
-- Compiling architecture or8_v of or8
-- Compiling entity wireand
-- Compiling architecture wireand_v of wireand
-- Compiling entity bscan_virtex4
-- Compiling architecture bscan_virtex4_v of bscan_virtex4
-- Compiling entity bufgctrl
-- Compiling architecture bufgctrl_v of bufgctrl
-- Loading package std_logic_arith
-- Compiling entity bufgmux_virtex4
-- Compiling architecture bufgmux_virtex4_v of bufgmux_virtex4
-- Compiling entity bufio
-- Compiling architecture bufio_v of bufio
-- Compiling entity bufr
-- Compiling architecture bufr_v of bufr
-- Compiling entity capture_virtex4
-- Compiling architecture capture_virtex4_v of capture_virtex4
-- Compiling entity dcireset
-- Compiling architecture dcireset_v of dcireset
-- Compiling entity dcm_adv_clock_divide_by_2
-- Compiling architecture dcm_adv_clock_divide_by_2_v of dcm_adv_clock_divide_by_2
-- Compiling entity dcm_adv_maximum_period_check
-- Compiling architecture dcm_adv_maximum_period_check_v of dcm_adv_maximum_period_check
-- Compiling entity dcm_adv_clock_lost
-- Compiling architecture dcm_adv_clock_lost_v of dcm_adv_clock_lost
-- Compiling entity dcm_adv
-- Compiling architecture dcm_adv_v of dcm_adv
-- Loading package numeric_std
-- Compiling entity dcm_base
-- Compiling architecture dcm_base_v of dcm_base
-- Compiling entity dcm_ps
-- Compiling architecture dcm_ps_v of dcm_ps
-- Loading package std_logic_signed
-- Compiling entity dsp48
-- Compiling architecture dsp48_v of dsp48
-- Compiling entity fifo16
-- Compiling architecture fifo16_v of fifo16
-- Compiling entity frame_ecc_virtex4
-- Compiling architecture frame_ecc_virtex4_v of frame_ecc_virtex4
-- Compiling entity gt11clk
-- Compiling architecture gt11clk_v of gt11clk
-- Compiling entity gt11clk_mgt
-- Compiling architecture gt11clk_mgt_v of gt11clk_mgt
-- Compiling entity icap_virtex4
-- Compiling architecture icap_virtex4_v of icap_virtex4
-- Compiling entity iddr
-- Compiling architecture iddr_v of iddr
-- Compiling entity idelay
-- Compiling architecture idelay_v of idelay
-- Compiling entity idelayctrl
-- Compiling architecture idelayctrl_v of idelayctrl
-- Compiling entity bscntrl
-- Compiling architecture bscntrl_v of bscntrl
-- Compiling entity ice_module
-- Compiling architecture ice_v of ice_module
-- Compiling entity iserdes
-- Compiling architecture iserdes_v of iserdes
-- Compiling entity jtag_sim_virtex4_submod
-- Compiling architecture jtag_sim_virtex4_submod_v of jtag_sim_virtex4_submod
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package textio
-- Loading package vital_timing
-- Loading package vital_primitives
-- Loading package vpkg
-- Loading package vcomponents
-- Compiling entity jtag_sim_virtex4
-- Compiling architecture jtag_sim_virtex4_v of jtag_sim_virtex4
-- Compiling entity oddr
-- Compiling architecture oddr_v of oddr
-- Loading package std_logic_arith
-- Compiling entity plg
-- Compiling architecture plg_v of plg
-- Compiling entity ioout
-- Compiling architecture ioout_v of ioout
-- Compiling entity iot
-- Compiling architecture iot_v of iot
-- Compiling entity oserdes
-- Compiling architecture oserdes_v of oserdes
-- Compiling entity pmcd
-- Compiling architecture pmcd_v of pmcd
-- Compiling entity ramb16
-- Compiling architecture ramb16_v of ramb16
-- Compiling entity ramb32_s64_ecc
-- Compiling architecture ramb32_s64_ecc_v of ramb32_s64_ecc
-- Compiling entity startbuf_virtex4
-- Compiling architecture startbuf_virtex4_v of startbuf_virtex4
-- Compiling entity startup_virtex4
-- Compiling architecture startup_virtex4_v of startup_virtex4
-- Compiling entity usr_access_virtex4
-- Compiling architecture usr_access_virtex4_v of usr_access_virtex4
-- Compiling entity iddr2
-- Compiling architecture iddr2_v of iddr2
-- Loading package std_logic_signed
-- Compiling entity mult18x18sio
-- Compiling architecture mult18x18sio_v of mult18x18sio
-- Compiling entity oddr2
-- Compiling architecture oddr2_v of oddr2
-- Compiling entity startup_spartan3e
-- Compiling architecture startup_spartan3e_v of startup_spartan3e
-- Compiling entity afifo36_internal
-- Compiling architecture afifo36_internal_v of afifo36_internal
-- Compiling entity aramb36_internal
-- Compiling architecture aramb36_internal_v of aramb36_internal
-- Compiling entity bscan_virtex5
-- Compiling architecture bscan_virtex5_v of bscan_virtex5
-- Compiling entity bufgmux_ctrl
-- Compiling architecture bufgmux_ctrl_v of bufgmux_ctrl
-- Compiling entity capture_virtex5
-- Compiling architecture capture_virtex5_v of capture_virtex5
-- Compiling entity carry4
-- Compiling architecture carry4_v of carry4
-- Compiling entity cfglut5
-- Compiling architecture cfglut5_v of cfglut5
-- Compiling entity crc32
-- Compiling architecture crc32_v of crc32
-- Compiling entity crc64
-- Compiling architecture crc64_v of crc64
-- Compiling entity dsp48e
-- Compiling architecture dsp48e_v of dsp48e
-- Compiling entity fifo18
-- Compiling architecture fifo18_v of fifo18
-- Compiling entity fifo18_36
-- Compiling architecture fifo18_36_v of fifo18_36
-- Compiling entity fifo36
-- Compiling architecture fifo36_v of fifo36
-- Compiling entity fifo36_72
-- Compiling architecture fifo36_72_v of fifo36_72
-- Compiling entity fifo36_72_exp
-- Compiling architecture fifo36_72_exp_v of fifo36_72_exp
-- Compiling entity fifo36_exp
-- Compiling architecture fifo36_exp_v of fifo36_exp
-- Compiling entity frame_ecc_virtex5
-- Compiling architecture frame_ecc_virtex5_v of frame_ecc_virtex5
-- Compiling entity icap_virtex5
-- Compiling architecture icap_virtex5_v of icap_virtex5
-- Compiling entity iddr_2clk
-- Compiling architecture iddr_2clk_v of iddr_2clk
-- Compiling entity iodelay
-- Compiling architecture iodelay_v of iodelay
-- Compiling entity bscntrl
-- Compiling architecture bscntrl_v of bscntrl
-- Compiling entity ice_module
-- Compiling architecture ice_v of ice_module
-- Compiling entity iserdes_nodelay
-- Compiling architecture iserdes_nodelay_v of iserdes_nodelay
-- Compiling entity jtag_sim_virtex5_submod
-- Compiling architecture jtag_sim_virtex5_submod_v of jtag_sim_virtex5_submod
-- Compiling entity jtag_sim_virtex5
-- Compiling architecture jtag_sim_virtex5_v of jtag_sim_virtex5
-- Compiling entity key_clear
-- Compiling architecture key_clear_v of key_clear
-- Compiling entity lut5
-- Compiling architecture lut5_v of lut5
-- Compiling entity lut5_d
-- Compiling architecture lut5_d_v of lut5_d
-- Compiling entity lut5_l
-- Compiling architecture lut5_l_v of lut5_l
-- Compiling entity lut6
-- Compiling architecture lut6_v of lut6
-- Compiling entity lut6_2
-- Compiling architecture lut6_2_v of lut6_2
-- Compiling entity lut6_d
-- Compiling architecture lut6_d_v of lut6_d
-- Compiling entity lut6_l
-- Compiling architecture lut6_l_v of lut6_l
-- Loading package numeric_std
-- Compiling entity pll_adv
-- Compiling architecture pll_adv_v of pll_adv
-- Compiling entity pll_base
-- Compiling architecture pll_base_v of pll_base
-- Compiling entity ram128x1d
-- Compiling architecture ram128x1d_v of ram128x1d
-- Compiling entity ram256x1s
-- Compiling architecture ram256x1s_v of ram256x1s
-- Compiling entity ram32m
-- Compiling architecture ram32m_v of ram32m
-- Compiling entity ram64m
-- Compiling architecture ram64m_v of ram64m
-- Compiling entity ramb18
-- Compiling architecture ramb18_v of ramb18
-- Compiling entity ramb18sdp
-- Compiling architecture ramb18sdp_v of ramb18sdp
-- Compiling entity ramb36
-- Compiling architecture ramb36_v of ramb36
-- Compiling entity ramb36_exp
-- Compiling architecture ramb36_exp_v of ramb36_exp
-- Compiling entity ramb36sdp
-- Compiling architecture ramb36sdp_v of ramb36sdp
-- Compiling entity ramb36sdp_exp
-- Compiling architecture ramb36sdp_exp_v of ramb36sdp_exp
-- Compiling entity srlc32e
-- Compiling architecture srlc32e_v of srlc32e
-- Compiling entity startup_virtex5
-- Compiling architecture startup_virtex5_v of startup_virtex5
-- Compiling entity sysmon
-- Compiling architecture sysmon_v of sysmon
-- Compiling entity usr_access_virtex5
-- Compiling architecture usr_access_virtex5_v of usr_access_virtex5
-- Compiling entity bscan_spartan3a
-- Compiling architecture bscan_spartan3a_v of bscan_spartan3a
-- Compiling entity capture_spartan3a
-- Compiling architecture capture_spartan3a_v of capture_spartan3a
-- Compiling entity dna_port
-- Compiling architecture dna_port_v of dna_port
-- Compiling entity ibuf_dly_adj
-- Compiling architecture ibuf_dly_adj_v of ibuf_dly_adj
-- Compiling entity ibufds_dly_adj
-- Compiling architecture ibufds_dly_adj_v of ibufds_dly_adj
-- Compiling entity icap_spartan3a
-- Compiling architecture icap_spartan3a_v of icap_spartan3a
-- Compiling entity jtag_sim_spartan3a
-- Compiling architecture jtag_sim_spartan3a_v of jtag_sim_spartan3a
-- Compiling entity ramb16bwe
-- Compiling architecture ramb16bwe_v of ramb16bwe
-- Compiling entity ramb16bwe_s18
-- Compiling architecture ramb16bwe_s18_v of ramb16bwe_s18
-- Compiling entity ramb16bwe_s18_s18
-- Compiling architecture ramb16bwe_s18_s18_v of ramb16bwe_s18_s18
-- Compiling entity ramb16bwe_s18_s9
-- Compiling architecture ramb16bwe_s18_s9_v of ramb16bwe_s18_s9
-- Compiling entity ramb16bwe_s36
-- Compiling architecture ramb16bwe_s36_v of ramb16bwe_s36
-- Compiling entity ramb16bwe_s36_s18
-- Compiling architecture ramb16bwe_s36_s18_v of ramb16bwe_s36_s18
-- Compiling entity ramb16bwe_s36_s36
-- Compiling architecture ramb16bwe_s36_s36_v of ramb16bwe_s36_s36
-- Compiling entity ramb16bwe_s36_s9
-- Compiling architecture ramb16bwe_s36_s9_v of ramb16bwe_s36_s9
-- Loading package std_logic_textio
-- Loading package std_logic_unsigned
-- Compiling entity dataflash
-- Compiling architecture design of dataflash
-- Compiling entity spi_access
-- Compiling architecture spi_access_v of spi_access
-- Compiling entity startup_spartan3a
-- Compiling architecture startup_spartan3a_v of startup_spartan3a
-- Compiling entity dsp48a
-- Compiling architecture dsp48a_v of dsp48a
-- Compiling entity ramb16bwer
-- Compiling architecture ramb16bwer_v of ramb16bwer

END_COMPILE:unisim

==============================================================================

    > Log file /home/habea2/Geccko3com/gecko3com_v04/lib/unisim/cxl_unisim.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[unisim]: No error(s), no warning(s)

--> Compiling vhdl simprim library
    > Simprim compiled to /home/habea2/Geccko3com/gecko3com_v04/lib/simprim

==============================================================================
START_COMPILE simprim


Modifying modelsim.ini

Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package vital_timing
-- Compiling package vcomponents

Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package vital_timing
-- Loading package vital_primitives
-- Loading package textio
-- Compiling package vpackage
-- Compiling package body vpackage
-- Loading package vpackage

Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package vital_timing
-- Loading package vital_primitives
-- Compiling entity x_and16
-- Compiling architecture x_and16_v of x_and16
-- Compiling entity x_and2
-- Compiling architecture x_and2_v of x_and2
-- Compiling entity x_and3
-- Compiling architecture x_and3_v of x_and3
-- Compiling entity x_and32
-- Compiling architecture x_and32_v of x_and32
-- Compiling entity x_and4
-- Compiling architecture x_and4_v of x_and4
-- Compiling entity x_and5
-- Compiling architecture x_and5_v of x_and5
-- Compiling entity x_and6
-- Compiling architecture x_and6_v of x_and6
-- Compiling entity x_and7
-- Compiling architecture x_and7_v of x_and7
-- Compiling entity x_and8
-- Compiling architecture x_and8_v of x_and8
-- Compiling entity x_and9
-- Compiling architecture x_and9_v of x_and9
-- Compiling entity x_bpad
-- Compiling architecture x_bpad_v of x_bpad
-- Compiling entity x_bscan_fpgacore
-- Compiling architecture x_bscan_fpgacore_v of x_bscan_fpgacore
-- Compiling entity x_bscan_spartan2
-- Compiling architecture x_bscan_spartan2_v of x_bscan_spartan2
-- Compiling entity x_bscan_spartan3
-- Compiling architecture x_bscan_spartan3_v of x_bscan_spartan3
-- Compiling entity x_bscan_virtex
-- Compiling architecture x_bscan_virtex_v of x_bscan_virtex
-- Compiling entity x_bscan_virtex2
-- Compiling architecture x_bscan_virtex2_v of x_bscan_virtex2
-- Loading package textio
-- Loading package vpackage
-- Compiling entity x_buf
-- Compiling architecture x_buf_v of x_buf
-- Loading package vcomponents
-- Compiling entity x_bufgmux
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(1731):       tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(1731): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_bufgmux_v of x_bufgmux
-- Compiling entity x_bufgmux_1
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(1944):       tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(1944): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_bufgmux_1_v of x_bufgmux_1
-- Compiling entity x_ckbuf
-- Compiling architecture x_ckbuf_v of x_ckbuf
-- Compiling entity x_clk_div
-- Compiling architecture x_clk_div_v of x_clk_div
-- Compiling entity x_clkdll_maximum_period_check
-- Compiling architecture x_clkdll_maximum_period_check_v of x_clkdll_maximum_period_check
-- Compiling entity x_clkdll
-- Compiling architecture x_clkdll_v of x_clkdll
-- Compiling entity x_clkdlle_maximum_period_check
-- Compiling architecture x_clkdlle_maximum_period_check_v of x_clkdlle_maximum_period_check
-- Compiling entity x_clkdlle
-- Compiling architecture x_clkdlle_v of x_clkdlle
-- Compiling entity x_dcm_clock_divide_by_2
-- Compiling architecture x_dcm_clock_divide_by_2_v of x_dcm_clock_divide_by_2
-- Compiling entity x_dcm_maximum_period_check
-- Compiling architecture x_dcm_maximum_period_check_v of x_dcm_maximum_period_check
-- Compiling entity x_dcm_clock_lost
-- Compiling architecture x_dcm_clock_lost_v of x_dcm_clock_lost
-- Compiling entity x_dcm
-- Compiling architecture x_dcm_v of x_dcm
-- Compiling entity x_dcm_sp_clock_divide_by_2
-- Compiling architecture x_dcm_sp_clock_divide_by_2_v of x_dcm_sp_clock_divide_by_2
-- Compiling entity x_dcm_sp_maximum_period_check
-- Compiling architecture x_dcm_sp_maximum_period_check_v of x_dcm_sp_maximum_period_check
-- Compiling entity x_dcm_sp_clock_lost
-- Compiling architecture x_dcm_sp_clock_lost_v of x_dcm_sp_clock_lost
-- Compiling entity x_dcm_sp
-- Compiling architecture x_dcm_sp_v of x_dcm_sp
-- Compiling entity x_fdd
-- Compiling architecture x_fdd_v of x_fdd
-- Compiling entity x_fddrcpe
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8208):     tbpd_GSR_Q_C0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8208): (vcom-1288) VITAL timing generic "tbpd_gsr_q_c0" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8229):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8229): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8238):     tisd_GSR_C0 : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8238): (vcom-1288) VITAL timing generic "tisd_gsr_c0" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8239):     tisd_GSR_C1 : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8239): (vcom-1288) VITAL timing generic "tisd_gsr_c1" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8246):     tpd_GSR_Q : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8246): (vcom-1288) VITAL timing generic "tpd_gsr_q" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8254):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8254): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8259):     trecovery_GSR_C0_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8259): (vcom-1288) VITAL timing generic "trecovery_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8260):     trecovery_GSR_C1_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8260): (vcom-1288) VITAL timing generic "trecovery_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8266):     tremoval_GSR_C0_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8266): (vcom-1288) VITAL timing generic "tremoval_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8267):     tremoval_GSR_C1_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8267): (vcom-1288) VITAL timing generic "tremoval_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_fddrcpe_v of x_fddrcpe
-- Compiling entity x_fddrrse
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8736):     tbpd_GSR_Q_C0 : VitalDelayType01 := (0.000 ns, 0.000 ns);    
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8736): (vcom-1288) VITAL timing generic "tbpd_gsr_q_c0" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8763):     tipd_GSR : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8763): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8767):     tisd_GSR_C0 : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8767): (vcom-1288) VITAL timing generic "tisd_gsr_c0" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8768):     tisd_GSR_C1 : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8768): (vcom-1288) VITAL timing generic "tisd_gsr_c1" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8780):     tpd_GSR_Q : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8780): (vcom-1288) VITAL timing generic "tpd_gsr_q" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8786):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8786): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8790):     trecovery_GSR_C0_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8790): (vcom-1288) VITAL timing generic "trecovery_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8791):     trecovery_GSR_C1_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8791): (vcom-1288) VITAL timing generic "trecovery_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8793):     tremoval_GSR_C0_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8793): (vcom-1288) VITAL timing generic "tremoval_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8794):     tremoval_GSR_C1_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(8794): (vcom-1288) VITAL timing generic "tremoval_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_fddrrse_v of x_fddrrse
-- Compiling entity x_ff
-- Compiling architecture x_ff_v of x_ff
-- Compiling entity x_ff_cpld
-- Compiling architecture x_ff_cpld_v of x_ff_cpld
-- Compiling entity x_ibufds
-- Compiling architecture x_ibufds_v of x_ibufds
-- Compiling entity x_inv
-- Compiling architecture x_inv_v of x_inv
-- Compiling entity x_ipad
-- Compiling architecture x_ipad_v of x_ipad
-- Compiling entity x_keeper
-- Compiling architecture x_keeper_v of x_keeper
-- Compiling entity x_latch
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10318):       tpd_GSR_O  : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10318): (vcom-1288) VITAL timing generic "tpd_gsr_o" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10319):       tpd_PRLD_O : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10319): (vcom-1288) VITAL timing generic "tpd_prld_o" port specification "prld" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_latch_v of x_latch
-- Compiling entity x_latch_cpld
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10612):       tpd_GSR_O  : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10612): (vcom-1288) VITAL timing generic "tpd_gsr_o" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10613):       tpd_PRLD_O : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10613): (vcom-1288) VITAL timing generic "tpd_prld_o" port specification "prld" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_latch_cpld_v of x_latch_cpld
-- Compiling entity x_latche
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10909):       tpd_GSR_O  : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10909): (vcom-1288) VITAL timing generic "tpd_gsr_o" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10910):       tpd_PRLD_O : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(10910): (vcom-1288) VITAL timing generic "tpd_prld_o" port specification "prld" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_latche_v of x_latche
-- Compiling entity x_lut2
-- Compiling architecture x_lut2_v of x_lut2
-- Compiling entity x_lut3
-- Compiling architecture x_lut3_v of x_lut3
-- Compiling entity x_lut4
-- Compiling architecture x_lut4_v of x_lut4
-- Compiling entity x_lut5
-- Compiling architecture x_lut5_v of x_lut5
-- Compiling entity x_lut6
-- Compiling architecture x_lut6_v of x_lut6
-- Compiling entity x_lut7
-- Compiling architecture x_lut7_v of x_lut7
-- Compiling entity x_lut8
-- Compiling architecture x_lut8_v of x_lut8
-- Compiling entity x_mult18x18
-- Compiling architecture x_mult18x18_v of x_mult18x18
-- Compiling entity x_mult18x18s
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13831):       tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13831): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13834):       tpd_GSR_P :     VitalDelayArrayType01 (35 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13834): (vcom-1288) VITAL timing generic "tpd_gsr_p" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13836):       trecovery_GSR_C_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13836): (vcom-1288) VITAL timing generic "trecovery_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13852):       thold_GSR_C_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13852): (vcom-1288) VITAL timing generic "thold_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13860):       tisd_GSR_C : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13860): (vcom-1288) VITAL timing generic "tisd_gsr_c" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13865):       tpw_GSR_posedge : VitalDelayType := 0.000 ns
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(13865): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_mult18x18s_v of x_mult18x18s
-- Compiling entity x_mux2
-- Compiling architecture x_mux2_v of x_mux2
-- Compiling entity x_muxddr
-- Compiling architecture x_muxddr_v of x_muxddr
-- Compiling entity x_obuf
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15701):       tpd_GTS_O : VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15701): (vcom-1288) VITAL timing generic "tpd_gts_o" port specification "gts" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_obuf_v of x_obuf
-- Compiling entity x_obufds
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15830):       tpd_GTS_O : VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15830): (vcom-1288) VITAL timing generic "tpd_gts_o" port specification "gts" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15831):       tpd_GTS_OB : VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15831): (vcom-1288) VITAL timing generic "tpd_gts_ob" port specification "gts" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_obufds_v of x_obufds
-- Compiling entity x_obuft
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15999):       tpd_GTS_O : VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(15999): (vcom-1288) VITAL timing generic "tpd_gts_o" port specification "gts" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_obuft_v of x_obuft
-- Compiling entity x_obuftds
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(16136):       tpd_GTS_O : VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(16136): (vcom-1288) VITAL timing generic "tpd_gts_o" port specification "gts" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(16137):       tpd_GTS_OB : VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(16137): (vcom-1288) VITAL timing generic "tpd_gts_ob" port specification "gts" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_obuftds_v of x_obuftds
-- Compiling entity x_one
-- Compiling architecture x_one_v of x_one
-- Compiling entity x_opad
-- Compiling architecture x_opad_v of x_opad
-- Compiling entity x_or16
-- Compiling architecture x_or16_v of x_or16
-- Compiling entity x_or2
-- Compiling architecture x_or2_v of x_or2
-- Compiling entity x_or3
-- Compiling architecture x_or3_v of x_or3
-- Compiling entity x_or32
-- Compiling architecture x_or32_v of x_or32
-- Compiling entity x_or4
-- Compiling architecture x_or4_v of x_or4
-- Compiling entity x_or5
-- Compiling architecture x_or5_v of x_or5
-- Compiling entity x_or6
-- Compiling architecture x_or6_v of x_or6
-- Compiling entity x_or7
-- Compiling architecture x_or7_v of x_or7
-- Compiling entity x_or8
-- Compiling architecture x_or8_v of x_or8
-- Compiling entity x_or9
-- Compiling architecture x_or9_v of x_or9
-- Compiling entity x_pd
-- Compiling architecture x_pd_v of x_pd
-- Compiling entity x_pu
-- Compiling architecture x_pu_v of x_pu
-- Compiling entity x_ramb16_s1
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17743):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17743): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17748):     tpd_GSR_DO : VitalDelayArrayType01 (0 downto 0) := (others => (0.0 ns, 0.0 ns));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17748): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17750):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17750): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17768):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17768): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17778):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17778): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17784):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(17784): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s1_v of x_ramb16_s1
-- Compiling entity x_ramb16_s18
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18556):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18556): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18562):     tpd_GSR_DO : VitalDelayArrayType01 (15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18562): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18563):     tpd_GSR_DOP : VitalDelayArrayType01 (1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18563): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18565):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18565): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18587):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18587): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18598):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18598): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18604):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(18604): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s18_v of x_ramb16_s18
-- Compiling entity x_ramb16_s18_s18
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19938):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19938): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19940):     tpd_GSR_DOA  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19940): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19941):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19941): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19942):     tpd_GSR_DOPA : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19942): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19943):     tpd_GSR_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19943): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19950):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19950): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19964):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19964): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19986):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(19986): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20000):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20000): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20006):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20006): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20007):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20007): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20013):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20013): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20017):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20017): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20018):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20018): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20024):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20024): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20032):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(20032): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s18_s18_v of x_ramb16_s18_s18
-- Compiling entity x_ramb16_s18_s36
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23000):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23000): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23002):     tpd_GSR_DOA  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23002): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23003):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23003): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23004):     tpd_GSR_DOPA : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23004): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23005):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23005): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23012):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23012): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23026):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23026): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23048):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23048): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23062):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23062): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23068):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23068): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23069):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23069): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23075):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23075): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23079):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23079): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23080):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23080): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23086):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23086): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23094):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(23094): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s18_s36_v of x_ramb16_s18_s36
-- Compiling entity x_ramb16_s1_s1
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26668):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26668): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26670):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26670): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26671):     tpd_GSR_DOB  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26671): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26676):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26676): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26688):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26688): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26706):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26706): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26718):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26718): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26724):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26724): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26729):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26729): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26733):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26733): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26738):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26738): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26746):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(26746): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s1_s1_v of x_ramb16_s1_s1
-- Compiling entity x_ramb16_s1_s18
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28593):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28593): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28595):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28595): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28596):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28596): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28597):     tpd_GSR_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28597): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28603):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28603): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28615):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28615): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28635):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28635): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28649):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28649): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28655):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28655): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28660):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28660): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28664):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28664): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28665):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28665): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28671):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28671): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28679):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(28679): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s1_s18_v of x_ramb16_s1_s18
-- Compiling entity x_ramb16_s1_s2
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31088):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31088): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31090):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31090): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31091):     tpd_GSR_DOB  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31091): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31096):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31096): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31108):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31108): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31126):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31126): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31138):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31138): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31144):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31144): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31149):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31149): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31153):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31153): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31158):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31158): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31166):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(31166): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s1_s2_v of x_ramb16_s1_s2
-- Compiling entity x_ramb16_s1_s36
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33026):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33026): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33028):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33028): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33029):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33029): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33030):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33030): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33036):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33036): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33048):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33048): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33068):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33068): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33082):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33082): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33088):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33088): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33093):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33093): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33097):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33097): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33098):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33098): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33104):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33104): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33112):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(33112): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s1_s36_v of x_ramb16_s1_s36
-- Compiling entity x_ramb16_s1_s4
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36129):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36129): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36131):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36131): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36132):     tpd_GSR_DOB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36132): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36137):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36137): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36149):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36149): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36167):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36167): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36179):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36179): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36185):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36185): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36190):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36190): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36194):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36194): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36199):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36199): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36207):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(36207): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s1_s4_v of x_ramb16_s1_s4
-- Compiling entity x_ramb16_s1_s9
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38115):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38115): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38117):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38117): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38118):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38118): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38119):     tpd_GSR_DOPB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38119): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38125):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38125): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38137):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38137): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38157):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38157): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38171):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38171): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38177):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38177): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38182):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38182): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38186):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38186): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38187):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38187): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38193):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38193): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38201):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(38201): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s1_s9_v of x_ramb16_s1_s9
-- Compiling entity x_ramb16_s2
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40310):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40310): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40315):     tpd_GSR_DO : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40315): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40317):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40317): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40335):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40335): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40345):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40345): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40351):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(40351): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s2_v of x_ramb16_s2
-- Compiling entity x_ramb16_s2_s18
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41144):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41144): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41146):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41146): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41147):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41147): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41148):     tpd_GSR_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41148): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41154):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41154): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41166):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41166): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41186):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41186): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41200):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41200): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41206):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41206): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41211):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41211): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41215):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41215): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41216):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41216): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41222):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41222): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41230):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(41230): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s2_s18_v of x_ramb16_s2_s18
-- Compiling entity x_ramb16_s2_s2
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43652):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43652): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43654):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43654): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43655):     tpd_GSR_DOB  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43655): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43660):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43660): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43672):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43672): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43690):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43690): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43702):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43702): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43708):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43708): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43713):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43713): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43717):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43717): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43722):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43722): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43730):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(43730): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s2_s2_v of x_ramb16_s2_s2
-- Compiling entity x_ramb16_s2_s36
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45603):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45603): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45605):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45605): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45606):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45606): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45607):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45607): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45613):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45613): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45625):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45625): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45645):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45645): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45659):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45659): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45665):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45665): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45670):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45670): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45674):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45674): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45675):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45675): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45681):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45681): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45689):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(45689): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s2_s36_v of x_ramb16_s2_s36
-- Compiling entity x_ramb16_s2_s4
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48719):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48719): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48721):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48721): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48722):     tpd_GSR_DOB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48722): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48727):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48727): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48739):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48739): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48757):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48757): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48769):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48769): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48775):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48775): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48780):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48780): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48784):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48784): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48789):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48789): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48797):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(48797): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s2_s4_v of x_ramb16_s2_s4
-- Compiling entity x_ramb16_s2_s9
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50718):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50718): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50720):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50720): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50721):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50721): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50722):     tpd_GSR_DOPB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50722): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50728):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50728): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50740):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50740): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50760):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50760): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50774):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50774): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50780):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50780): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50785):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50785): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50789):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50789): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50790):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50790): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50796):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50796): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50804):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(50804): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s2_s9_v of x_ramb16_s2_s9
-- Compiling entity x_ramb16_s36
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52929):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52929): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52935):     tpd_GSR_DO  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52935): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52936):     tpd_GSR_DOP : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52936): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52938):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52938): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52960):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52960): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52971):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52971): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52977):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(52977): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s36_v of x_ramb16_s36
-- Compiling entity x_ramb16_s36_s36
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54921):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54921): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54923):     tpd_GSR_DOA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54923): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54924):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54924): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54925):     tpd_GSR_DOPA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54925): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54926):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54926): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54933):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54933): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54947):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54947): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54969):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54969): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54983):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54983): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54989):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54989): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54990):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54990): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54996):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(54996): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55000):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55000): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55001):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55001): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55007):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55007): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55015):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(55015): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s36_s36_v of x_ramb16_s36_s36
-- Compiling entity x_ramb16_s4
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59191):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59191): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59196):     tpd_GSR_DO : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59196): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59198):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59198): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59216):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59216): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59226):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59226): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59232):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(59232): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s4_v of x_ramb16_s4
-- Compiling entity x_ramb16_s4_s18
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60069):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60069): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60071):     tpd_GSR_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60071): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60072):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60072): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60073):     tpd_GSR_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60073): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60079):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60079): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60091):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60091): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60111):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60111): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60125):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60125): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60131):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60131): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60136):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60136): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60140):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60140): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60141):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60141): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60147):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60147): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60155):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(60155): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s4_s18_v of x_ramb16_s4_s18
-- Compiling entity x_ramb16_s4_s36
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62626):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62626): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62628):     tpd_GSR_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62628): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62629):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62629): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62630):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62630): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62636):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62636): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62648):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62648): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62668):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62668): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62682):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62682): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62688):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62688): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62693):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62693): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62697):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62697): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62698):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62698): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62704):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62704): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62712):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(62712): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s4_s36_v of x_ramb16_s4_s36
-- Compiling entity x_ramb16_s4_s4
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65790):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65790): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65792):     tpd_GSR_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65792): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65793):     tpd_GSR_DOB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65793): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65798):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65798): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65810):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65810): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65828):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65828): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65840):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65840): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65846):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65846): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65851):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65851): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65855):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65855): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65860):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65860): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65868):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(65868): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s4_s4_v of x_ramb16_s4_s4
-- Compiling entity x_ramb16_s4_s9
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67837):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67837): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67839):     tpd_GSR_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67839): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67840):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67840): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67841):     tpd_GSR_DOPB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67841): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67847):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67847): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67859):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67859): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67879):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67879): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67893):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67893): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67899):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67899): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67904):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67904): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67908):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67908): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67909):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67909): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67915):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67915): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67923):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(67923): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s4_s9_v of x_ramb16_s4_s9
-- Compiling entity x_ramb16_s9
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70094):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70094): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70100):     tpd_GSR_DO  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70100): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70101):     tpd_GSR_DOP : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70101): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70103):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70103): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70125):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70125): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70136):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70136): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70142):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(70142): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s9_v of x_ramb16_s9
-- Compiling entity x_ramb16_s9_s18
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71180):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71180): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71182):     tpd_GSR_DOA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71182): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71183):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71183): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71184):     tpd_GSR_DOPA : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71184): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71185):     tpd_GSR_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71185): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71192):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71192): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71206):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71206): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71228):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71228): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71242):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71242): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71248):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71248): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71249):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71249): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71255):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71255): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71259):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71259): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71260):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71260): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71266):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71266): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71274):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(71274): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s9_s18_v of x_ramb16_s9_s18
-- Compiling entity x_ramb16_s9_s36
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73949):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73949): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73951):     tpd_GSR_DOA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73951): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73952):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73952): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73953):     tpd_GSR_DOPA : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73953): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73954):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73954): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73961):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73961): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73975):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73975): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73997):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(73997): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74011):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74011): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74017):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74017): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74018):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74018): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74024):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74024): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74028):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74028): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74029):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74029): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74035):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74035): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74043):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(74043): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s9_s36_v of x_ramb16_s9_s36
-- Compiling entity x_ramb16_s9_s9
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77326):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77326): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77328):     tpd_GSR_DOA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77328): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77329):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77329): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77330):     tpd_GSR_DOPA : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77330): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77331):     tpd_GSR_DOPB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77331): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77338):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77338): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77352):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77352): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77374):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77374): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77388):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77388): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77394):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77394): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77395):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77395): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77401):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77401): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77405):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77405): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77406):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(0 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77406): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77412):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77412): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77420):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(77420): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_s9_s9_v of x_ramb16_s9_s9
-- Compiling entity x_ramb4_s1
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79794):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79794): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79799):     tpd_GSR_DO : VitalDelayArrayType01 (0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79799): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79801):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79801): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79819):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79819): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79829):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79829): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79835):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(79835): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s1_v of x_ramb4_s1
-- Compiling entity x_ramb4_s16
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80463):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80463): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80468):     tpd_GSR_DO : VitalDelayArrayType01 (15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80468): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80470):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80470): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80488):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80488): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80498):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80498): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80504):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(80504): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s16_v of x_ramb4_s16
-- Compiling entity x_ramb4_s16_s16
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81574):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81574): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81578):     tpd_GSR_DOA  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81578): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81579):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81579): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81581):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81581): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81593):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81593): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81611):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81611): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81623):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81623): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81629):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81629): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81634):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81634): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81638):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81638): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81643):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81643): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81651):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(81651): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s16_s16_v of x_ramb4_s16_s16
-- Compiling entity x_ramb4_s1_s1
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83835):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83835): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83839):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83839): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83840):     tpd_GSR_DOB  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83840): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83842):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83842): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83854):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83854): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83872):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83872): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83884):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83884): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83890):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83890): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83895):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83895): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83899):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83899): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83904):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83904): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83912):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(83912): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s1_s1_v of x_ramb4_s1_s1
-- Compiling entity x_ramb4_s1_s16
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85222):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85222): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85226):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85226): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85227):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85227): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85229):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85229): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85241):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85241): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85259):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85259): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85271):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85271): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85277):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85277): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85282):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85282): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85286):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85286): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85291):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85291): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85299):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(85299): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s1_s16_v of x_ramb4_s1_s16
-- Compiling entity x_ramb4_s1_s2
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87046):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87046): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87050):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87050): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87051):     tpd_GSR_DOB  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87051): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87053):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87053): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87065):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87065): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87083):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87083): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87095):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87095): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87101):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87101): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87106):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87106): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87110):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87110): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87115):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87115): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87123):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(87123): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s1_s2_v of x_ramb4_s1_s2
-- Compiling entity x_ramb4_s1_s4
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88446):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88446): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88450):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88450): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88451):     tpd_GSR_DOB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88451): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88453):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88453): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88465):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88465): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88483):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88483): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88495):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88495): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88501):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88501): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88506):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88506): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88510):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88510): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88515):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88515): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88523):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(88523): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s1_s4_v of x_ramb4_s1_s4
-- Compiling entity x_ramb4_s1_s8
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89894):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89894): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89898):     tpd_GSR_DOA  : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89898): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89899):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89899): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89901):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89901): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89913):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89913): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89931):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89931): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89943):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89943): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89949):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(0 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89949): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89954):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89954): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89958):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89958): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89963):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89963): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89971):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(89971): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s1_s8_v of x_ramb4_s1_s8
-- Compiling entity x_ramb4_s2
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91457):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91457): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91462):     tpd_GSR_DO : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91462): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91464):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91464): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91482):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91482): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91492):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91492): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91498):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(91498): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s2_v of x_ramb4_s2
-- Compiling entity x_ramb4_s2_s16
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92141):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92141): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92145):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92145): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92146):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92146): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92148):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92148): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92160):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92160): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92178):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92178): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92190):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92190): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92196):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92196): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92201):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92201): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92205):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92205): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92210):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92210): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92218):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(92218): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s2_s16_v of x_ramb4_s2_s16
-- Compiling entity x_ramb4_s2_s2
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93978):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93978): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93982):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93982): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93983):     tpd_GSR_DOB  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93983): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93985):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93985): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93997):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(93997): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94015):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94015): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94027):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94027): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94033):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94033): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94038):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94038): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94042):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94042): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94047):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94047): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94055):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(94055): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s2_s2_v of x_ramb4_s2_s2
-- Compiling entity x_ramb4_s2_s4
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95391):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95391): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95395):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95395): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95396):     tpd_GSR_DOB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95396): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95398):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95398): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95410):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95410): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95428):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95428): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95440):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95440): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95446):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95446): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95451):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95451): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95455):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95455): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95460):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95460): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95468):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(95468): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s2_s4_v of x_ramb4_s2_s4
-- Compiling entity x_ramb4_s2_s8
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96852):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96852): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96856):     tpd_GSR_DOA  : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96856): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96857):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96857): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96859):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96859): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96871):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96871): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96889):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96889): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96901):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96901): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96907):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(1 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96907): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96912):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96912): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96916):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96916): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96921):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96921): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96929):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(96929): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s2_s8_v of x_ramb4_s2_s8
-- Compiling entity x_ramb4_s4
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98425):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98425): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98430):     tpd_GSR_DO : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98430): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98432):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98432): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98450):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98450): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98460):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98460): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98466):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(98466): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s4_v of x_ramb4_s4
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package vital_timing
-- Loading package vital_primitives
-- Loading package textio
-- Loading package vpackage
-- Loading package vcomponents
-- Compiling entity x_ramb4_s4_s16
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99158):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99158): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99162):     tpd_GSR_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99162): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99163):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99163): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99165):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99165): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99177):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99177): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99195):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99195): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99207):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99207): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99213):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99213): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99218):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99218): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99222):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99222): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99227):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99227): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99235):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(99235): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s4_s16_v of x_ramb4_s4_s16
-- Compiling entity x_ramb4_s4_s4
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101043):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101043): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101047):     tpd_GSR_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101047): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101048):     tpd_GSR_DOB  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101048): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101050):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101050): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101062):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101062): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101080):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101080): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101092):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101092): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101098):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101098): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101103):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101103): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101107):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101107): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101112):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101112): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101120):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(101120): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s4_s4_v of x_ramb4_s4_s4
-- Compiling entity x_ramb4_s4_s8
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102552):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102552): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102556):     tpd_GSR_DOA  : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102556): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102557):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102557): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102559):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102559): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102571):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102571): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102589):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102589): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102601):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102601): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102607):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(3 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102607): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102612):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102612): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102616):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102616): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102621):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102621): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102629):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(102629): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s4_s8_v of x_ramb4_s4_s8
-- Compiling entity x_ramb4_s8
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104174):     tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104174): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104179):     tpd_GSR_DO : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104179): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104181):     trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104181): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104199):     thold_GSR_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104199): (vcom-1288) VITAL timing generic "thold_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104209):     tisd_GSR_CLK : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104209): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104215):     tpw_GSR_posedge : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(104215): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s8_v of x_ramb4_s8
-- Compiling entity x_ramb4_s8_s16
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105022):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105022): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105026):     tpd_GSR_DOA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105026): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105027):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105027): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105029):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105029): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105041):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105041): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105059):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105059): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105071):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105071): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105077):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105077): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105082):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105082): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105086):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105086): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105091):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105091): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105099):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(105099): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s8_s16_v of x_ramb4_s8_s16
-- Compiling entity x_ramb4_s8_s8
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107025):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107025): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107029):     tpd_GSR_DOA  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107029): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107030):     tpd_GSR_DOB  : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107030): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107032):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107032): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107044):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107044): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107062):     thold_GSR_CLKA_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107062): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107074):     thold_GSR_CLKB_negedge_posedge   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107074): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107080):     tbpd_GSR_DOA_CLKA : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107080): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107085):     tisd_GSR_CLKA     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107085): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107089):     tbpd_GSR_DOB_CLKB : VitalDelayArrayType01(7 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107089): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107094):     tisd_GSR_CLKB     : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107094): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107102):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(107102): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb4_s8_s8_v of x_ramb4_s8_s8
-- Compiling entity x_ramd16
-- Compiling architecture x_ramd16_v of x_ramd16
-- Compiling entity x_ramd32
-- Compiling architecture x_ramd32_v of x_ramd32
-- Compiling entity x_ramd64
-- Compiling architecture x_ramd64_v of x_ramd64
-- Compiling entity x_rams128
-- Compiling architecture x_rams128_v of x_rams128
-- Compiling entity x_rams16
-- Compiling architecture x_rams16_v of x_rams16
-- Compiling entity x_rams32
-- Compiling architecture x_rams32_v of x_rams32
-- Compiling entity x_rams64
-- Compiling architecture x_rams64_v of x_rams64
-- Compiling entity x_roc
-- Compiling architecture x_roc_v of x_roc
-- Compiling entity x_rocbuf
-- Compiling architecture x_rocbuf_v of x_rocbuf
-- Compiling entity x_sff
-- Compiling architecture x_sff_v of x_sff
-- Compiling entity x_srl16e
-- Compiling architecture x_srl16e_v of x_srl16e
-- Compiling entity x_srlc16e
-- Compiling architecture x_srlc16e_v of x_srlc16e
-- Compiling entity x_suh
-- Compiling architecture x_suh_v of x_suh
-- Compiling entity x_toc
-- Compiling architecture x_toc_v of x_toc
-- Compiling entity x_tocbuf
-- Compiling architecture x_tocbuf_v of x_tocbuf
-- Compiling entity x_tri
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(112957):     tpd_GTS_O : VitalDelayType01z := (0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(112957): (vcom-1288) VITAL timing generic "tpd_gts_o" port specification "gts" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_tri_v of x_tri
-- Compiling entity x_upad
-- Compiling architecture x_upad_v of x_upad
-- Compiling entity x_xor16
-- Compiling architecture x_xor16_v of x_xor16
-- Compiling entity x_xor2
-- Compiling architecture x_xor2_v of x_xor2
-- Compiling entity x_xor3
-- Compiling architecture x_xor3_v of x_xor3
-- Compiling entity x_xor32
-- Compiling architecture x_xor32_v of x_xor32
-- Compiling entity x_xor4
-- Compiling architecture x_xor4_v of x_xor4
-- Compiling entity x_xor5
-- Compiling architecture x_xor5_v of x_xor5
-- Compiling entity x_xor6
-- Compiling architecture x_xor6_v of x_xor6
-- Compiling entity x_xor7
-- Compiling architecture x_xor7_v of x_xor7
-- Compiling entity x_xor8
-- Compiling architecture x_xor8_v of x_xor8
-- Compiling entity x_zero
-- Compiling architecture x_zero_v of x_zero
-- Compiling entity x_bscan_virtex4
-- Compiling architecture x_bscan_virtex4_v of x_bscan_virtex4
-- Compiling entity x_bufgctrl
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114440):       tbpd_GSR_O_I0       : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114440): (vcom-1288) VITAL timing generic "tbpd_gsr_o_i0" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114445):       tipd_GSR       : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114445): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114457):       tpd_GSR_O      : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114457): (vcom-1288) VITAL timing generic "tpd_gsr_o" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114465):       tisd_GSR_I0    : VitalDelayType   := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114465): (vcom-1288) VITAL timing generic "tisd_gsr_i0" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114466):       tisd_GSR_I1    : VitalDelayType   := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114466): (vcom-1288) VITAL timing generic "tisd_gsr_i1" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114579):       tpw_GSR_posedge              : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114579): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114586):       trecovery_GSR_I0_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114586): (vcom-1288) VITAL timing generic "trecovery_gsr_i0_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114587):       trecovery_GSR_I1_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114587): (vcom-1288) VITAL timing generic "trecovery_gsr_i1_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114590):       tremoval_GSR_I0_negedge_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114590): (vcom-1288) VITAL timing generic "tremoval_gsr_i0_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114591):       tremoval_GSR_I1_negedge_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(114591): (vcom-1288) VITAL timing generic "tremoval_gsr_i1_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_bufgctrl_v of x_bufgctrl
-- Compiling entity x_bufr
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115230):       tipd_GSR  : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115230): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115243):       tpd_GSR_O : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115243): (vcom-1288) VITAL timing generic "tpd_gsr_o" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115247):       tisd_GSR_I : VitalDelayType   := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115247): (vcom-1288) VITAL timing generic "tisd_gsr_i" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115265):       tpw_GSR_posedge            : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115265): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115272):       trecovery_GSR_I_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115272): (vcom-1288) VITAL timing generic "trecovery_gsr_i_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115276):       tremoval_GSR_I_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(115276): (vcom-1288) VITAL timing generic "tremoval_gsr_i_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_bufr_v of x_bufr
-- Compiling entity x_dcm_adv_clock_divide_by_2
-- Compiling architecture x_dcm_adv_clock_divide_by_2_v of x_dcm_adv_clock_divide_by_2
-- Compiling entity x_dcm_adv_maximum_period_check
-- Compiling architecture x_dcm_adv_maximum_period_check_v of x_dcm_adv_maximum_period_check
-- Compiling entity x_dcm_adv_clock_lost
-- Compiling architecture x_dcm_adv_clock_lost_v of x_dcm_adv_clock_lost
-- Compiling entity x_dcm_adv
-- Compiling architecture x_dcm_adv_v of x_dcm_adv
-- Loading package std_logic_arith
-- Loading package std_logic_signed
-- Compiling entity x_dsp48
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(118546):         tipd_GSR        : VitalDelayType01 := ( 0 ps,  0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(118546): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(118711):         tisd_GSR_CLK            : VitalDelayType  := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(118711): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(118731):         trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(118731): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_dsp48_v of x_dsp48
-- Compiling entity x_fifo16
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141381):     tipd_GSR   : VitalDelayType01                   := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141381): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141397):     tpd_GSR_DO            : VitalDelayArrayType01 (31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141397): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141398):     tpd_GSR_DOP           : VitalDelayArrayType01 (3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141398): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141399):     tpd_GSR_EMPTY         : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141399): (vcom-1288) VITAL timing generic "tpd_gsr_empty" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141400):     tpd_GSR_ALMOSTEMPTY   : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141400): (vcom-1288) VITAL timing generic "tpd_gsr_almostempty" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141401):     tpd_GSR_FULL          : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141401): (vcom-1288) VITAL timing generic "tpd_gsr_full" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141402):     tpd_GSR_ALMOSTFULL    : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141402): (vcom-1288) VITAL timing generic "tpd_gsr_almostfull" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141403):     tpd_GSR_RDCOUNT       : VitalDelayArrayType01 (11 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141403): (vcom-1288) VITAL timing generic "tpd_gsr_rdcount" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141404):     tpd_GSR_RDERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141404): (vcom-1288) VITAL timing generic "tpd_gsr_rderr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141405):     tpd_GSR_WRCOUNT       : VitalDelayArrayType01 (11 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141405): (vcom-1288) VITAL timing generic "tpd_gsr_wrcount" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141406):     tpd_GSR_WRERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141406): (vcom-1288) VITAL timing generic "tpd_gsr_wrerr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141419):     trecovery_GSR_WRCLK_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141419): (vcom-1288) VITAL timing generic "trecovery_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141420):     trecovery_GSR_RDCLK_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141420): (vcom-1288) VITAL timing generic "trecovery_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141427):     tremoval_GSR_WRCLK_negedge_posedge : VitalDelayType  := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141427): (vcom-1288) VITAL timing generic "tremoval_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141428):     tremoval_GSR_RDCLK_negedge_posedge : VitalDelayType  := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141428): (vcom-1288) VITAL timing generic "tremoval_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141459):     tisd_GSR_WRCLK   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(141459): (vcom-1288) VITAL timing generic "tisd_gsr_wrclk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_fifo16_v of x_fifo16
-- Compiling entity x_gt11clk
-- Compiling architecture x_gt11clk_v of x_gt11clk
-- Compiling entity x_iddr
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144426):       tipd_GSR  : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144426): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144443):       tpd_GSR_Q1 : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144443): (vcom-1288) VITAL timing generic "tpd_gsr_q1" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144444):       tpd_GSR_Q2 : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144444): (vcom-1288) VITAL timing generic "tpd_gsr_q2" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144451):       tisd_GSR_C : VitalDelayType   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144451): (vcom-1288) VITAL timing generic "tisd_gsr_c" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144495):       tpw_GSR_posedge            : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144495): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144503):       trecovery_GSR_C_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144503): (vcom-1288) VITAL timing generic "trecovery_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144514):       tremoval_GSR_C_negedge_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(144514): (vcom-1288) VITAL timing generic "tremoval_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_iddr_v of x_iddr
-- Compiling entity x_idelay
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145137):       tipd_GSR    : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145137): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145148):       tpd_GSR_O : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145148): (vcom-1288) VITAL timing generic "tpd_gsr_o" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145152):       tisd_GSR_C  : VitalDelayType  := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145152): (vcom-1288) VITAL timing generic "tisd_gsr_c" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145175):       tpw_GSR_posedge             : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145175): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145181):       trecovery_GSR_C_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145181): (vcom-1288) VITAL timing generic "trecovery_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145184):       tremoval_GSR_C_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(145184): (vcom-1288) VITAL timing generic "tremoval_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_idelay_v of x_idelay
-- Compiling entity x_idelayctrl
-- Compiling architecture x_idelayctrl_v of x_idelayctrl
-- Compiling entity bscntrl
-- Compiling architecture bscntrl_v of bscntrl
-- Compiling entity ice_module
-- Compiling architecture ice_v of ice_module
-- Compiling entity x_iserdes
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146363):       tipd_GSR              : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146363): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146388):       tpd_GSR_Q1    : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146388): (vcom-1288) VITAL timing generic "tpd_gsr_q1" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146389):       tpd_GSR_Q2    : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146389): (vcom-1288) VITAL timing generic "tpd_gsr_q2" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146390):       tpd_GSR_Q3    : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146390): (vcom-1288) VITAL timing generic "tpd_gsr_q3" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146391):       tpd_GSR_Q4    : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146391): (vcom-1288) VITAL timing generic "tpd_gsr_q4" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146392):       tpd_GSR_Q5    : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146392): (vcom-1288) VITAL timing generic "tpd_gsr_q5" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146393):       tpd_GSR_Q6    : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146393): (vcom-1288) VITAL timing generic "tpd_gsr_q6" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146409):       tisd_GSR                      : VitalDelayType := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146409): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146412):       tisd_SHIFTIN1         : VitalDelayType := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146412): (vcom-1287) VITAL timing generic "tisd_shiftin1" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146413):       tisd_SHIFTIN2         : VitalDelayType := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146413): (vcom-1287) VITAL timing generic "tisd_shiftin2" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146496):       tpw_GSR_posedge       : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146496): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146504):       trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146504): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146509):       tremoval_GSR_CLK_negedge_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(146509): (vcom-1288) VITAL timing generic "tremoval_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_iserdes_v of x_iserdes
-- Compiling entity x_oddr
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148383):       tipd_GSR  : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148383): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148397):       tpd_GSR_Q : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148397): (vcom-1288) VITAL timing generic "tpd_gsr_q" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148405):       tisd_GSR_C : VitalDelayType   := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148405): (vcom-1288) VITAL timing generic "tisd_gsr_c" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148459):       tpw_GSR_negedge            : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148459): (vcom-1288) VITAL timing generic "tpw_gsr_negedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148460):       tpw_GSR_posedge            : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148460): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148472):       trecovery_GSR_C_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148472): (vcom-1288) VITAL timing generic "trecovery_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148479):       tremoval_GSR_C_negedge_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(148479): (vcom-1288) VITAL timing generic "tremoval_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_oddr_v of x_oddr
-- Compiling entity x_plg
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149072):       tisd_C23              : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149072): (vcom-1287) VITAL timing generic "tisd_c23" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149073):       tisd_C45              : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149073): (vcom-1287) VITAL timing generic "tisd_c45" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149074):       tisd_C67              : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149074): (vcom-1287) VITAL timing generic "tisd_c67" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149075):       tisd_GSR              : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149075): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149076):       tisd_RST              : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149076): (vcom-1287) VITAL timing generic "tisd_rst" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149077):       tisd_SEL              : VitalDelayArrayType(1 downto 0) :=  (others => 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149077): (vcom-1287) VITAL timing generic "tisd_sel" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149086):       tpw_R_posedge : VitalDelayType := 0.0 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149086): (vcom-1288) VITAL timing generic "tpw_r_posedge" port specification "r" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149087):       tpw_S_posedge : VitalDelayType := 0.0 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149087): (vcom-1288) VITAL timing generic "tpw_s_posedge" port specification "s" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149094):       trecovery_R_CLK_negedge_posedge   : VitalDelayType := 0.0 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149094): (vcom-1288) VITAL timing generic "trecovery_r_clk_negedge_posedge" port specification "r" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149095):       trecovery_S_CLK_negedge_posedge   : VitalDelayType := 0.0 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149095): (vcom-1288) VITAL timing generic "trecovery_s_clk_negedge_posedge" port specification "s" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149099):       tremoval_R_CLK_negedge_posedge    : VitalDelayType := 0.0 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149099): (vcom-1288) VITAL timing generic "tremoval_r_clk_negedge_posedge" port specification "r" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149100):       tremoval_S_CLK_negedge_posedge    : VitalDelayType := 0.0 ns
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149100): (vcom-1288) VITAL timing generic "tremoval_s_clk_negedge_posedge" port specification "s" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_plg_v of x_plg
-- Compiling entity x_ioout
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149456):       tisd_D1                       : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149456): (vcom-1287) VITAL timing generic "tisd_d1" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149457):       tisd_D2                       : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149457): (vcom-1287) VITAL timing generic "tisd_d2" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149458):       tisd_D3                       : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149458): (vcom-1287) VITAL timing generic "tisd_d3" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149459):       tisd_D4                       : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149459): (vcom-1287) VITAL timing generic "tisd_d4" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149460):       tisd_D5                       : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149460): (vcom-1287) VITAL timing generic "tisd_d5" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149461):       tisd_D6                       : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149461): (vcom-1287) VITAL timing generic "tisd_d6" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149462):       tisd_GSR                      : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149462): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149463):       tisd_OCE                      : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149463): (vcom-1287) VITAL timing generic "tisd_oce" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149464):       tisd_REV                      : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149464): (vcom-1287) VITAL timing generic "tisd_rev" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149465):       tisd_SR                       : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149465): (vcom-1287) VITAL timing generic "tisd_sr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149466):       tisd_SHIFTIN1         : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149466): (vcom-1287) VITAL timing generic "tisd_shiftin1" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149467):       tisd_SHIFTIN2         : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(149467): (vcom-1287) VITAL timing generic "tisd_shiftin2" has invalid port specification.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ioout_v of x_ioout
-- Compiling entity x_iot
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150483):       tisd_GSR                  : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150483): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150484):       tisd_LOAD                 : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150484): (vcom-1287) VITAL timing generic "tisd_load" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150485):       tisd_REV                  : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150485): (vcom-1287) VITAL timing generic "tisd_rev" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150486):       tisd_SR                    : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150486): (vcom-1287) VITAL timing generic "tisd_sr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150487):       tisd_T1                   : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150487): (vcom-1287) VITAL timing generic "tisd_t1" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150488):       tisd_T2                   : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150488): (vcom-1287) VITAL timing generic "tisd_t2" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150489):       tisd_T3                   : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150489): (vcom-1287) VITAL timing generic "tisd_t3" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150490):       tisd_T4                   : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150490): (vcom-1287) VITAL timing generic "tisd_t4" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150491):       tisd_TCE                  : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150491): (vcom-1287) VITAL timing generic "tisd_tce" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150496):       tpw_CLK_posedge       : VitalDelayType := 0.0 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150496): (vcom-1288) VITAL timing generic "tpw_clk_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150502):       tperiod_CLK_posedge   : VitalDelayType := 0.0 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150502): (vcom-1288) VITAL timing generic "tperiod_clk_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150505):       trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.0 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150505): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150506):       trecovery_REV_CLK_negedge_posedge   : VitalDelayType := 0.0 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150506): (vcom-1288) VITAL timing generic "trecovery_rev_clk_negedge_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150507):       trecovery_SR_CLK_negedge_posedge   : VitalDelayType := 0.0 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150507): (vcom-1288) VITAL timing generic "trecovery_sr_clk_negedge_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150510):       tremoval_GSR_CLK_negedge_posedge  : VitalDelayType := 0.0 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150510): (vcom-1288) VITAL timing generic "tremoval_gsr_clk_negedge_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150511):       tremoval_REV_CLK_negedge_posedge    : VitalDelayType := 0.0 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150511): (vcom-1288) VITAL timing generic "tremoval_rev_clk_negedge_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150512):       tremoval_SR_CLK_negedge_posedge    : VitalDelayType := 0.0 ns
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(150512): (vcom-1288) VITAL timing generic "tremoval_sr_clk_negedge_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_iot_v of x_iot
-- Compiling entity x_oserdes
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151211):       tipd_GSR                      : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151211): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151245):       tpd_GSR_OQ            : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151245): (vcom-1288) VITAL timing generic "tpd_gsr_oq" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151246):       tpd_GSR_TQ            : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151246): (vcom-1288) VITAL timing generic "tpd_gsr_tq" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151258):       tisd_GSR                      : VitalDelayType := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151258): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151262):       tisd_SHIFTIN1         : VitalDelayType := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151262): (vcom-1287) VITAL timing generic "tisd_shiftin1" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151263):       tisd_SHIFTIN2         : VitalDelayType := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151263): (vcom-1287) VITAL timing generic "tisd_shiftin2" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151381):       tpw_GSR_posedge               : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151381): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151390):       trecovery_GSR_CLK_negedge_posedge             : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151390): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151391):       trecovery_GSR_CLKDIV_negedge_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151391): (vcom-1288) VITAL timing generic "trecovery_gsr_clkdiv_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151399):       tremoval_GSR_CLK_negedge_posedge              : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151399): (vcom-1288) VITAL timing generic "tremoval_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151400):       tremoval_GSR_CLKDIV_negedge_posedge   : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(151400): (vcom-1288) VITAL timing generic "tremoval_gsr_clkdiv_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_oserdes_v of x_oserdes
-- Compiling entity x_pmcd
-- Compiling architecture x_pmcd_v of x_pmcd
-- Compiling entity x_ramb16
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153370):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153370): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153374):     tpd_GSR_DOA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153374): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153375):     tpd_GSR_DOPA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153375): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153376):     tpd_GSR_CASCADEOUTA : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153376): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeouta" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153378):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153378): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153379):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153379): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153380):     tpd_GSR_CASCADEOUTB : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153380): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153394):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153394): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153395):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153395): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153455):     thold_GSR_CLKA_negedge_posedge    : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153455): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153473):     thold_GSR_CLKB_negedge_posedge    : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153473): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153483):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153483): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153484):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153484): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153485):     tbpd_GSR_CASCADEOUTA_CLKA : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153485): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeouta_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153493):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153493): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153498):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153498): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153499):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153499): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153500):     tbpd_GSR_CASCADEOUTB_CLKB : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153500): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153508):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153508): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153520):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(153520): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16_v of x_ramb16
-- Compiling entity x_iddr2
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155341):       tbpd_GSR_Q0_C0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155341): (vcom-1288) VITAL timing generic "tbpd_gsr_q0_c0" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155345):       tbpd_GSR_Q1_C1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155345): (vcom-1288) VITAL timing generic "tbpd_gsr_q1_c1" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155354):       tipd_GSR  : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155354): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155373):       tpd_GSR_Q0 : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155373): (vcom-1288) VITAL timing generic "tpd_gsr_q0" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155374):       tpd_GSR_Q1 : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155374): (vcom-1288) VITAL timing generic "tpd_gsr_q1" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155384):       tisd_GSR_C0 : VitalDelayType   := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155384): (vcom-1288) VITAL timing generic "tisd_gsr_c0" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155385):       tisd_GSR_C1 : VitalDelayType   := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155385): (vcom-1288) VITAL timing generic "tisd_gsr_c1" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155434):       tpw_GSR_posedge            : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155434): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155443):       trecovery_GSR_C0_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155443): (vcom-1288) VITAL timing generic "trecovery_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155446):       trecovery_GSR_C1_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155446): (vcom-1288) VITAL timing generic "trecovery_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155451):       tremoval_GSR_C0_negedge_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155451): (vcom-1288) VITAL timing generic "tremoval_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155454):       tremoval_GSR_C1_negedge_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(155454): (vcom-1288) VITAL timing generic "tremoval_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_iddr2_v of x_iddr2
-- Compiling entity x_mult18x18sio
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156221):     tipd_GSR        : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156221): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156233):     tpd_GSR_P       : VitalDelayArrayType01 (35 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156233): (vcom-1288) VITAL timing generic "tpd_gsr_p" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156247):         tisd_GSR_CLK        : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156247): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156314):     tpw_GSR_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156314): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156317):         trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0 ps
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(156317): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_mult18x18sio_v of x_mult18x18sio
-- Compiling entity x_oddr2
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160013):       tbpd_GSR_Q_C0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160013): (vcom-1288) VITAL timing generic "tbpd_gsr_q_c0" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160023):       tipd_GSR  : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160023): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160038):       tpd_GSR_Q : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160038): (vcom-1288) VITAL timing generic "tpd_gsr_q" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160050):       tisd_GSR_C0 : VitalDelayType   := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160050): (vcom-1288) VITAL timing generic "tisd_gsr_c0" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160051):       tisd_GSR_C1 : VitalDelayType   := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160051): (vcom-1288) VITAL timing generic "tisd_gsr_c1" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160109):       tpw_GSR_posedge            : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160109): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160118):       trecovery_GSR_C0_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160118): (vcom-1288) VITAL timing generic "trecovery_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160121):       trecovery_GSR_C1_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160121): (vcom-1288) VITAL timing generic "trecovery_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160126):       tremoval_GSR_C0_negedge_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160126): (vcom-1288) VITAL timing generic "tremoval_gsr_c0_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160129):       tremoval_GSR_C1_negedge_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(160129): (vcom-1288) VITAL timing generic "tremoval_gsr_c1_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_oddr2_v of x_oddr2
-- Compiling entity x_afifo36_internal
-- Compiling architecture x_afifo36_internal_v of x_afifo36_internal
-- Compiling entity x_aramb36_internal
-- Compiling architecture x_aramb36_internal_v of x_aramb36_internal
-- Compiling entity x_bscan_virtex5
-- Compiling architecture x_bscan_virtex5_v of x_bscan_virtex5
-- Compiling entity x_carry4
-- Compiling architecture x_carry4_v of x_carry4
-- Compiling entity x_crc32
-- Compiling architecture x_crc32_v of x_crc32
-- Compiling entity x_crc64
-- Compiling architecture x_crc64_v of x_crc64
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_signed
-- Loading package textio
-- Loading package vital_timing
-- Loading package vcomponents
-- Loading package vital_primitives
-- Loading package vpackage
-- Compiling entity x_dsp48e
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(173174):         tipd_GSR        : VitalDelayType01 := ( 0 ps,  0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(173174): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(173478):         tisd_GSR_CLK            : VitalDelayType  := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(173478): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(173499):         trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(173499): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_dsp48e_v of x_dsp48e
-- Compiling entity x_fifo18
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207047):     tipd_GSR   : VitalDelayType01                   := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207047): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207063):     tpd_GSR_DO            : VitalDelayArrayType01 (15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207063): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207064):     tpd_GSR_DOP           : VitalDelayArrayType01 (1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207064): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207065):     tpd_GSR_EMPTY         : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207065): (vcom-1288) VITAL timing generic "tpd_gsr_empty" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207066):     tpd_GSR_ALMOSTEMPTY   : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207066): (vcom-1288) VITAL timing generic "tpd_gsr_almostempty" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207067):     tpd_GSR_FULL          : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207067): (vcom-1288) VITAL timing generic "tpd_gsr_full" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207068):     tpd_GSR_ALMOSTFULL    : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207068): (vcom-1288) VITAL timing generic "tpd_gsr_almostfull" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207069):     tpd_GSR_RDCOUNT       : VitalDelayArrayType01 (11 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207069): (vcom-1288) VITAL timing generic "tpd_gsr_rdcount" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207070):     tpd_GSR_RDERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207070): (vcom-1288) VITAL timing generic "tpd_gsr_rderr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207071):     tpd_GSR_WRCOUNT       : VitalDelayArrayType01 (11 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207071): (vcom-1288) VITAL timing generic "tpd_gsr_wrcount" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207072):     tpd_GSR_WRERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207072): (vcom-1288) VITAL timing generic "tpd_gsr_wrerr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207093):     trecovery_GSR_WRCLK_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207093): (vcom-1288) VITAL timing generic "trecovery_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207094):     trecovery_GSR_RDCLK_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207094): (vcom-1288) VITAL timing generic "trecovery_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207101):     tremoval_GSR_WRCLK_negedge_posedge : VitalDelayType  := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207101): (vcom-1288) VITAL timing generic "tremoval_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207102):     tremoval_GSR_RDCLK_negedge_posedge : VitalDelayType  := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207102): (vcom-1288) VITAL timing generic "tremoval_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207133):     tisd_GSR_WRCLK   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(207133): (vcom-1288) VITAL timing generic "tisd_gsr_wrclk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_fifo18_v of x_fifo18
-- Compiling entity x_fifo18_36
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208761):     tipd_GSR   : VitalDelayType01                   := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208761): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208777):     tpd_GSR_DO            : VitalDelayArrayType01 (31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208777): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208778):     tpd_GSR_DOP           : VitalDelayArrayType01 (3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208778): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208779):     tpd_GSR_EMPTY         : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208779): (vcom-1288) VITAL timing generic "tpd_gsr_empty" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208780):     tpd_GSR_ALMOSTEMPTY   : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208780): (vcom-1288) VITAL timing generic "tpd_gsr_almostempty" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208781):     tpd_GSR_FULL          : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208781): (vcom-1288) VITAL timing generic "tpd_gsr_full" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208782):     tpd_GSR_ALMOSTFULL    : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208782): (vcom-1288) VITAL timing generic "tpd_gsr_almostfull" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208783):     tpd_GSR_RDCOUNT       : VitalDelayArrayType01 (8 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208783): (vcom-1288) VITAL timing generic "tpd_gsr_rdcount" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208784):     tpd_GSR_RDERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208784): (vcom-1288) VITAL timing generic "tpd_gsr_rderr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208785):     tpd_GSR_WRCOUNT       : VitalDelayArrayType01 (8 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208785): (vcom-1288) VITAL timing generic "tpd_gsr_wrcount" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208786):     tpd_GSR_WRERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208786): (vcom-1288) VITAL timing generic "tpd_gsr_wrerr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208807):     trecovery_GSR_WRCLK_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208807): (vcom-1288) VITAL timing generic "trecovery_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208808):     trecovery_GSR_RDCLK_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208808): (vcom-1288) VITAL timing generic "trecovery_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208815):     tremoval_GSR_WRCLK_negedge_posedge : VitalDelayType  := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208815): (vcom-1288) VITAL timing generic "tremoval_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208816):     tremoval_GSR_RDCLK_negedge_posedge : VitalDelayType  := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208816): (vcom-1288) VITAL timing generic "tremoval_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208847):     tisd_GSR_WRCLK   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(208847): (vcom-1288) VITAL timing generic "tisd_gsr_wrclk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_fifo18_36_v of x_fifo18_36
-- Compiling entity x_fifo36_72_exp
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211009):     tipd_GSR   : VitalDelayType01                   := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211009): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211038):     tpd_GSR_DO            : VitalDelayArrayType01 (63 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211038): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211039):     tpd_GSR_DOP           : VitalDelayArrayType01 (7 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211039): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211040):     tpd_GSR_EMPTY         : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211040): (vcom-1288) VITAL timing generic "tpd_gsr_empty" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211041):     tpd_GSR_ALMOSTEMPTY   : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211041): (vcom-1288) VITAL timing generic "tpd_gsr_almostempty" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211042):     tpd_GSR_FULL          : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211042): (vcom-1288) VITAL timing generic "tpd_gsr_full" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211043):     tpd_GSR_ALMOSTFULL    : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211043): (vcom-1288) VITAL timing generic "tpd_gsr_almostfull" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211044):     tpd_GSR_RDCOUNT       : VitalDelayArrayType01 (12 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211044): (vcom-1288) VITAL timing generic "tpd_gsr_rdcount" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211045):     tpd_GSR_RDERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211045): (vcom-1288) VITAL timing generic "tpd_gsr_rderr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211046):     tpd_GSR_WRCOUNT       : VitalDelayArrayType01 (12 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211046): (vcom-1288) VITAL timing generic "tpd_gsr_wrcount" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211047):     tpd_GSR_WRERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211047): (vcom-1288) VITAL timing generic "tpd_gsr_wrerr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211048):     tpd_GSR_ECCPARITY : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211048): (vcom-1288) VITAL timing generic "tpd_gsr_eccparity" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211049):     tpd_GSR_DBITERR  : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211049): (vcom-1288) VITAL timing generic "tpd_gsr_dbiterr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211050):     tpd_GSR_SBITERR  : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211050): (vcom-1288) VITAL timing generic "tpd_gsr_sbiterr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211071):     trecovery_GSR_WRCLKL_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211071): (vcom-1288) VITAL timing generic "trecovery_gsr_wrclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211072):     trecovery_GSR_RDCLKL_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211072): (vcom-1288) VITAL timing generic "trecovery_gsr_rdclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211073):     trecovery_GSR_RDRCLKL_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211073): (vcom-1288) VITAL timing generic "trecovery_gsr_rdrclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211081):     tremoval_GSR_WRCLKL_negedge_posedge : VitalDelayType  := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211081): (vcom-1288) VITAL timing generic "tremoval_gsr_wrclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211082):     tremoval_GSR_RDCLKL_negedge_posedge : VitalDelayType  := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211082): (vcom-1288) VITAL timing generic "tremoval_gsr_rdclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211083):     tremoval_GSR_RDRCLKL_negedge_posedge : VitalDelayType  := 0 ps;    
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211083): (vcom-1288) VITAL timing generic "tremoval_gsr_rdrclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211119):     tisd_GSR_WRCLKL   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(211119): (vcom-1288) VITAL timing generic "tisd_gsr_wrclkl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_fifo36_72_exp_v of x_fifo36_72_exp
-- Compiling entity x_fifo36_exp
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215121):     tipd_GSR   : VitalDelayType01                   := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215121): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215144):     tpd_GSR_DO            : VitalDelayArrayType01 (31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215144): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215145):     tpd_GSR_DOP           : VitalDelayArrayType01 (3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215145): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215146):     tpd_GSR_EMPTY         : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215146): (vcom-1288) VITAL timing generic "tpd_gsr_empty" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215147):     tpd_GSR_ALMOSTEMPTY   : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215147): (vcom-1288) VITAL timing generic "tpd_gsr_almostempty" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215148):     tpd_GSR_FULL          : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215148): (vcom-1288) VITAL timing generic "tpd_gsr_full" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215149):     tpd_GSR_ALMOSTFULL    : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215149): (vcom-1288) VITAL timing generic "tpd_gsr_almostfull" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215150):     tpd_GSR_RDCOUNT       : VitalDelayArrayType01 (12 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215150): (vcom-1288) VITAL timing generic "tpd_gsr_rdcount" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215151):     tpd_GSR_RDERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215151): (vcom-1288) VITAL timing generic "tpd_gsr_rderr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215152):     tpd_GSR_WRCOUNT       : VitalDelayArrayType01 (12 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215152): (vcom-1288) VITAL timing generic "tpd_gsr_wrcount" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215153):     tpd_GSR_WRERR         : VitalDelayType01                    := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215153): (vcom-1288) VITAL timing generic "tpd_gsr_wrerr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215174):     trecovery_GSR_WRCLKL_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215174): (vcom-1288) VITAL timing generic "trecovery_gsr_wrclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215175):     trecovery_GSR_RDCLKL_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215175): (vcom-1288) VITAL timing generic "trecovery_gsr_rdclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215176):     trecovery_GSR_RDRCLKL_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215176): (vcom-1288) VITAL timing generic "trecovery_gsr_rdrclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215184):     tremoval_GSR_WRCLKL_negedge_posedge : VitalDelayType  := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215184): (vcom-1288) VITAL timing generic "tremoval_gsr_wrclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215185):     tremoval_GSR_RDCLKL_negedge_posedge : VitalDelayType  := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215185): (vcom-1288) VITAL timing generic "tremoval_gsr_rdclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215186):     tremoval_GSR_RDRCLKL_negedge_posedge : VitalDelayType  := 0 ps;    
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215186): (vcom-1288) VITAL timing generic "tremoval_gsr_rdrclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215222):     tisd_GSR_WRCLKL   : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(215222): (vcom-1288) VITAL timing generic "tisd_gsr_wrclkl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_fifo36_exp_v of x_fifo36_exp
-- Compiling entity x_iddr_2clk
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217622):       tipd_GSR  : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217622): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217651):       tpd_GSR_Q1 : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217651): (vcom-1288) VITAL timing generic "tpd_gsr_q1" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217652):       tpd_GSR_Q2 : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217652): (vcom-1288) VITAL timing generic "tpd_gsr_q2" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217662):       tisd_GSR_C : VitalDelayType   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217662): (vcom-1288) VITAL timing generic "tisd_gsr_c" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217746):       tpw_GSR_posedge            : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217746): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217755):       trecovery_GSR_C_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217755): (vcom-1288) VITAL timing generic "trecovery_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217765):       trecovery_GSR_CB_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217765): (vcom-1288) VITAL timing generic "trecovery_gsr_cb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217776):       tremoval_GSR_C_negedge_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217776): (vcom-1288) VITAL timing generic "tremoval_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217786):       tremoval_GSR_CB_negedge_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(217786): (vcom-1288) VITAL timing generic "tremoval_gsr_cb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_iddr_2clk_v of x_iddr_2clk
-- Compiling entity x_iodelay
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218738):       tipd_GSR              : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218738): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218754):       tpd_GSR_DATAOUT : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218754): (vcom-1288) VITAL timing generic "tpd_gsr_dataout" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218761):       tisd_GSR_C : VitalDelayType := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218761): (vcom-1288) VITAL timing generic "tisd_gsr_c" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218788):       tpw_GSR_posedge             : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218788): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218794):       trecovery_GSR_C_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218794): (vcom-1288) VITAL timing generic "trecovery_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218797):       tremoval_GSR_C_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(218797): (vcom-1288) VITAL timing generic "tremoval_gsr_c_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_iodelay_v of x_iodelay
-- Compiling entity bscntrl
-- Compiling architecture bscntrl_v of bscntrl
-- Compiling entity ice_module
-- Compiling architecture ice_v of ice_module
-- Compiling entity x_iserdes_nodelay
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219830):       tipd_DIN              : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219830): (vcom-1288) VITAL timing generic "tipd_din" port specification "din" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219831):       tipd_GSR              : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219831): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219873):       tpd_GSR_Q1    : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219873): (vcom-1288) VITAL timing generic "tpd_gsr_q1" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219874):       tpd_GSR_Q2    : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219874): (vcom-1288) VITAL timing generic "tpd_gsr_q2" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219875):       tpd_GSR_Q3    : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219875): (vcom-1288) VITAL timing generic "tpd_gsr_q3" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219876):       tpd_GSR_Q4    : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219876): (vcom-1288) VITAL timing generic "tpd_gsr_q4" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219877):       tpd_GSR_Q5    : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219877): (vcom-1288) VITAL timing generic "tpd_gsr_q5" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219878):       tpd_GSR_Q6    : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219878): (vcom-1288) VITAL timing generic "tpd_gsr_q6" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219898):       tisd_GSR                      : VitalDelayType := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219898): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219905):       tisd_SHIFTIN1         : VitalDelayType := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219905): (vcom-1287) VITAL timing generic "tisd_shiftin1" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219906):       tisd_SHIFTIN2         : VitalDelayType := 0.0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(219906): (vcom-1287) VITAL timing generic "tisd_shiftin2" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(220020):       tpw_GSR_posedge       : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(220020): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(220027):       trecovery_GSR_CLK_negedge_posedge    : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(220027): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(220034):       tremoval_GSR_CLK_negedge_posedge    : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(220034): (vcom-1288) VITAL timing generic "tremoval_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_iserdes_nodelay_v of x_iserdes_nodelay
-- Compiling entity x_lut6_2
-- Compiling architecture x_lut6_2_v of x_lut6_2
-- Loading package numeric_std
-- Compiling entity x_pll_adv
-- Compiling architecture x_pll_adv_v of x_pll_adv
-- Compiling entity x_ram32m
-- Compiling architecture x_ram32m_v of x_ram32m
-- Compiling entity x_ram64m
-- Compiling architecture x_ram64m_v of x_ram64m
-- Compiling entity x_ramb18
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228301):     tipd_CASCADEINLATA  : VitalDelayType01               := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228301): (vcom-1288) VITAL timing generic "tipd_cascadeinlata" port specification "cascadeinlata" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228302):     tipd_CASCADEINREGA  : VitalDelayType01               := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228302): (vcom-1288) VITAL timing generic "tipd_cascadeinrega" port specification "cascadeinrega" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228312):     tipd_CASCADEINLATB  : VitalDelayType01               := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228312): (vcom-1288) VITAL timing generic "tipd_cascadeinlatb" port specification "cascadeinlatb" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228313):     tipd_CASCADEINREGB  : VitalDelayType01               := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228313): (vcom-1288) VITAL timing generic "tipd_cascadeinregb" port specification "cascadeinregb" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228315):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228315): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228319):     tpd_GSR_DOA  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228319): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228320):     tpd_GSR_DOPA : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228320): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228321):     tpd_GSR_CASCADEOUTLATA : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228321): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutlata" port specification "gsr" and "cascadeoutlata" do not denote ports.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228322):     tpd_GSR_CASCADEOUTREGA : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228322): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutrega" port specification "gsr" and "cascadeoutrega" do not denote ports.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228324):     tpd_GSR_DOB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228324): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228325):     tpd_GSR_DOPB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228325): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228326):     tpd_GSR_CASCADEOUTLATB : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228326): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutlatb" port specification "gsr" and "cascadeoutlatb" do not denote ports.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228327):     tpd_GSR_CASCADEOUTREGB : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228327): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutregb" port specification "gsr" and "cascadeoutregb" do not denote ports.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228331):     tpd_CLKA_CASCADEOUTLATA : VitalDelayType01            := (100 ps, 100 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228331): (vcom-1288) VITAL timing generic "tpd_clka_cascadeoutlata" port specification "cascadeoutlata" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228332):     tpd_CLKA_CASCADEOUTREGA : VitalDelayType01            := (100 ps, 100 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228332): (vcom-1288) VITAL timing generic "tpd_clka_cascadeoutrega" port specification "cascadeoutrega" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228336):     tpd_CLKB_CASCADEOUTLATB : VitalDelayType01            := (100 ps, 100 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228336): (vcom-1288) VITAL timing generic "tpd_clkb_cascadeoutlatb" port specification "cascadeoutlatb" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228337):     tpd_CLKB_CASCADEOUTREGB : VitalDelayType01            := (100 ps, 100 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228337): (vcom-1288) VITAL timing generic "tpd_clkb_cascadeoutregb" port specification "cascadeoutregb" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228341):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228341): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228342):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228342): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228390):     thold_GSR_CLKA_negedge_posedge    : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228390): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228408):     thold_GSR_CLKB_negedge_posedge    : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228408): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228418):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228418): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228419):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228419): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228420):     tbpd_GSR_CASCADEOUTLATA_CLKA : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228420): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutlata_clka" port specification "gsr" and "cascadeoutlata" do not denote ports.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228421):     tbpd_GSR_CASCADEOUTREGA_CLKA : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228421): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutrega_clka" port specification "gsr" and "cascadeoutrega" do not denote ports.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228428):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228428): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228431):     tisd_CASCADEINLATA_CLKA     : VitalDelayType               := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228431): (vcom-1288) VITAL timing generic "tisd_cascadeinlata_clka" port specification "cascadeinlata" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228432):     tisd_CASCADEINREGA_CLKA     : VitalDelayType               := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228432): (vcom-1288) VITAL timing generic "tisd_cascadeinrega_clka" port specification "cascadeinrega" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228435):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(15 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228435): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228436):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(1 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228436): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228437):     tbpd_GSR_CASCADEOUTLATB_CLKB : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228437): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutlatb_clkb" port specification "gsr" and "cascadeoutlatb" do not denote ports.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228438):     tbpd_GSR_CASCADEOUTREGB_CLKB : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228438): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutregb_clkb" port specification "gsr" and "cascadeoutregb" do not denote ports.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228445):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228445): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228448):     tisd_CASCADEINLATB_CLKB     : VitalDelayType               := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228448): (vcom-1288) VITAL timing generic "tisd_cascadeinlatb_clkb" port specification "cascadeinlatb" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228449):     tisd_CASCADEINREGB_CLKB     : VitalDelayType               := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(228449): (vcom-1288) VITAL timing generic "tisd_cascadeinregb_clkb" port specification "cascadeinregb" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb18_v of x_ramb18
-- Compiling entity x_ramb18sdp
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231455):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231455): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231459):     tpd_GSR_DO  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231459): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231460):     tpd_GSR_DOP : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231460): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231467):     trecovery_GSR_RDCLK_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231467): (vcom-1288) VITAL timing generic "trecovery_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231468):     trecovery_GSR_WRCLK_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231468): (vcom-1288) VITAL timing generic "trecovery_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231502):     thold_GSR_RDCLK_negedge_posedge    : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231502): (vcom-1288) VITAL timing generic "thold_gsr_rdclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231512):     thold_GSR_WRCLK_negedge_posedge    : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231512): (vcom-1288) VITAL timing generic "thold_gsr_wrclk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231516):     tbpd_GSR_DO_RDCLK  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231516): (vcom-1288) VITAL timing generic "tbpd_gsr_do_rdclk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231517):     tbpd_GSR_DOP_RDCLK : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231517): (vcom-1288) VITAL timing generic "tbpd_gsr_dop_rdclk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231524):     tisd_GSR_RDCLK      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231524): (vcom-1288) VITAL timing generic "tisd_gsr_rdclk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231531):     tisd_GSR_WRCLK      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(231531): (vcom-1288) VITAL timing generic "tisd_gsr_wrclk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb18sdp_v of x_ramb18sdp
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package vital_timing
-- Loading package vcomponents
-- Loading package vital_primitives
-- Loading package textio
-- Loading package vpackage
-- Compiling entity x_ramb36_exp
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234218):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234218): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234222):     tpd_GSR_DOA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234222): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234223):     tpd_GSR_DOPA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234223): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234224):     tpd_GSR_CASCADEOUTLATA : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234224): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutlata" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234225):     tpd_GSR_CASCADEOUTREGA : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234225): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutrega" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234229):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234229): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234230):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234230): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234231):     tpd_GSR_CASCADEOUTLATB : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234231): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutlatb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234232):     tpd_GSR_CASCADEOUTREGB : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234232): (vcom-1288) VITAL timing generic "tpd_gsr_cascadeoutregb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234252):     trecovery_GSR_CLKAL_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234252): (vcom-1288) VITAL timing generic "trecovery_gsr_clkal_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234253):     trecovery_GSR_CLKBL_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234253): (vcom-1288) VITAL timing generic "trecovery_gsr_clkbl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234313):     thold_GSR_CLKAL_negedge_posedge    : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234313): (vcom-1288) VITAL timing generic "thold_gsr_clkal_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234337):     thold_GSR_CLKBL_negedge_posedge    : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234337): (vcom-1288) VITAL timing generic "thold_gsr_clkbl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234353):     tbpd_GSR_DOA_CLKAL  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234353): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clkal" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234354):     tbpd_GSR_DOPA_CLKAL : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234354): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clkal" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234355):     tbpd_GSR_CASCADEOUTLATA_CLKAL : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234355): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutlata_clkal" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234356):     tbpd_GSR_CASCADEOUTREGA_CLKAL : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234356): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutrega_clkal" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234364):     tisd_GSR_CLKAL      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234364): (vcom-1288) VITAL timing generic "tisd_gsr_clkal" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234365):     tisd_GSR_REGCLKAL      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234365): (vcom-1288) VITAL timing generic "tisd_gsr_regclkal" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234374):     tbpd_GSR_DOB_CLKBL  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234374): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkbl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234375):     tbpd_GSR_DOPB_CLKBL : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234375): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkbl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234376):     tbpd_GSR_CASCADEOUTLATB_CLKBL : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234376): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutlatb_clkbl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234377):     tbpd_GSR_CASCADEOUTREGB_CLKBL : VitalDelayType01            := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234377): (vcom-1288) VITAL timing generic "tbpd_gsr_cascadeoutregb_clkbl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234385):     tisd_GSR_CLKBL      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234385): (vcom-1288) VITAL timing generic "tisd_gsr_clkbl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234386):     tisd_GSR_REGCLKBL      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(234386): (vcom-1288) VITAL timing generic "tisd_gsr_regclkbl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb36_exp_v of x_ramb36_exp
-- Compiling entity x_ramb36sdp_exp
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239516):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239516): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239520):     tpd_GSR_DO  : VitalDelayArrayType01(63 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239520): (vcom-1288) VITAL timing generic "tpd_gsr_do" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239521):     tpd_GSR_DOP : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239521): (vcom-1288) VITAL timing generic "tpd_gsr_dop" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239522):     tpd_GSR_ECCPARITY : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239522): (vcom-1288) VITAL timing generic "tpd_gsr_eccparity" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239523):     tbpd_GSR_ECCPARITY_RDCLKL : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239523): (vcom-1288) VITAL timing generic "tbpd_gsr_eccparity_rdclkl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239524):     tpd_GSR_DBITERR  : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239524): (vcom-1288) VITAL timing generic "tpd_gsr_dbiterr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239525):     tbpd_GSR_DBITERR_RDCLKL  : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239525): (vcom-1288) VITAL timing generic "tbpd_gsr_dbiterr_rdclkl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239526):     tpd_GSR_SBITERR  : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239526): (vcom-1288) VITAL timing generic "tpd_gsr_sbiterr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239527):     tbpd_GSR_SBITERR_RDCLKL  : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239527): (vcom-1288) VITAL timing generic "tbpd_gsr_sbiterr_rdclkl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239542):     trecovery_GSR_RDCLKL_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239542): (vcom-1288) VITAL timing generic "trecovery_gsr_rdclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239543):     trecovery_GSR_WRCLKL_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239543): (vcom-1288) VITAL timing generic "trecovery_gsr_wrclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239581):     thold_GSR_RDCLKL_negedge_posedge    : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239581): (vcom-1288) VITAL timing generic "thold_gsr_rdclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239595):     thold_GSR_WRCLKL_negedge_posedge    : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239595): (vcom-1288) VITAL timing generic "thold_gsr_wrclkl_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239599):     tbpd_GSR_DO_RDCLKL  : VitalDelayArrayType01(63 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239599): (vcom-1288) VITAL timing generic "tbpd_gsr_do_rdclkl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239600):     tbpd_GSR_DOP_RDCLKL : VitalDelayArrayType01(7 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239600): (vcom-1288) VITAL timing generic "tbpd_gsr_dop_rdclkl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239608):     tisd_GSR_RDCLKL      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239608): (vcom-1288) VITAL timing generic "tisd_gsr_rdclkl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239609):     tisd_GSR_RDRCLKL      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239609): (vcom-1288) VITAL timing generic "tisd_gsr_rdrclkl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239618):     tisd_GSR_WRCLKL      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(239618): (vcom-1288) VITAL timing generic "tisd_gsr_wrclkl" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb36sdp_exp_v of x_ramb36sdp_exp
-- Compiling entity x_ramd128
-- Compiling architecture x_ramd128_v of x_ramd128
-- Compiling entity x_ramd64_adv
-- Compiling architecture x_ramd64_adv_v of x_ramd64_adv
-- Compiling entity x_rams256
-- Compiling architecture x_rams256_v of x_rams256
-- Compiling entity x_rams64_adv
-- Compiling architecture x_rams64_adv_v of x_rams64_adv
-- Compiling entity x_srlc32e
-- Compiling architecture x_srlc32e_v of x_srlc32e
-- Loading package std_logic_arith
-- Loading package std_logic_signed
-- Loading package numeric_std
-- Compiling entity x_sysmon
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246421):         tisd_DI : VitalDelayArrayType(15 downto 0) := (others => 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246421): (vcom-1287) VITAL timing generic "tisd_di" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246422):         tisd_DADDR : VitalDelayArrayType(6 downto 0) := (others => 0.000 ns);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246422): (vcom-1287) VITAL timing generic "tisd_daddr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246423):         tisd_DEN : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246423): (vcom-1287) VITAL timing generic "tisd_den" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246424):         tisd_DWE : VitalDelayType := 0.000 ns;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(246424): (vcom-1287) VITAL timing generic "tisd_dwe" has invalid port specification.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_sysmon_v of x_sysmon
-- Compiling entity x_bscan_spartan3a
-- Compiling architecture x_bscan_spartan3a_v of x_bscan_spartan3a
-- Compiling entity x_dna_port
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(249867):       tipd_GSR : VitalDelayType01 := (0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(249867): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(249877):       tisd_GSR_CLK   : VitalDelayType   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(249877): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_dna_port_v of x_dna_port
-- Compiling entity x_ibuf_dly_adj
-- Compiling architecture x_ibuf_dly_adj_v of x_ibuf_dly_adj
-- Compiling entity x_ibufds_dly_adj
-- Compiling architecture x_ibufds_dly_adj_v of x_ibufds_dly_adj
-- Compiling entity x_ramb16bwe
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250790):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250790): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250794):     tpd_GSR_DOA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250794): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250795):     tpd_GSR_DOPA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250795): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250797):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250797): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250798):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250798): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250808):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250808): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250809):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250809): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250849):     thold_GSR_CLKA_negedge_posedge    : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250849): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250863):     thold_GSR_CLKB_negedge_posedge    : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250863): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250869):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250869): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250870):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250870): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250877):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250877): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250881):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250881): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250882):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250882): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250889):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250889): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250900):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(250900): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16bwe_v of x_ramb16bwe
-- Loading package std_logic_textio
-- Loading package std_logic_unsigned
-- Compiling entity dataflash
-- Compiling architecture design of dataflash
-- Compiling entity x_spi_access
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(262963):         tipd_GSR        : VitalDelayType01 := ( 0 ps,  0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(262963): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(262971):         tisd_GSR_CLK    : VitalDelayType   := 0 ps; 
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(262971): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_spi_access_v of x_spi_access
-- Compiling entity x_dsp48a
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(263352):         tipd_GSR        : VitalDelayType01 := ( 0 ps,  0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(263352): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(263582):         tisd_GSR_CLK            : VitalDelayType  := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(263582): (vcom-1288) VITAL timing generic "tisd_gsr_clk" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(263602):         trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(263602): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_dsp48a_v of x_dsp48a
-- Compiling entity x_ramb16bwer
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285454):     tipd_GSR : VitalDelayType01 := ( 0 ps, 0 ps);
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285454): (vcom-1288) VITAL timing generic "tipd_gsr" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285465):     tpd_GSR_DOA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285465): (vcom-1288) VITAL timing generic "tpd_gsr_doa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285466):     tpd_GSR_DOPA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285466): (vcom-1288) VITAL timing generic "tpd_gsr_dopa" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285468):     tpd_GSR_DOB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285468): (vcom-1288) VITAL timing generic "tpd_gsr_dob" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285469):     tpd_GSR_DOPB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285469): (vcom-1288) VITAL timing generic "tpd_gsr_dopb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285479):     trecovery_GSR_CLKA_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285479): (vcom-1288) VITAL timing generic "trecovery_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285480):     trecovery_GSR_CLKB_negedge_posedge : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285480): (vcom-1288) VITAL timing generic "trecovery_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285530):     thold_GSR_CLKA_negedge_posedge    : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285530): (vcom-1288) VITAL timing generic "thold_gsr_clka_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285546):     thold_GSR_CLKB_negedge_posedge    : VitalDelayType                   := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285546): (vcom-1288) VITAL timing generic "thold_gsr_clkb_negedge_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285554):     tbpd_GSR_DOA_CLKA  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285554): (vcom-1288) VITAL timing generic "tbpd_gsr_doa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285555):     tbpd_GSR_DOPA_CLKA : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285555): (vcom-1288) VITAL timing generic "tbpd_gsr_dopa_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285562):     tisd_GSR_CLKA      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285562): (vcom-1288) VITAL timing generic "tisd_gsr_clka" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285567):     tbpd_GSR_DOB_CLKB  : VitalDelayArrayType01(31 downto 0) := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285567): (vcom-1288) VITAL timing generic "tbpd_gsr_dob_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285568):     tbpd_GSR_DOPB_CLKB : VitalDelayArrayType01(3 downto 0)  := (others => (0 ps, 0 ps));
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285568): (vcom-1288) VITAL timing generic "tbpd_gsr_dopb_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285575):     tisd_GSR_CLKB      : VitalDelayType                     := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285575): (vcom-1288) VITAL timing generic "tisd_gsr_clkb" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285587):     tpw_GSR_posedge  : VitalDelayType := 0 ps;
** Warning: [6] /opt/xilinx/ise_91i/vhdl/src/simprims/simprim_VITAL_mti.vhd(285587): (vcom-1288) VITAL timing generic "tpw_gsr_posedge" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ramb16bwer_v of x_ramb16bwer

END_COMPILE:simprim

==============================================================================

    > Log file /home/habea2/Geccko3com/gecko3com_v04/lib/simprim/cxl_simprim.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[simprim]: No error(s), 986 warning(s)

--> Compiling vhdl XilinxCoreLib library
    > XilinxCoreLib compiled to /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib

==============================================================================
START_COMPILE XilinxCoreLib


Modifying modelsim.ini

Modifying modelsim.ini

Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
-- Loading package standard
-- Loading package textio
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling entity blk_mem_gen_v2_2_output_stage
-- Compiling architecture behavioral of blk_mem_gen_v2_2_output_stage
-- Compiling entity blk_mem_gen_v2_2
-- Compiling architecture behavioral of blk_mem_gen_v2_2
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(417):       file_open(init_file, C_INIT_FILE_NAME, read_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(417): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(419):       while (i < depth and not endfile(init_file)) loop
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(419): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(421):         readline(init_file, file_buffer);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(421): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(431):       file_close(init_file);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(431): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
-- Loading package std_logic_textio
-- Compiling package blk_mem_gen_v2_2_comp
-- Loading package blk_mem_gen_v2_2_comp
-- Compiling entity blk_mem_gen_v2_2_xst
-- Compiling architecture behavioral of blk_mem_gen_v2_2_xst
-- Compiling package blk_mem_gen_v2_2_xst_comp
-- Loading package numeric_std
-- Compiling entity dist_mem_gen_v3_1
-- Compiling architecture behavioral of dist_mem_gen_v3_1
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2218):       file_open(mif_status, meminitfile, filename, read_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2218): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2230):          if not(endfile(meminitfile)) and i < depth then
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2230): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2233):             readline(meminitfile, bitline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2233): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2264):       file_close(meminitfile);      
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2264): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2352):          memory_content := read_mif(filename, def_data, depth, width);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(2352): (vcom-1284) Cannot call side-effect function "read_mif" from pure function "init_mem".
-- Compiling package dist_mem_gen_v3_1_comp
-- Loading package dist_mem_gen_v3_1_comp
-- Compiling entity dist_mem_gen_v3_1_xst
-- Compiling architecture behavioral of dist_mem_gen_v3_1_xst
-- Compiling package dist_mem_gen_v3_1_xst_comp
-- Compiling package prims_constants_v8_0
-- Loading package prims_constants_v8_0
-- Compiling package prims_utils_v8_0
-- Compiling package body prims_utils_v8_0
-- Loading package prims_utils_v8_0
-- Compiling package pkg_baseblox_v8_0
-- Compiling package body pkg_baseblox_v8_0
-- Loading package pkg_baseblox_v8_0
-- Loading package prims_utils_v8_0
-- Loading package pkg_baseblox_v8_0
-- Compiling entity c_lut_v8_0
-- Compiling architecture behavioral of c_lut_v8_0
-- Compiling package c_lut_v8_0_comp
-- Loading package c_lut_v8_0_comp
-- Compiling entity c_lut_v8_0_xst
-- Compiling architecture behavioural of c_lut_v8_0_xst
-- Compiling package c_lut_v8_0_xst_comp
-- Compiling package floating_point_v3_0_consts
-- Loading package floating_point_v3_0_consts
-- Compiling package floating_point_pkg_v3_0
-- Compiling package body floating_point_pkg_v3_0
-- Loading package floating_point_pkg_v3_0
-- Loading package floating_point_pkg_v3_0
-- Compiling entity flt_pt_operator_v3_0
-- Compiling architecture behavioral of flt_pt_operator_v3_0
-- Compiling entity floating_point_v3_0_xst
-- Compiling architecture behavioral of floating_point_v3_0_xst
-- Compiling package floating_point_v3_0_xst_comp
-- Loading package floating_point_v3_0_xst_comp
-- Compiling entity floating_point_v3_0
-- Compiling architecture behavioral of floating_point_v3_0
-- Compiling package floating_point_v3_0_comp
-- Compiling package prims_constants_v9_1
-- Loading package prims_constants_v9_1
-- Compiling package prims_utils_v9_1
-- Compiling package body prims_utils_v9_1
-- Loading package prims_utils_v9_1
-- Compiling package pkg_baseblox_v9_1
-- Compiling package body pkg_baseblox_v9_1
-- Loading package pkg_baseblox_v9_1
-- Loading package prims_utils_v9_1
-- Loading package pkg_baseblox_v9_1
-- Compiling entity c_reg_fd_v9_1
-- Compiling architecture behavioral of c_reg_fd_v9_1
-- Compiling package c_reg_fd_v9_1_comp
-- Loading package c_reg_fd_v9_1_comp
-- Compiling entity c_addsub_v9_1
-- Compiling architecture behavioral of c_addsub_v9_1
-- Compiling package c_addsub_v9_1_comp
-- Compiling entity c_compare_v9_1
-- Compiling architecture behavioral of c_compare_v9_1
-- Compiling package c_compare_v9_1_comp
-- Compiling entity c_mux_bus_v9_1
-- Compiling architecture behavioral of c_mux_bus_v9_1
-- Compiling package c_mux_bus_v9_1_comp
-- Loading package c_addsub_v9_1_comp
-- Loading package c_compare_v9_1_comp
-- Loading package c_mux_bus_v9_1_comp
-- Compiling entity c_counter_binary_v9_1
-- Compiling architecture behavioral of c_counter_binary_v9_1
-- Compiling package c_counter_binary_v9_1_comp
-- Loading package c_counter_binary_v9_1_comp
-- Compiling entity c_counter_binary_v9_1_xst
-- Compiling architecture behavioral of c_counter_binary_v9_1_xst
-- Compiling package c_counter_binary_v9_1_xst_comp
-- Compiling package prims_constants_v9_0
-- Loading package prims_constants_v9_0
-- Compiling package prims_utils_v9_0
-- Compiling package body prims_utils_v9_0
-- Loading package prims_utils_v9_0
-- Compiling package pkg_baseblox_v9_0
-- Compiling package body pkg_baseblox_v9_0
-- Loading package pkg_baseblox_v9_0
-- Loading package prims_utils_v9_0
-- Loading package pkg_baseblox_v9_0
-- Compiling package pkg_mult_gen_v9_0
-- Compiling package body pkg_mult_gen_v9_0
-- Loading package pkg_mult_gen_v9_0
-- Loading package std_logic_signed
-- Loading package pkg_mult_gen_v9_0
-- Compiling entity mult_gen_v9_0
-- Compiling architecture behavioral of mult_gen_v9_0
-- Compiling package mult_gen_v9_0_comp
-- Loading package mult_gen_v9_0_comp
-- Compiling entity mult_gen_v9_0_xst
-- Compiling architecture behavioral of mult_gen_v9_0_xst
-- Compiling package mult_gen_v9_0_xst_comp
-- Compiling entity sdivider_v4_0
-- Compiling architecture behavioral of sdivider_v4_0
-- Compiling package sdivider_v4_0_comp
-- Loading package sdivider_v4_0_comp
-- Compiling entity sdivider_v4_0_xst
-- Compiling architecture behavioral of sdivider_v4_0_xst
-- Compiling package sdivider_v4_0_xst_comp
-- Compiling package pkg_sdivider_v4_0
-- Compiling package body pkg_sdivider_v4_0
-- Loading package pkg_sdivider_v4_0
-- Compiling package prims_constants_v6_0
-- Compiling package prims_utils_v6_0
-- Loading package prims_constants_v6_0
-- Compiling package body prims_utils_v6_0
-- Loading package prims_utils_v6_0
-- Loading package prims_utils_v6_0
-- Compiling entity pipeline_v6_0
-- Compiling architecture behavioral of pipeline_v6_0
-- Compiling entity c_reg_fd_v6_0
-- Compiling architecture behavioral of c_reg_fd_v6_0
-- Compiling package c_reg_fd_v6_0_comp
-- Loading package c_reg_fd_v6_0_comp
-- Compiling entity c_decode_binary_v6_0
-- Compiling architecture behavioral of c_decode_binary_v6_0
-- Compiling package c_decode_binary_v6_0_comp
-- Compiling package prims_comps_v6_0
-- Loading package prims_comps_v6_0
-- Compiling entity c_buft_v6_0
-- Compiling architecture buft_beh of c_buft_v6_0
-- Compiling configuration cfg_buft_beh
-- Loading entity c_buft_v6_0
-- Loading architecture buft_beh of c_buft_v6_0
-- Compiling entity c_pullup_v6_0
-- Compiling architecture pullup_beh of c_pullup_v6_0
-- Compiling configuration cfg_pullup_beh
-- Loading entity c_pullup_v6_0
-- Loading architecture pullup_beh of c_pullup_v6_0
-- Compiling entity c_lut_v6_0
-- Compiling architecture lut_beh of c_lut_v6_0
-- Compiling configuration cfg_lut_beh
-- Loading entity c_lut_v6_0
-- Loading architecture lut_beh of c_lut_v6_0
-- Compiling entity c_mux_slice_bufe_v6_0
-- Compiling architecture behavioral of c_mux_slice_bufe_v6_0
-- Compiling package c_mux_slice_bufe_v6_0_comp
-- Compiling entity c_reg_ld_v6_0
-- Compiling architecture behavioral of c_reg_ld_v6_0
-- Compiling package c_reg_ld_v6_0_comp
-- Compiling package baseblox_v6_0_services
-- Compiling package body baseblox_v6_0_services
-- Loading package baseblox_v6_0_services
-- Compiling entity c_mux_slice_buft_v6_0
-- Compiling architecture behavioral of c_mux_slice_buft_v6_0
-- Compiling package c_mux_slice_buft_v6_0_comp
-- Compiling entity c_addsub_v6_0
-- Compiling architecture behavioral of c_addsub_v6_0
-- Compiling package c_addsub_v6_0_comp
-- Compiling entity c_compare_v6_0
-- Compiling architecture behavioral of c_compare_v6_0
-- Compiling package c_compare_v6_0_comp
-- Compiling entity c_mux_bus_v6_0
-- Compiling architecture behavioral of c_mux_bus_v6_0
-- Compiling package c_mux_bus_v6_0_comp
-- Compiling entity c_gate_bit_v6_0
-- Compiling architecture behavioral of c_gate_bit_v6_0
-- Compiling package c_gate_bit_v6_0_comp
-- Loading package c_addsub_v6_0_comp
-- Loading package c_compare_v6_0_comp
-- Loading package c_mux_bus_v6_0_comp
-- Loading package c_gate_bit_v6_0_comp
-- Compiling entity c_counter_binary_v6_0
-- Compiling architecture behavioral of c_counter_binary_v6_0
-- Compiling package c_counter_binary_v6_0_comp
-- Compiling entity c_reg_fd_v8_0
-- Compiling architecture behavioral of c_reg_fd_v8_0
-- Compiling package c_reg_fd_v8_0_comp
-- Loading package c_reg_fd_v8_0_comp
-- Compiling entity c_reg_fd_v8_0_xst
-- Compiling architecture behavioral of c_reg_fd_v8_0_xst
-- Compiling package c_reg_fd_v8_0_xst_comp
-- Compiling entity c_reg_fd_v9_0
-- Compiling architecture behavioral of c_reg_fd_v9_0
-- Compiling package c_reg_fd_v9_0_comp
-- Loading package c_reg_fd_v9_0_comp
-- Compiling entity c_twos_comp_v9_0
-- Compiling architecture behavioral of c_twos_comp_v9_0
-- Compiling package c_twos_comp_v9_0_comp
-- Loading package c_twos_comp_v9_0_comp
-- Compiling entity c_twos_comp_v9_0_xst
-- Compiling architecture behavioral of c_twos_comp_v9_0_xst
-- Compiling package c_twos_comp_v9_0_xst_comp
-- Compiling entity async_fifo_v6_1
-- Compiling architecture behavioral of async_fifo_v6_1
-- Compiling package async_fifo_v6_1_comp
-- Compiling package prims_constants_v7_0
-- Compiling package family
-- Compiling package body family
-- Loading package family
-- Loading package prims_constants_v7_0
-- Loading package family
-- Compiling package c_dist_mem_v7_0_services
-- Compiling package body c_dist_mem_v7_0_services
-- Loading package c_dist_mem_v7_0_services
-- Compiling entity blk_mem_gen_v2_3_output_stage
-- Compiling architecture behavioral of blk_mem_gen_v2_3_output_stage
-- Compiling entity blk_mem_gen_v2_3
-- Compiling architecture behavioral of blk_mem_gen_v2_3
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33647):       file_open(init_file, C_INIT_FILE_NAME, read_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33647): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33649):       while (i < depth and not endfile(init_file)) loop
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33649): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33651):         readline(init_file, file_buffer);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33651): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33661):       file_close(init_file);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(33661): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
-- Compiling package blk_mem_gen_v2_3_comp
-- Loading package blk_mem_gen_v2_3_comp
-- Compiling entity blk_mem_gen_v2_3_xst
-- Compiling architecture behavioral of blk_mem_gen_v2_3_xst
-- Compiling package blk_mem_gen_v2_3_xst_comp
-- Compiling package blkmemdp_v6_0_services
-- Compiling package body blkmemdp_v6_0_services
-- Loading package blkmemdp_v6_0_services
-- Compiling entity c_addsub_v9_0
-- Compiling architecture behavioral of c_addsub_v9_0
-- Compiling package c_addsub_v9_0_comp
-- Loading package c_addsub_v9_0_comp
-- Compiling entity c_accum_v9_0
-- Compiling architecture behavioral of c_accum_v9_0
-- Compiling package c_accum_v9_0_comp
-- Loading package c_accum_v9_0_comp
-- Compiling entity c_accum_v9_0_xst
-- Compiling architecture behavioral of c_accum_v9_0_xst
-- Compiling package c_accum_v9_0_xst_comp
-- Compiling entity c_mux_bit_v8_0
-- Compiling architecture behavioral of c_mux_bit_v8_0
-- Compiling package c_mux_bit_v8_0_comp
-- Loading package c_mux_bit_v8_0_comp
-- Compiling entity c_shift_fd_v8_0
-- Compiling architecture behavioral of c_shift_fd_v8_0
-- Compiling package c_shift_fd_v8_0_comp
-- Loading package c_shift_fd_v8_0_comp
-- Compiling entity c_shift_fd_v8_0_xst
-- Compiling architecture behavioral of c_shift_fd_v8_0_xst
-- Compiling package c_shift_fd_v8_0_xst_comp
-- Compiling entity c_addsub_v8_0
-- Compiling architecture behavioral of c_addsub_v8_0
-- Compiling package c_addsub_v8_0_comp
-- Compiling entity c_compare_v8_0
-- Compiling architecture behavioral of c_compare_v8_0
-- Compiling package c_compare_v8_0_comp
-- Compiling entity c_mux_bus_v8_0
-- Compiling architecture behavioral of c_mux_bus_v8_0
-- Compiling package c_mux_bus_v8_0_comp
-- Loading package c_addsub_v8_0_comp
-- Loading package c_compare_v8_0_comp
-- Loading package c_mux_bus_v8_0_comp
-- Compiling entity c_counter_binary_v8_0
-- Compiling architecture behavioral of c_counter_binary_v8_0
-- Compiling package c_counter_binary_v8_0_comp
-- Loading package c_counter_binary_v8_0_comp
-- Compiling entity c_counter_binary_v8_0_xst
-- Compiling architecture behavioral of c_counter_binary_v8_0_xst
-- Compiling package c_counter_binary_v8_0_xst_comp
-- Compiling entity c_twos_comp_v9_1
-- Compiling architecture behavioral of c_twos_comp_v9_1
-- Compiling package c_twos_comp_v9_1_comp
-- Loading package c_twos_comp_v9_1_comp
-- Compiling entity c_twos_comp_v9_1_xst
-- Compiling architecture behavioral of c_twos_comp_v9_1_xst
-- Compiling package c_twos_comp_v9_1_xst_comp
-- Compiling package iputils_conv
-- Compiling package body iputils_conv
-- Loading package iputils_conv
-- Compiling package iputils_misc
-- Compiling package body iputils_misc
-- Loading package iputils_misc
-- Loading package iputils_conv
-- Loading package iputils_misc
-- Compiling entity fifo_generator_v2_0_bhv_as
-- Compiling architecture behavioral of fifo_generator_v2_0_bhv_as
-- Compiling entity fifo_generator_v2_0_bhv_ss
-- Compiling architecture behavioral of fifo_generator_v2_0_bhv_ss
-- Compiling entity fifo_generator_v2_0_bhv_fifo16
-- Compiling architecture behavioral of fifo_generator_v2_0_bhv_fifo16
-- Loading entity fifo_generator_v2_0_bhv_as
-- Loading entity fifo_generator_v2_0_bhv_ss
-- Compiling entity fifo_generator_v2_0
-- Compiling architecture behavioral of fifo_generator_v2_0
-- Compiling package fifo_generator_v2_0_comp
-- Compiling entity c_shift_ram_v8_0
-- Compiling architecture behavioral of c_shift_ram_v8_0
-- Compiling package c_shift_ram_v8_0_comp
-- Loading package c_shift_ram_v8_0_comp
-- Compiling entity c_shift_ram_v8_0_xst
-- Compiling architecture behavioral of c_shift_ram_v8_0_xst
-- Compiling package c_shift_ram_v8_0_xst_comp
-- Compiling package blkmemsp_pkg_v5_0
-- Compiling package body blkmemsp_pkg_v5_0
-- Loading package blkmemsp_pkg_v5_0
-- Compiling package ul_utils
-- Compiling package body ul_utils
-- Loading package ul_utils
-- Compiling package math_int
-- Compiling package body math_int
-- Loading package math_int
-- Loading package ul_utils
-- Compiling package mem_init_file_pack_v5_0
-- Compiling package body mem_init_file_pack_v5_0
-- Loading package mem_init_file_pack_v5_0
-- Loading package mem_init_file_pack_v5_0
-- Loading package blkmemsp_pkg_v5_0
-- Compiling entity blkmemsp_v5_0
-- Compiling architecture behavioral of blkmemsp_v5_0
-- Compiling package blkmemsp_v5_0_comp
-- Compiling package pkg_mult_gen_v10_0
-- Compiling package body pkg_mult_gen_v10_0
-- Loading package pkg_mult_gen_v10_0
-- Loading package pkg_mult_gen_v10_0
-- Compiling entity mult_gen_v10_0
-- Compiling architecture behavioral of mult_gen_v10_0
-- Compiling package mult_gen_v10_0_comp
-- Loading package mult_gen_v10_0_comp
-- Compiling entity mult_gen_v10_0_xst
-- Compiling architecture behavioral of mult_gen_v10_0_xst
-- Compiling package mult_gen_v10_0_xst_comp
-- Compiling package c_dist_mem_v6_0_services
-- Compiling package body c_dist_mem_v6_0_services
-- Loading package c_dist_mem_v6_0_services
-- Compiling package mult_gen_const_pkg_v8_0
-- Loading package mult_gen_const_pkg_v8_0
-- Compiling package parm_v8_0_services
-- Compiling package body parm_v8_0_services
-- Loading package parm_v8_0_services
-- Loading package parm_v8_0_services
-- Compiling package ccm_v8_0_services
-- Compiling package body ccm_v8_0_services
-- Loading package ccm_v8_0_services
-- Loading package ccm_v8_0_services
-- Compiling package mult_gen_v8_0_services
-- Compiling package body mult_gen_v8_0_services
-- Loading package mult_gen_v8_0_services
-- Loading package mult_gen_v8_0_services
-- Compiling package mult_pkg_v8_0
-- Compiling package body mult_pkg_v8_0
-- Loading package mult_pkg_v8_0
-- Loading package mult_pkg_v8_0
-- Compiling entity mult_gen_v8_0_non_seq
-- Compiling architecture behavioral of mult_gen_v8_0_non_seq
-- Compiling package mult_gen_v8_0_non_seq_comp
-- Compiling package iputils_family
-- Compiling package body iputils_family
-- Loading package iputils_family
-- Loading package mult_gen_v8_0_non_seq_comp
-- Loading package iputils_family
-- Compiling entity mult_gen_v8_0
-- Compiling architecture behavioral of mult_gen_v8_0
-- Compiling package mult_gen_v8_0_comp
-- Loading package mult_gen_v8_0_comp
-- Compiling entity mult_gen_v8_0_xst
-- Compiling architecture behavioral of mult_gen_v8_0_xst
-- Compiling package mult_gen_v8_0_xst_comp
-- Compiling package blkmemdp_v5_0_services
-- Compiling package body blkmemdp_v5_0_services
-- Loading package blkmemdp_v5_0_services
-- Compiling entity blk_mem_gen_v2_4_output_stage
-- Compiling architecture behavioral of blk_mem_gen_v2_4_output_stage
-- Compiling entity blk_mem_gen_v2_4
-- Compiling architecture behavioral of blk_mem_gen_v2_4
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68132):       file_open(init_file, C_INIT_FILE_NAME, read_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68132): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68134):       while (i < depth and not endfile(init_file)) loop
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68134): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68136):         readline(init_file, file_buffer);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68136): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68146):       file_close(init_file);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(68146): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
-- Compiling package blk_mem_gen_v2_4_comp
-- Loading package blk_mem_gen_v2_4_comp
-- Compiling entity blk_mem_gen_v2_4_xst
-- Compiling architecture behavioral of blk_mem_gen_v2_4_xst
-- Compiling package blk_mem_gen_v2_4_xst_comp
-- Compiling package iputils_math
-- Compiling package body iputils_math
-- Loading package iputils_math
-- Compiling package iputils_mem87
-- Compiling package body iputils_mem87
-- Loading package iputils_mem87
-- Compiling package iputils_slv
-- Loading package iputils_math
-- Compiling package body iputils_slv
-- Loading package iputils_slv
-- Compiling package cam_v5_0_pkg
-- Compiling package body cam_v5_0_pkg
-- Loading package cam_v5_0_pkg
-- Loading package cam_v5_0_pkg
-- Loading package iputils_mem87
-- Loading package iputils_slv
-- Compiling entity cam_v5_0
-- Compiling architecture behavioral of cam_v5_0
-- Compiling package cam_v5_0_comp
-- Compiling entity c_gate_bit_v9_0
-- Compiling architecture behavioral of c_gate_bit_v9_0
-- Compiling package c_gate_bit_v9_0_comp
-- Loading package c_gate_bit_v9_0_comp
-- Compiling entity c_gate_bit_v9_0_xst
-- Compiling architecture behavioral of c_gate_bit_v9_0_xst
-- Compiling package c_gate_bit_v9_0_xst_comp
-- Compiling package cam_v4_0_pkg
-- Compiling package body cam_v4_0_pkg
-- Loading package cam_v4_0_pkg
-- Loading package cam_v4_0_pkg
-- Compiling entity cam_v4_0
-- Compiling architecture behavioral of cam_v4_0
-- Compiling package cam_v4_0_comp
-- Compiling entity c_mux_bus_v8_0_xst
-- Compiling architecture behavioral of c_mux_bus_v8_0_xst
-- Compiling package c_mux_bus_v8_0_xst_comp
-- Compiling entity c_mux_bit_v8_0_xst
-- Compiling architecture behavioral of c_mux_bit_v8_0_xst
-- Compiling package c_mux_bit_v8_0_xst_comp
-- Compiling package iputils_std_logic_arith
-- Compiling package body iputils_std_logic_arith
-- Loading package iputils_std_logic_arith
-- Loading package iputils_std_logic_arith
-- Compiling package iputils_std_logic_unsigned
-- Compiling package body iputils_std_logic_unsigned
-- Loading package iputils_std_logic_unsigned
-- Loading package iputils_std_logic_unsigned
-- Compiling entity fifo_generator_v3_1_bhv_as
-- Compiling architecture behavioral of fifo_generator_v3_1_bhv_as
-- Compiling entity fifo_generator_v3_1_bhv_ss
-- Compiling architecture behavioral of fifo_generator_v3_1_bhv_ss
-- Compiling entity fifo_generator_v3_1_bhv_preload0
-- Compiling architecture behavioral of fifo_generator_v3_1_bhv_preload0
-- Loading entity fifo_generator_v3_1_bhv_as
-- Loading entity fifo_generator_v3_1_bhv_ss
-- Compiling entity fifo_generator_v3_1
-- Compiling architecture behavioral of fifo_generator_v3_1
-- Compiling package fifo_generator_v3_1_comp
-- Loading package fifo_generator_v3_1_comp
-- Compiling entity fifo_generator_v3_1_xst
-- Compiling architecture behavioral of fifo_generator_v3_1_xst
-- Compiling package fifo_generator_v3_1_xst_comp
-- Compiling entity c_compare_v9_0
-- Compiling architecture behavioral of c_compare_v9_0
-- Compiling package c_compare_v9_0_comp
-- Loading package c_compare_v9_0_comp
-- Compiling entity c_compare_v9_0_xst
-- Compiling architecture behavioral of c_compare_v9_0_xst
-- Compiling package c_compare_v9_0_xst_comp
-- Compiling package c_compare_v9_0_rtl_comp
-- Compiling package prims_constants_v5_0
-- Compiling package prims_utils_v5_0
-- Loading package prims_constants_v5_0
-- Compiling package body prims_utils_v5_0
-- Loading package prims_utils_v5_0
-- Loading package prims_utils_v5_0
-- Compiling entity pipeline_v5_0
-- Compiling architecture behavioral of pipeline_v5_0
-- Compiling entity c_reg_fd_v5_0
-- Compiling architecture behavioral of c_reg_fd_v5_0
-- Compiling package c_reg_fd_v5_0_comp
-- Loading package c_reg_fd_v5_0_comp
-- Compiling entity c_dist_mem_v5_1
-- Compiling architecture behavioral of c_dist_mem_v5_1
-- Compiling package c_dist_mem_v5_1_comp
-- Compiling package blkmemsp_pkg_v6_1
-- Compiling package body blkmemsp_pkg_v6_1
-- Loading package blkmemsp_pkg_v6_1
-- Compiling package mem_init_file_pack_v6_1
-- Compiling package body mem_init_file_pack_v6_1
-- Loading package mem_init_file_pack_v6_1
-- Loading package mem_init_file_pack_v6_1
-- Loading package blkmemsp_pkg_v6_1
-- Compiling entity blkmemsp_v6_1
-- Compiling architecture behavioral of blkmemsp_v6_1
-- Compiling package blkmemsp_v6_1_comp
-- Loading package blkmemsp_v6_1_comp
-- Compiling entity blkmemsp_v6_1_xst
-- Compiling architecture xilinx of blkmemsp_v6_1_xst
-- Compiling package blkmemsp_v6_1_xst_comp
-- Compiling entity c_shift_ram_v9_1
-- Compiling architecture behavioral of c_shift_ram_v9_1
-- Compiling package c_shift_ram_v9_1_comp
-- Loading package c_shift_ram_v9_1_comp
-- Compiling entity c_shift_ram_v9_1_xst
-- Compiling architecture behavioral of c_shift_ram_v9_1_xst
-- Compiling package c_shift_ram_v9_1_xst_comp
-- Compiling entity c_mux_slice_buft_v4_0
-- Compiling architecture behavioral of c_mux_slice_buft_v4_0
-- Compiling package c_mux_slice_buft_v4_0_comp
-- Compiling package prims_constants_v4_0
-- Compiling package prims_utils_v4_0
-- Loading package prims_constants_v4_0
-- Compiling package body prims_utils_v4_0
-- Loading package prims_utils_v4_0
-- Loading package prims_utils_v4_0
-- Compiling entity pipeline_v4_0
-- Compiling architecture behavioral of pipeline_v4_0
-- Compiling entity c_reg_fd_v4_0
-- Compiling architecture behavioral of c_reg_fd_v4_0
-- Compiling package c_reg_fd_v4_0_comp
-- Loading package c_reg_fd_v4_0_comp
-- Compiling entity c_gate_bit_bus_v4_0
-- Compiling architecture behavioral of c_gate_bit_bus_v4_0
-- Compiling package c_gate_bit_bus_v4_0_comp
-- Compiling entity c_reg_ld_v4_0
-- Compiling architecture behavioral of c_reg_ld_v4_0
-- Compiling package c_reg_ld_v4_0_comp
-- Compiling package prims_comps_v4_0
-- Loading package prims_comps_v4_0
-- Compiling entity c_lut_v4_0
-- Compiling architecture behavioral of c_lut_v4_0
-- Compiling configuration cfg_lut
-- Loading entity c_lut_v4_0
-- Loading architecture behavioral of c_lut_v4_0
-- Compiling entity c_mux_bit_v4_0
-- Compiling architecture behavioral of c_mux_bit_v4_0
-- Compiling package c_mux_bit_v4_0_comp
-- Loading package c_mux_bit_v4_0_comp
-- Compiling entity c_shift_fd_v4_0
-- Compiling architecture behavioral of c_shift_fd_v4_0
-- Compiling package c_shift_fd_v4_0_comp
-- Compiling entity c_addsub_v4_0
-- Compiling architecture behavioral of c_addsub_v4_0
-- Compiling package c_addsub_v4_0_comp
-- Loading package c_addsub_v4_0_comp
-- Compiling entity c_accum_v4_0
-- Compiling architecture behavioral of c_accum_v4_0
-- Compiling package c_accum_v4_0_comp
-- Compiling entity c_decode_binary_v4_0
-- Compiling architecture behavioral of c_decode_binary_v4_0
-- Compiling package c_decode_binary_v4_0_comp
-- Compiling entity c_mux_slice_bufe_v4_0
-- Compiling architecture behavioral of c_mux_slice_bufe_v4_0
-- Compiling package c_mux_slice_bufe_v4_0_comp
-- Compiling entity fifo_generator_v2_2_bhv_as
-- Compiling architecture behavioral of fifo_generator_v2_2_bhv_as
-- Compiling entity fifo_generator_v2_2_bhv_ss
-- Compiling architecture behavioral of fifo_generator_v2_2_bhv_ss
-- Compiling entity fifo_generator_v2_2_bhv_fifo16
-- Compiling architecture behavioral of fifo_generator_v2_2_bhv_fifo16
-- Compiling entity fifo_generator_v2_2_bhv_preload0
-- Compiling architecture behavioral of fifo_generator_v2_2_bhv_preload0
-- Loading entity fifo_generator_v2_2_bhv_as
-- Loading entity fifo_generator_v2_2_bhv_ss
-- Loading entity fifo_generator_v2_2_bhv_fifo16
-- Compiling entity fifo_generator_v2_2
-- Compiling architecture behavioral of fifo_generator_v2_2
-- Compiling package fifo_generator_v2_2_comp
-- Compiling entity c_mux_bit_v9_1
-- Compiling architecture behavioral of c_mux_bit_v9_1
-- Compiling package c_mux_bit_v9_1_comp
-- Loading package c_mux_bit_v9_1_comp
-- Compiling entity c_shift_fd_v9_1
-- Compiling architecture behavioral of c_shift_fd_v9_1
-- Compiling package c_shift_fd_v9_1_comp
-- Loading package c_shift_fd_v9_1_comp
-- Compiling entity c_shift_fd_v9_1_xst
-- Compiling architecture behavioral of c_shift_fd_v9_1_xst
-- Compiling package c_shift_fd_v9_1_xst_comp
-- Compiling entity async_fifo_v5_0
-- Compiling architecture behavioral of async_fifo_v5_0
-- Compiling package async_fifo_v5_0_comp
-- Compiling package blkmemsp_pkg_v3_2
-- Compiling package body blkmemsp_pkg_v3_2
-- Loading package blkmemsp_pkg_v3_2
-- Compiling package mem_init_file_pack_v3_2
-- Compiling package body mem_init_file_pack_v3_2
-- Loading package mem_init_file_pack_v3_2
-- Loading package mem_init_file_pack_v3_2
-- Loading package blkmemsp_pkg_v3_2
-- Compiling entity blkmemsp_v3_2
-- Compiling architecture behavioral of blkmemsp_v3_2
-- Compiling package blkmemsp_v3_2_comp
-- Compiling entity c_compare_v9_1_xst
-- Compiling architecture behavioral of c_compare_v9_1_xst
-- Compiling package c_compare_v9_1_xst_comp
-- Compiling package c_compare_v9_1_rtl_comp
-- Compiling package prims_utils_v7_0
-- Compiling package body prims_utils_v7_0
-- Loading package prims_utils_v7_0
-- Loading package prims_utils_v7_0
-- Compiling entity pipeline_v7_0
-- Compiling architecture behavioral of pipeline_v7_0
-- Compiling entity c_reg_ld_v7_0
-- Compiling architecture behavioral of c_reg_ld_v7_0
-- Compiling package c_reg_ld_v7_0_comp
-- Compiling entity c_reg_fd_v7_0
-- Compiling architecture behavioral of c_reg_fd_v7_0
-- Compiling package c_reg_fd_v7_0_comp
-- Loading package c_reg_fd_v7_0_comp
-- Compiling entity c_decode_binary_v7_0
-- Compiling architecture behavioral of c_decode_binary_v7_0
-- Compiling package c_decode_binary_v7_0_comp
-- Compiling entity c_mux_slice_buft_v7_0
-- Compiling architecture behavioral of c_mux_slice_buft_v7_0
-- Compiling package c_mux_slice_buft_v7_0_comp
-- Compiling entity c_mux_slice_bufe_v7_0
-- Compiling architecture behavioral of c_mux_slice_bufe_v7_0
-- Compiling package c_mux_slice_bufe_v7_0_comp
-- Compiling package prims_comps_v7_0
-- Loading package prims_comps_v7_0
-- Compiling entity c_buft_v7_0
-- Compiling architecture buft_beh of c_buft_v7_0
-- Compiling configuration cfg_buft_beh
-- Loading entity c_buft_v7_0
-- Loading architecture buft_beh of c_buft_v7_0
-- Compiling entity c_pullup_v7_0
-- Compiling architecture pullup_beh of c_pullup_v7_0
-- Compiling configuration cfg_pullup_beh
-- Loading entity c_pullup_v7_0
-- Loading architecture pullup_beh of c_pullup_v7_0
-- Compiling entity c_lut_v7_0
-- Compiling architecture lut_beh of c_lut_v7_0
-- Compiling configuration cfg_lut_beh
-- Loading entity c_lut_v7_0
-- Loading architecture lut_beh of c_lut_v7_0
-- Compiling package baseblox_v7_0_services
-- Compiling package body baseblox_v7_0_services
-- Loading package baseblox_v7_0_services
-- Compiling entity c_addsub_v7_0
-- Compiling architecture behavioral of c_addsub_v7_0
-- Compiling package c_addsub_v7_0_comp
-- Compiling entity c_compare_v7_0
-- Compiling architecture behavioral of c_compare_v7_0
-- Compiling package c_compare_v7_0_comp
-- Compiling entity c_mux_bus_v7_0
-- Compiling architecture behavioral of c_mux_bus_v7_0
-- Compiling package c_mux_bus_v7_0_comp
-- Compiling entity c_gate_bit_v7_0
-- Compiling architecture behavioral of c_gate_bit_v7_0
-- Compiling package c_gate_bit_v7_0_comp
-- Loading package c_addsub_v7_0_comp
-- Loading package c_compare_v7_0_comp
-- Loading package c_mux_bus_v7_0_comp
-- Loading package c_gate_bit_v7_0_comp
-- Compiling entity c_counter_binary_v7_0
-- Compiling architecture behavioral of c_counter_binary_v7_0
-- Compiling package c_counter_binary_v7_0_comp
-- Compiling entity lfsr_v3_0_dvunit_bhv
-- Compiling architecture xilinx of lfsr_v3_0_dvunit_bhv
-- Compiling entity lfsr_v3_0
-- Compiling architecture behavioral of lfsr_v3_0
-- Compiling package lfsr_v3_0_comp
-- Compiling package pkg_div_repmult_v1_0
-- Compiling package body pkg_div_repmult_v1_0
-- Loading package pkg_div_repmult_v1_0
-- Loading package pkg_div_repmult_v1_0
-- Compiling entity div_repmult_v1_0
-- Compiling architecture behavioral of div_repmult_v1_0
-- Compiling package div_repmult_v1_0_comp
-- Loading package div_repmult_v1_0_comp
-- Compiling entity div_repmult_v1_0_xst
-- Compiling architecture behavioral of div_repmult_v1_0_xst
-- Compiling package div_repmult_v1_0_xst_comp
-- Compiling package sync_fifo_pkg_v4_0
-- Compiling package body sync_fifo_pkg_v4_0
-- Loading package sync_fifo_pkg_v4_0
-- Loading package sync_fifo_pkg_v4_0
-- Compiling entity sync_fifo_v4_0
-- Compiling architecture behavioral of sync_fifo_v4_0
-- Compiling package sync_fifo_v4_0_comp
-- Compiling entity fifo_generator_v3_2_bhv_as
-- Compiling architecture behavioral of fifo_generator_v3_2_bhv_as
-- Compiling entity fifo_generator_v3_2_bhv_ss
-- Compiling architecture behavioral of fifo_generator_v3_2_bhv_ss
-- Compiling entity fifo_generator_v3_2_bhv_preload0
-- Compiling architecture behavioral of fifo_generator_v3_2_bhv_preload0
-- Loading entity fifo_generator_v3_2_bhv_as
-- Loading entity fifo_generator_v3_2_bhv_ss
-- Compiling entity fifo_generator_v3_2
-- Compiling architecture behavioral of fifo_generator_v3_2
-- Compiling package fifo_generator_v3_2_comp
-- Loading package fifo_generator_v3_2_comp
-- Compiling entity fifo_generator_v3_2_xst
-- Compiling architecture behavioral of fifo_generator_v3_2_xst
-- Compiling package fifo_generator_v3_2_xst_comp
-- Compiling entity c_mux_bus_v9_0
-- Compiling architecture behavioral of c_mux_bus_v9_0
-- Compiling package c_mux_bus_v9_0_comp
-- Loading package c_mux_bus_v9_0_comp
-- Compiling entity c_counter_binary_v9_0
-- Compiling architecture behavioral of c_counter_binary_v9_0
-- Compiling package c_counter_binary_v9_0_comp
-- Loading package c_counter_binary_v9_0_comp
-- Compiling entity c_counter_binary_v9_0_xst
-- Compiling architecture behavioral of c_counter_binary_v9_0_xst
-- Compiling package c_counter_binary_v9_0_xst_comp
-- Compiling entity fifo_generator_v1_0_bhv_as
-- Compiling architecture behavioral of fifo_generator_v1_0_bhv_as
-- Compiling entity fifo_generator_v1_0_bhv_ss
-- Compiling architecture behavioral of fifo_generator_v1_0_bhv_ss
-- Compiling entity fifo_generator_v1_0_bhv_fifo16
-- Compiling architecture behavioral of fifo_generator_v1_0_bhv_fifo16
-- Loading entity fifo_generator_v1_0_bhv_as
-- Loading entity fifo_generator_v1_0_bhv_ss
-- Compiling entity fifo_generator_v1_0
-- Compiling architecture behavioral of fifo_generator_v1_0
-- Compiling package fifo_generator_v1_0_comp
-- Compiling entity dist_mem_gen_v1_1
-- Compiling architecture behavioral of dist_mem_gen_v1_1
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127423):       file_open(mif_status, meminitfile, filename, read_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127423): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127435):          if not(endfile(meminitfile)) and i < depth then
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127435): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127438):             readline(meminitfile, bitline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127438): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127469):       file_close(meminitfile);      
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127469): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127557):          memory_content := read_mif(filename, def_data, depth, width);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(127557): (vcom-1284) Cannot call side-effect function "read_mif" from pure function "init_mem".
-- Compiling package dist_mem_gen_v1_1_comp
-- Loading package dist_mem_gen_v1_1_comp
-- Compiling entity dist_mem_gen_v1_1_xst
-- Compiling architecture behavioral of dist_mem_gen_v1_1_xst
-- Compiling package dist_mem_gen_v1_1_xst_comp
-- Compiling entity c_dist_mem_v7_1
-- Compiling architecture behavioral of c_dist_mem_v7_1
-- Compiling package c_dist_mem_v7_1_comp
-- Loading package c_dist_mem_v7_1_comp
-- Compiling entity c_dist_mem_v7_1_xst
-- Compiling architecture xilinx of c_dist_mem_v7_1_xst
-- Compiling package c_dist_mem_v7_1_xst_comp
-- Compiling package c_dist_mem_v7_1_services
-- Compiling package body c_dist_mem_v7_1_services
-- Loading package c_dist_mem_v7_1_services
-- Compiling entity lfsr_v2_0_dvunit_bhv
-- Compiling architecture xilinx of lfsr_v2_0_dvunit_bhv
-- Compiling entity lfsr_v2_0
-- Compiling architecture behavioral of lfsr_v2_0
-- Compiling package lfsr_v2_0_comp
-- Compiling entity c_compare_v8_0_xst
-- Compiling architecture behavioral of c_compare_v8_0_xst
-- Compiling package c_compare_v8_0_xst_comp
-- Compiling entity c_lut_v9_0
-- Compiling architecture behavioral of c_lut_v9_0
-- Compiling package c_lut_v9_0_comp
-- Loading package c_lut_v9_0_comp
-- Compiling entity c_lut_v9_0_xst
-- Compiling architecture behavioral of c_lut_v9_0_xst
-- Compiling package c_lut_v9_0_xst_comp
-- Compiling entity c_gate_bit_v9_1
-- Compiling architecture behavioral of c_gate_bit_v9_1
-- Compiling package c_gate_bit_v9_1_comp
-- Loading package c_gate_bit_v9_1_comp
-- Compiling entity c_gate_bit_v9_1_xst
-- Compiling architecture behavioral of c_gate_bit_v9_1_xst
-- Compiling package c_gate_bit_v9_1_xst_comp
-- Compiling entity fifo_generator_v2_3_bhv_as
-- Compiling architecture behavioral of fifo_generator_v2_3_bhv_as
-- Compiling entity fifo_generator_v2_3_bhv_ss
-- Compiling architecture behavioral of fifo_generator_v2_3_bhv_ss
-- Compiling entity fifo_generator_v2_3_bhv_fifo16
-- Compiling architecture behavioral of fifo_generator_v2_3_bhv_fifo16
-- Compiling entity fifo_generator_v2_3_bhv_preload0
-- Compiling architecture behavioral of fifo_generator_v2_3_bhv_preload0
-- Loading entity fifo_generator_v2_3_bhv_as
-- Loading entity fifo_generator_v2_3_bhv_ss
-- Loading entity fifo_generator_v2_3_bhv_fifo16
-- Compiling entity fifo_generator_v2_3
-- Compiling architecture behavioral of fifo_generator_v2_3
-- Compiling package fifo_generator_v2_3_comp
-- Compiling entity c_mux_bus_v9_1_xst
-- Compiling architecture behavioral of c_mux_bus_v9_1_xst
-- Compiling package c_mux_bus_v9_1_xst_comp
-- Compiling package blkmemsp_pkg_v6_2
-- Compiling package body blkmemsp_pkg_v6_2
-- Loading package blkmemsp_pkg_v6_2
-- Compiling package mem_init_file_pack_v6_2
-- Compiling package body mem_init_file_pack_v6_2
-- Loading package mem_init_file_pack_v6_2
-- Loading package mem_init_file_pack_v6_2
-- Loading package blkmemsp_pkg_v6_2
-- Compiling entity blkmemsp_v6_2
-- Compiling architecture behavioral of blkmemsp_v6_2
-- Compiling package blkmemsp_v6_2_comp
-- Loading package blkmemsp_v6_2_comp
-- Compiling entity blkmemsp_v6_2_xst
-- Compiling architecture xilinx of blkmemsp_v6_2_xst
-- Compiling package blkmemsp_v6_2_xst_comp
-- Compiling package prims_constants_v3_0
-- Compiling package prims_utils_v3_0
-- Loading package prims_constants_v3_0
-- Compiling package body prims_utils_v3_0
-- Loading package prims_utils_v3_0
-- Loading package prims_utils_v3_0
-- Compiling entity pipeline_v3_0
-- Compiling architecture behavioral of pipeline_v3_0
-- Compiling entity c_reg_fd_v3_0
-- Compiling architecture behavioral of c_reg_fd_v3_0
-- Compiling package c_reg_fd_v3_0_comp
-- Loading package c_reg_fd_v3_0_comp
-- Compiling entity c_shift_ram_v3_0
-- Compiling architecture behavioral of c_shift_ram_v3_0
-- Compiling package c_shift_ram_v3_0_comp
-- Compiling package prims_comps_v3_0
-- Loading package prims_comps_v3_0
-- Compiling entity c_lut_v3_0
-- Compiling architecture behavioral of c_lut_v3_0
-- Compiling configuration cfg_beh
-- Loading entity c_lut_v3_0
-- Loading architecture behavioral of c_lut_v3_0
-- Compiling entity c_addsub_v3_0
-- Compiling architecture behavioral of c_addsub_v3_0
-- Compiling package c_addsub_v3_0_comp
-- Compiling entity c_compare_v3_0
-- Compiling architecture behavioral of c_compare_v3_0
-- Compiling package c_compare_v3_0_comp
-- Compiling entity c_mux_bus_v3_0
-- Compiling architecture behavioral of c_mux_bus_v3_0
-- Compiling package c_mux_bus_v3_0_comp
-- Loading package c_addsub_v3_0_comp
-- Loading package c_compare_v3_0_comp
-- Loading package c_mux_bus_v3_0_comp
-- Compiling entity c_counter_binary_v3_0
-- Compiling architecture behavioral of c_counter_binary_v3_0
-- Compiling package c_counter_binary_v3_0_comp
-- Compiling entity c_gate_bus_v3_0
-- Compiling architecture behavioral of c_gate_bus_v3_0
-- Compiling package c_gate_bus_v3_0_comp
-- Compiling entity c_dist_mem_v3_0
-- Compiling architecture behavioral of c_dist_mem_v3_0
-- Compiling package c_dist_mem_v3_0_comp
-- Compiling entity c_mux_slice_bufe_v3_0
-- Compiling architecture behavioral of c_mux_slice_bufe_v3_0
-- Compiling package c_mux_slice_bufe_v3_0_comp
-- Compiling entity c_mux_slice_buft_v3_0
-- Compiling architecture behavioral of c_mux_slice_buft_v3_0
-- Compiling package c_mux_slice_buft_v3_0_comp
-- Compiling entity c_accum_v3_0
-- Compiling architecture behavioral of c_accum_v3_0
-- Compiling package c_accum_v3_0_comp
-- Compiling entity c_twos_comp_v3_0
-- Compiling architecture behavioral of c_twos_comp_v3_0
-- Compiling package c_twos_comp_v3_0_comp
-- Compiling entity c_gate_bit_v3_0
-- Compiling architecture behavioral of c_gate_bit_v3_0
-- Compiling package c_gate_bit_v3_0_comp
-- Compiling entity c_reg_ld_v3_0
-- Compiling architecture behavioral of c_reg_ld_v3_0
-- Compiling package c_reg_ld_v3_0_comp
-- Compiling entity c_gate_bit_bus_v3_0
-- Compiling architecture behavioral of c_gate_bit_bus_v3_0
-- Compiling package c_gate_bit_bus_v3_0_comp
-- Compiling entity c_decode_binary_v3_0
-- Compiling architecture behavioral of c_decode_binary_v3_0
-- Compiling package c_decode_binary_v3_0_comp
-- Compiling entity c_mux_bit_v3_0
-- Compiling architecture behavioral of c_mux_bit_v3_0
-- Compiling package c_mux_bit_v3_0_comp
-- Loading package c_mux_bit_v3_0_comp
-- Compiling entity c_shift_fd_v3_0
-- Compiling architecture behavioral of c_shift_fd_v3_0
-- Compiling package c_shift_fd_v3_0_comp
-- Compiling package blkmemdp_pkg_v6_3
-- Compiling package body blkmemdp_pkg_v6_3
-- Loading package blkmemdp_pkg_v6_3
-- Compiling package blkmemdp_mem_init_file_pack_v6_3
-- Compiling package body blkmemdp_mem_init_file_pack_v6_3
-- Loading package blkmemdp_mem_init_file_pack_v6_3
-- Loading package vital_timing
-- Loading package blkmemdp_mem_init_file_pack_v6_3
-- Loading package blkmemdp_pkg_v6_3
-- Compiling entity blkmemdp_v6_3
-- Compiling architecture behavioral of blkmemdp_v6_3
-- Compiling package blkmemdp_v6_3_comp
-- Loading package blkmemdp_v6_3_comp
-- Compiling entity blkmemdp_v6_3_xst
-- Compiling architecture xilinx of blkmemdp_v6_3_xst
-- Compiling package blkmemdp_v6_3_xst_comp
-- Compiling package blkmemdp_v6_3_services
-- Compiling package body blkmemdp_v6_3_services
-- Loading package blkmemdp_v6_3_services
-- Compiling package blkmemdp_v6_1_services
-- Compiling package body blkmemdp_v6_1_services
-- Loading package blkmemdp_v6_1_services
-- Compiling package blkmemdp_pkg_v6_1
-- Compiling package body blkmemdp_pkg_v6_1
-- Loading package blkmemdp_pkg_v6_1
-- Compiling package blkmemdp_mem_init_file_pack_v6_1
-- Compiling package body blkmemdp_mem_init_file_pack_v6_1
-- Loading package blkmemdp_mem_init_file_pack_v6_1
-- Loading package blkmemdp_mem_init_file_pack_v6_1
-- Loading package blkmemdp_pkg_v6_1
-- Compiling entity blkmemdp_v6_1
-- Compiling architecture behavioral of blkmemdp_v6_1
-- Compiling package blkmemdp_v6_1_comp
-- Loading package blkmemdp_v6_1_comp
-- Compiling entity blkmemdp_v6_1_xst
-- Compiling architecture xilinx of blkmemdp_v6_1_xst
-- Compiling package blkmemdp_v6_1_xst_comp
-- Compiling entity c_dist_mem_v4_1
-- Compiling architecture behavioral of c_dist_mem_v4_1
-- Compiling package c_dist_mem_v4_1_comp
-- Compiling entity c_mux_bit_v9_0
-- Compiling architecture behavioral of c_mux_bit_v9_0
-- Compiling package c_mux_bit_v9_0_comp
-- Loading package c_mux_bit_v9_0_comp
-- Compiling entity c_mux_bit_v9_0_xst
-- Compiling architecture behavioral of c_mux_bit_v9_0_xst
-- Compiling package c_mux_bit_v9_0_xst_comp
-- Compiling entity async_fifo_v5_1
-- Compiling architecture behavioral of async_fifo_v5_1
-- Compiling package async_fifo_v5_1_comp
-- Compiling package blkmemdp_pkg_v3_2
-- Compiling package body blkmemdp_pkg_v3_2
-- Loading package blkmemdp_pkg_v3_2
-- Loading package blkmemdp_pkg_v3_2
-- Compiling entity blkmemdp_v3_2
-- Compiling architecture behavioral of blkmemdp_v3_2
-- Compiling package blkmemdp_v3_2_comp
-- Compiling entity c_dist_mem_v4_0
-- Compiling architecture behavioral of c_dist_mem_v4_0
-- Compiling package c_dist_mem_v4_0_comp
-- Compiling entity c_addsub_v8_0_xst
-- Compiling architecture behavioral of c_addsub_v8_0_xst
-- Compiling package c_addsub_v8_0_xst_comp
-- Compiling entity dist_mem_gen_v3_3
-- Compiling architecture behavioral of dist_mem_gen_v3_3
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166281):       file_open(mif_status, meminitfile, filename, read_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166281): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166293):          if not(endfile(meminitfile)) and i < depth then
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166293): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166296):             readline(meminitfile, bitline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166296): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166327):       file_close(meminitfile);      
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166327): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166415):          memory_content := read_mif(filename, def_data, depth, width);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(166415): (vcom-1284) Cannot call side-effect function "read_mif" from pure function "init_mem".
-- Compiling package dist_mem_gen_v3_3_comp
-- Loading package dist_mem_gen_v3_3_comp
-- Compiling entity dist_mem_gen_v3_3_xst
-- Compiling architecture behavioral of dist_mem_gen_v3_3_xst
-- Compiling package dist_mem_gen_v3_3_xst_comp
-- Compiling entity c_gate_bit_v8_0
-- Compiling architecture behavioral of c_gate_bit_v8_0
-- Compiling package c_gate_bit_v8_0_comp
-- Loading package c_gate_bit_v8_0_comp
-- Compiling entity c_gate_bit_v8_0_xst
-- Compiling architecture behavioral of c_gate_bit_v8_0_xst
-- Compiling package c_gate_bit_v8_0_xst_comp
-- Compiling entity c_accum_v8_0
-- Compiling architecture behavioral of c_accum_v8_0
-- Compiling package c_accum_v8_0_comp
-- Loading package c_accum_v8_0_comp
-- Compiling entity c_accum_v8_0_xst
-- Compiling architecture behavioral of c_accum_v8_0_xst
-- Compiling package c_accum_v8_0_xst_comp
-- Compiling entity c_dist_mem_v5_0
-- Compiling architecture behavioral of c_dist_mem_v5_0
-- Compiling package c_dist_mem_v5_0_comp
-- Compiling package blkmemdp_pkg_v4_0
-- Compiling package body blkmemdp_pkg_v4_0
-- Loading package blkmemdp_pkg_v4_0
-- Compiling package mem_init_file_pack_v4_0
-- Compiling package body mem_init_file_pack_v4_0
-- Loading package mem_init_file_pack_v4_0
-- Loading package mem_init_file_pack_v4_0
-- Loading package blkmemdp_pkg_v4_0
-- Compiling entity blkmemdp_v4_0
-- Compiling architecture behavioral of blkmemdp_v4_0
-- Compiling package blkmemdp_v4_0_comp
-- Compiling entity c_compare_v4_0
-- Compiling architecture behavioral of c_compare_v4_0
-- Compiling package c_compare_v4_0_comp
-- Compiling entity c_mux_bus_v4_0
-- Compiling architecture behavioral of c_mux_bus_v4_0
-- Compiling package c_mux_bus_v4_0_comp
-- Loading package c_compare_v4_0_comp
-- Loading package c_mux_bus_v4_0_comp
-- Compiling entity c_counter_binary_v4_0
-- Compiling architecture behavioral of c_counter_binary_v4_0
-- Compiling package c_counter_binary_v4_0_comp
-- Compiling entity c_gate_bus_v4_0
-- Compiling architecture behavioral of c_gate_bus_v4_0
-- Compiling package c_gate_bus_v4_0_comp
-- Compiling entity c_gate_bit_v4_0
-- Compiling architecture behavioral of c_gate_bit_v4_0
-- Compiling package c_gate_bit_v4_0_comp
-- Compiling package async_fifo_v4_0_pkg
-- Compiling package body async_fifo_v4_0_pkg
-- Loading package async_fifo_v4_0_pkg
-- Compiling package async_fifo_v4_0_components
-- Loading package c_dist_mem_v5_0_comp
-- Loading package blkmemdp_v4_0_comp
-- Compiling entity memory_v4
-- Compiling architecture behavioral of memory_v4
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity full_flag_reg_v4
-- Compiling architecture behavioral of full_flag_reg_v4
-- Compiling entity empty_flag_reg_v4
-- Compiling architecture behavioral of empty_flag_reg_v4
-- Compiling entity almst_full_v4
-- Compiling architecture behavioral of almst_full_v4
-- Compiling entity almst_empty_v4
-- Compiling architecture behavioral of almst_empty_v4
-- Loading package prims_constants_v4_0
-- Loading package c_counter_binary_v4_0_comp
-- Compiling entity bcount_up_ainit_v4
-- Compiling architecture behavioral of bcount_up_ainit_v4
-- Loading package c_gate_bus_v4_0_comp
-- Compiling entity binary_to_gray_v4
-- Compiling architecture behavioral of binary_to_gray_v4
-- Loading package c_compare_v4_0_comp
-- Compiling entity eq_compare_v4
-- Compiling architecture behavioral of eq_compare_v4
-- Loading package c_reg_fd_v4_0_comp
-- Compiling entity reg_ainit_v4
-- Compiling architecture behavioral of reg_ainit_v4
-- Loading package c_gate_bit_v4_0_comp
-- Compiling entity and_a_b_v4
-- Compiling architecture behavioral of and_a_b_v4
-- Compiling entity or_a_b_v4
-- Compiling architecture behavioral of or_a_b_v4
-- Compiling entity and_a_notb_v4
-- Compiling architecture behavioral of and_a_notb_v4
-- Compiling entity and_a_notb_fd_v4
-- Compiling architecture behavioral of and_a_notb_fd_v4
-- Compiling entity nand_a_notb_fd_v4
-- Compiling architecture behavioral of nand_a_notb_fd_v4
-- Compiling entity and_a_b_notc_v4
-- Compiling architecture behavioral of and_a_b_notc_v4
-- Compiling entity and_a_b_c_notd_v4
-- Compiling architecture behavioral of and_a_b_c_notd_v4
-- Compiling entity or_fd_v4
-- Compiling architecture behavioral of or_fd_v4
-- Compiling entity and_fd_v4
-- Compiling architecture behavioral of and_fd_v4
-- Compiling entity nand_fd_v4
-- Compiling architecture behavioral of nand_fd_v4
-- Compiling entity or3_fd_v4
-- Compiling architecture behavioral of or3_fd_v4
-- Loading package c_addsub_v4_0_comp
-- Loading package async_fifo_v4_0_components
-- Compiling entity count_sub_reg_v4
-- Compiling architecture behavioral of count_sub_reg_v4
-- Compiling entity xor_gate_bit_v4
-- Compiling architecture behavioral of xor_gate_bit_v4
-- Compiling entity gray_to_binary_v4
-- Compiling architecture behavioral of gray_to_binary_v4
-- Compiling entity fifoctlr_ns_v4
-- Compiling architecture behavioral of fifoctlr_ns_v4
-- Loading package prims_comps_v4_0
-- Loading package async_fifo_v4_0_pkg
-- Compiling entity async_fifo_v4_0
-- Compiling architecture behavioral of async_fifo_v4_0
-- Compiling package async_fifo_v4_0_comp
-- Compiling entity c_mux_slice_buft_v2_0
-- Compiling architecture behavioral of c_mux_slice_buft_v2_0
-- Compiling package c_mux_slice_buft_v2_0_comp
-- Compiling package prims_constants_v2_0
-- Loading package prims_constants_v2_0
-- Compiling package prims_comps_v2_0
-- Compiling package prims_utils_v2_0
-- Loading package std_logic_arith
-- Loading package textio
-- Compiling package body prims_utils_v2_0
-- Loading package prims_utils_v2_0
-- Loading package prims_utils_v2_0
-- Compiling entity pipeline_v2_0
-- Compiling architecture behavioral of pipeline_v2_0
-- Loading package prims_comps_v2_0
-- Compiling entity c_lut_v2_0
-- Compiling architecture behavioral of c_lut_v2_0
-- Compiling configuration cfg_beh
-- Loading entity c_lut_v2_0
-- Loading architecture behavioral of c_lut_v2_0
-- Compiling entity c_reg_fd_v2_0
-- Compiling architecture behavioral of c_reg_fd_v2_0
-- Compiling package c_reg_fd_v2_0_comp
-- Loading package c_reg_fd_v2_0_comp
-- Compiling entity c_addsub_v2_0
-- Compiling architecture behavioral of c_addsub_v2_0
-- Compiling package c_addsub_v2_0_comp
-- Loading package c_addsub_v2_0_comp
-- Compiling entity c_accum_v2_0
-- Compiling architecture behavioral of c_accum_v2_0
-- Compiling package c_accum_v2_0_comp
-- Compiling entity c_gate_bus_v2_0
-- Compiling architecture behavioral of c_gate_bus_v2_0
-- Compiling package c_gate_bus_v2_0_comp
-- Loading package ul_utils
-- Loading package mem_init_file_pack_v5_0
-- Compiling entity c_shift_ram_v2_0
-- Compiling architecture behavioral of c_shift_ram_v2_0
-- Compiling package c_shift_ram_v2_0_comp
-- Compiling entity c_mux_slice_bufe_v2_0
-- Compiling architecture behavioral of c_mux_slice_bufe_v2_0
-- Compiling package c_mux_slice_bufe_v2_0_comp
-- Compiling entity c_compare_v2_0
-- Compiling architecture behavioral of c_compare_v2_0
-- Compiling package c_compare_v2_0_comp
-- Compiling entity c_mux_bus_v2_0
-- Compiling architecture behavioral of c_mux_bus_v2_0
-- Compiling package c_mux_bus_v2_0_comp
-- Loading package c_compare_v2_0_comp
-- Loading package c_mux_bus_v2_0_comp
-- Compiling entity c_counter_binary_v2_0
-- Compiling architecture behavioral of c_counter_binary_v2_0
-- Compiling package c_counter_binary_v2_0_comp
-- Compiling entity c_twos_comp_v2_0
-- Compiling architecture behavioral of c_twos_comp_v2_0
-- Compiling package c_twos_comp_v2_0_comp
-- Compiling entity c_gate_bit_v2_0
-- Compiling architecture behavioral of c_gate_bit_v2_0
-- Compiling package c_gate_bit_v2_0_comp
-- Compiling entity c_dist_mem_v2_0
-- Compiling architecture behavioral of c_dist_mem_v2_0
-- Compiling package c_dist_mem_v2_0_comp
-- Compiling entity c_mux_bit_v2_0
-- Compiling architecture behavioral of c_mux_bit_v2_0
-- Compiling package c_mux_bit_v2_0_comp
-- Loading package c_mux_bit_v2_0_comp
-- Compiling entity c_shift_fd_v2_0
-- Compiling architecture behavioral of c_shift_fd_v2_0
-- Compiling package c_shift_fd_v2_0_comp
-- Compiling entity c_reg_ld_v2_0
-- Compiling architecture behavioral of c_reg_ld_v2_0
-- Compiling package c_reg_ld_v2_0_comp
-- Compiling entity c_decode_binary_v2_0
-- Compiling architecture behavioral of c_decode_binary_v2_0
-- Compiling package c_decode_binary_v2_0_comp
-- Compiling entity c_gate_bit_bus_v2_0
-- Compiling architecture behavioral of c_gate_bit_bus_v2_0
-- Compiling package c_gate_bit_bus_v2_0_comp
-- Loading package numeric_std
-- Loading package prims_constants_v9_0
-- Loading package c_addsub_v9_0_comp
-- Compiling entity c_addsub_v9_0_xst
-- Compiling architecture behavioral of c_addsub_v9_0_xst
-- Compiling package c_addsub_v9_0_xst_comp
-- Loading package std_logic_unsigned
-- Compiling entity blk_mem_gen_v2_1_output_stage
-- Compiling architecture behavioral of blk_mem_gen_v2_1_output_stage
-- Compiling entity blk_mem_gen_v2_1
-- Compiling architecture behavioral of blk_mem_gen_v2_1
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191758):       file_open(init_file, C_INIT_FILE_NAME, read_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191758): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191760):       while (i < depth and not endfile(init_file)) loop
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191760): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191762):         readline(init_file, file_buffer);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191762): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191772):       file_close(init_file);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(191772): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
-- Loading package std_logic_textio
-- Compiling package blk_mem_gen_v2_1_comp
-- Loading package blk_mem_gen_v2_1_comp
-- Compiling entity blk_mem_gen_v2_1_xst
-- Compiling architecture behavioral of blk_mem_gen_v2_1_xst
-- Compiling package blk_mem_gen_v2_1_xst_comp
-- Loading package prims_constants_v9_1
-- Loading package prims_utils_v9_1
-- Loading package c_mux_bit_v9_1_comp
-- Compiling entity c_mux_bit_v9_1_xst
-- Compiling architecture behavioral of c_mux_bit_v9_1_xst
-- Compiling package c_mux_bit_v9_1_xst_comp
-- Loading package c_addsub_v9_1_comp
-- Compiling entity c_addsub_v9_1_xst
-- Compiling architecture behavioral of c_addsub_v9_1_xst
-- Compiling package c_addsub_v9_1_xst_comp
-- Compiling entity example
-- Compiling architecture synth of example
-- Loading package iputils_conv
-- Loading package iputils_misc
-- Compiling entity fifo_generator_v2_1_bhv_as
-- Compiling architecture behavioral of fifo_generator_v2_1_bhv_as
-- Compiling entity fifo_generator_v2_1_bhv_ss
-- Compiling architecture behavioral of fifo_generator_v2_1_bhv_ss
-- Compiling entity fifo_generator_v2_1_bhv_fifo16
-- Compiling architecture behavioral of fifo_generator_v2_1_bhv_fifo16
-- Compiling entity fifo_generator_v2_1_bhv_preload0
-- Compiling architecture behavioral of fifo_generator_v2_1_bhv_preload0
-- Loading entity fifo_generator_v2_1_bhv_as
-- Loading entity fifo_generator_v2_1_bhv_ss
-- Loading entity fifo_generator_v2_1_bhv_fifo16
-- Compiling entity fifo_generator_v2_1
-- Compiling architecture behavioral of fifo_generator_v2_1
-- Compiling package fifo_generator_v2_1_comp
-- Compiling package sync_fifo_pkg_v3_0
-- Compiling package body sync_fifo_pkg_v3_0
-- Loading package sync_fifo_pkg_v3_0
-- Loading package sync_fifo_pkg_v3_0
-- Compiling entity sync_fifo_v3_0
-- Compiling architecture behavioral of sync_fifo_v3_0
-- Compiling package sync_fifo_v3_0_comp
-- Loading package prims_utils_v9_0
-- Loading package c_mux_bus_v9_0_comp
-- Compiling entity c_mux_bus_v9_0_xst
-- Compiling architecture behavioral of c_mux_bus_v9_0_xst
-- Compiling package c_mux_bus_v9_0_xst_comp
-- Loading package prims_constants_v8_0
-- Loading package prims_utils_v8_0
-- Loading package pkg_baseblox_v8_0
-- Loading package c_reg_fd_v8_0_comp
-- Compiling entity c_twos_comp_v8_0
-- Compiling architecture behavioral of c_twos_comp_v8_0
-- Compiling package c_twos_comp_v8_0_comp
-- Loading package c_twos_comp_v8_0_comp
-- Compiling entity c_twos_comp_v8_0_xst
-- Compiling architecture behavioral of c_twos_comp_v8_0_xst
-- Compiling package c_twos_comp_v8_0_xst_comp
-- Compiling entity fifo_generator_v1_1_bhv_as
-- Compiling architecture behavioral of fifo_generator_v1_1_bhv_as
-- Compiling entity fifo_generator_v1_1_bhv_ss
-- Compiling architecture behavioral of fifo_generator_v1_1_bhv_ss
-- Compiling entity fifo_generator_v1_1_bhv_fifo16
-- Compiling architecture behavioral of fifo_generator_v1_1_bhv_fifo16
-- Loading entity fifo_generator_v1_1_bhv_as
-- Loading entity fifo_generator_v1_1_bhv_ss
-- Compiling entity fifo_generator_v1_1
-- Compiling architecture behavioral of fifo_generator_v1_1
-- Compiling package fifo_generator_v1_1_comp
-- Compiling package blkmemdp_v4_0_services
-- Compiling package body blkmemdp_v4_0_services
-- Loading package blkmemdp_v4_0_services
-- Compiling package blkmemsp_pkg_v6_0
-- Compiling package body blkmemsp_pkg_v6_0
-- Loading package blkmemsp_pkg_v6_0
-- Compiling package mem_init_file_pack_v6_0
-- Compiling package body mem_init_file_pack_v6_0
-- Loading package mem_init_file_pack_v6_0
-- Loading package mem_init_file_pack_v6_0
-- Loading package blkmemsp_pkg_v6_0
-- Compiling entity blkmemsp_v6_0
-- Compiling architecture behavioral of blkmemsp_v6_0
-- Compiling package blkmemsp_v6_0_comp
-- Compiling entity blk_mem_gen_v1_1_output_stage
-- Compiling architecture behavioral of blk_mem_gen_v1_1_output_stage
-- Compiling entity blk_mem_gen_v1_1
-- Compiling architecture behavioral of blk_mem_gen_v1_1
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207521):       file_open(init_file, C_INIT_FILE_NAME, read_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207521): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207523):       while (i < depth and not endfile(init_file)) loop
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207523): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207525):         readline(init_file, file_buffer);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207525): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207535):       file_close(init_file);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(207535): (vcom-1283) Cannot reference file "init_file" inside pure function "init_memory".
-- Compiling entity dist_mem_gen_v2_1
-- Compiling architecture behavioral of dist_mem_gen_v2_1
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208619):       file_open(mif_status, meminitfile, filename, read_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208619): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208631):          if not(endfile(meminitfile)) and i < depth then
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208631): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208634):             readline(meminitfile, bitline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208634): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208665):       file_close(meminitfile);      
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208665): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208753):          memory_content := read_mif(filename, def_data, depth, width);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(208753): (vcom-1284) Cannot call side-effect function "read_mif" from pure function "init_mem".
-- Compiling package dist_mem_gen_v2_1_comp
-- Loading package dist_mem_gen_v2_1_comp
-- Compiling entity dist_mem_gen_v2_1_xst
-- Compiling architecture behavioral of dist_mem_gen_v2_1_xst
-- Compiling package dist_mem_gen_v2_1_xst_comp
-- Loading package iputils_math
-- Compiling package cam_v5_1_pkg
-- Compiling package body cam_v5_1_pkg
-- Loading package cam_v5_1_pkg
-- Loading package cam_v5_1_pkg
-- Loading package iputils_mem87
-- Loading package iputils_slv
-- Compiling entity cam_v5_1
-- Compiling architecture behavioral of cam_v5_1
-- Compiling package cam_v5_1_comp
-- Compiling package pkg_div_gen_v1_0
-- Compiling package body pkg_div_gen_v1_0
-- Loading package pkg_div_gen_v1_0
-- Loading package pkg_div_gen_v1_0
-- Loading package div_repmult_v1_0_comp
-- Loading package sdivider_v4_0_comp
-- Compiling entity div_gen_v1_0
-- Compiling architecture behavioral of div_gen_v1_0
-- Compiling package div_gen_v1_0_comp
-- Loading package div_gen_v1_0_comp
-- Compiling entity div_gen_v1_0_xst
-- Compiling architecture behavioral of div_gen_v1_0_xst
-- Compiling package div_gen_v1_0_xst_comp
-- Loading package pkg_baseblox_v9_1
-- Compiling entity c_lut_v9_1
-- Compiling architecture behavioral of c_lut_v9_1
-- Compiling package c_lut_v9_1_comp
-- Loading package c_lut_v9_1_comp
-- Compiling entity c_lut_v9_1_xst
-- Compiling architecture behavioral of c_lut_v9_1_xst
-- Compiling package c_lut_v9_1_xst_comp
-- Loading package c_reg_fd_v9_0_comp
-- Loading package c_mux_bit_v9_0_comp
-- Compiling entity c_shift_fd_v9_0
-- Compiling architecture behavioral of c_shift_fd_v9_0
-- Compiling package c_shift_fd_v9_0_comp
-- Loading package c_shift_fd_v9_0_comp
-- Compiling entity c_shift_fd_v9_0_xst
-- Compiling architecture behavioral of c_shift_fd_v9_0_xst
-- Compiling package c_shift_fd_v9_0_xst_comp
-- Compiling entity async_fifo_v6_0
-- Compiling architecture behavioral of async_fifo_v6_0
-- Compiling package async_fifo_v6_0_comp
-- Compiling package blkmemdp_pkg_v6_2
-- Compiling package body blkmemdp_pkg_v6_2
-- Loading package blkmemdp_pkg_v6_2
-- Compiling package blkmemdp_mem_init_file_pack_v6_2
-- Compiling package body blkmemdp_mem_init_file_pack_v6_2
-- Loading package blkmemdp_mem_init_file_pack_v6_2
-- Loading package vital_timing
-- Loading package blkmemdp_mem_init_file_pack_v6_2
-- Loading package blkmemdp_pkg_v6_2
-- Compiling entity blkmemdp_v6_2
-- Compiling architecture behavioral of blkmemdp_v6_2
-- Compiling package blkmemdp_v6_2_comp
-- Loading package blkmemdp_v6_2_comp
-- Compiling entity blkmemdp_v6_2_xst
-- Compiling architecture xilinx of blkmemdp_v6_2_xst
-- Compiling package blkmemdp_v6_2_xst_comp
-- Compiling package blkmemdp_v6_2_services
-- Compiling package body blkmemdp_v6_2_services
-- Loading package blkmemdp_v6_2_services
-- Loading package prims_constants_v5_0
-- Loading package prims_utils_v5_0
-- Loading package c_reg_fd_v5_0_comp
-- Compiling entity c_gate_bit_bus_v5_0
-- Compiling architecture behavioral of c_gate_bit_bus_v5_0
-- Compiling package c_gate_bit_bus_v5_0_comp
-- Compiling entity c_mux_slice_bufe_v5_0
-- Compiling architecture behavioral of c_mux_slice_bufe_v5_0
-- Compiling package c_mux_slice_bufe_v5_0_comp
-- Compiling package baseblox_v5_0_services
-- Compiling package body baseblox_v5_0_services
-- Loading package baseblox_v5_0_services
-- Compiling entity c_decode_binary_v5_0
-- Compiling architecture behavioral of c_decode_binary_v5_0
-- Compiling package c_decode_binary_v5_0_comp
-- Compiling entity c_gate_bit_v5_0
-- Compiling architecture behavioral of c_gate_bit_v5_0
-- Compiling package c_gate_bit_v5_0_comp
-- Compiling package prims_comps_v5_0
-- Loading package prims_comps_v5_0
-- Compiling entity c_lut_v5_0
-- Compiling architecture behavioral of c_lut_v5_0
-- Compiling configuration cfg_lut
-- Loading entity c_lut_v5_0
-- Loading architecture behavioral of c_lut_v5_0
-- Compiling entity c_addsub_v5_0
-- Compiling architecture behavioral of c_addsub_v5_0
-- Compiling package c_addsub_v5_0_comp
-- Loading package c_addsub_v5_0_comp
-- Compiling entity c_accum_v5_1
-- Compiling architecture behavioral of c_accum_v5_1
-- Compiling package c_accum_v5_1_comp
-- Compiling entity c_reg_ld_v5_0
-- Compiling architecture behavioral of c_reg_ld_v5_0
-- Compiling package c_reg_ld_v5_0_comp
-- Compiling entity c_compare_v5_0
-- Compiling architecture behavioral of c_compare_v5_0
-- Compiling package c_compare_v5_0_comp
-- Compiling entity c_mux_bus_v5_0
-- Compiling architecture behavioral of c_mux_bus_v5_0
-- Compiling package c_mux_bus_v5_0_comp
-- Loading package c_compare_v5_0_comp
-- Loading package c_mux_bus_v5_0_comp
-- Compiling entity c_counter_binary_v5_0
-- Compiling architecture behavioral of c_counter_binary_v5_0
-- Compiling package c_counter_binary_v5_0_comp
-- Compiling entity c_gate_bus_v5_0
-- Compiling architecture behavioral of c_gate_bus_v5_0
-- Compiling package c_gate_bus_v5_0_comp
-- Compiling entity c_mux_slice_buft_v5_0
-- Compiling architecture behavioral of c_mux_slice_buft_v5_0
-- Compiling package c_mux_slice_buft_v5_0_comp
-- Compiling package blkmemsp_pkg_v4_0
-- Compiling package body blkmemsp_pkg_v4_0
-- Loading package blkmemsp_pkg_v4_0
-- Loading package mem_init_file_pack_v4_0
-- Loading package blkmemsp_pkg_v4_0
-- Compiling entity blkmemsp_v4_0
-- Compiling architecture behavioral of blkmemsp_v4_0
-- Compiling package blkmemsp_v4_0_comp
-- Compiling package sync_fifo_pkg_v5_0
-- Compiling package body sync_fifo_pkg_v5_0
-- Loading package sync_fifo_pkg_v5_0
-- Loading package sync_fifo_pkg_v5_0
-- Compiling entity sync_fifo_v5_0
-- Compiling architecture behavioral of sync_fifo_v5_0
-- Compiling package sync_fifo_v5_0_comp
-- Loading package sync_fifo_v5_0_comp
-- Compiling entity sync_fifo_v5_0_xst
-- Compiling architecture xilinx of sync_fifo_v5_0_xst
-- Compiling package sync_fifo_v5_0_xst_comp
-- Compiling entity dist_mem_gen_v3_2
-- Compiling architecture behavioral of dist_mem_gen_v3_2
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228103):       file_open(mif_status, meminitfile, filename, read_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228103): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228115):          if not(endfile(meminitfile)) and i < depth then
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228115): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228118):             readline(meminitfile, bitline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228118): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228149):       file_close(meminitfile);      
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228149): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_mif".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228237):          memory_content := read_mif(filename, def_data, depth, width);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(228237): (vcom-1284) Cannot call side-effect function "read_mif" from pure function "init_mem".
-- Compiling package dist_mem_gen_v3_2_comp
-- Loading package dist_mem_gen_v3_2_comp
-- Compiling entity dist_mem_gen_v3_2_xst
-- Compiling architecture behavioral of dist_mem_gen_v3_2_xst
-- Compiling package dist_mem_gen_v3_2_xst_comp
-- Loading package c_reg_fd_v9_1_comp
-- Compiling entity c_accum_v9_1
-- Compiling architecture behavioral of c_accum_v9_1
-- Compiling package c_accum_v9_1_comp
-- Loading package c_accum_v9_1_comp
-- Compiling entity c_accum_v9_1_xst
-- Compiling architecture behavioral of c_accum_v9_1_xst
-- Compiling package c_accum_v9_1_xst_comp
-- Loading package iputils_std_logic_arith
-- Loading package iputils_std_logic_unsigned
-- Compiling entity fifo_generator_v3_3_bhv_as
-- Compiling architecture behavioral of fifo_generator_v3_3_bhv_as
-- Compiling entity fifo_generator_v3_3_bhv_ss
-- Compiling architecture behavioral of fifo_generator_v3_3_bhv_ss
-- Compiling entity fifo_generator_v3_3_bhv_preload0
-- Compiling architecture behavioral of fifo_generator_v3_3_bhv_preload0
-- Loading entity fifo_generator_v3_3_bhv_as
-- Loading entity fifo_generator_v3_3_bhv_ss
-- Compiling entity fifo_generator_v3_3
-- Compiling architecture behavioral of fifo_generator_v3_3
-- Compiling package fifo_generator_v3_3_comp
-- Loading package fifo_generator_v3_3_comp
-- Compiling entity fifo_generator_v3_3_xst
-- Compiling architecture behavioral of fifo_generator_v3_3_xst
-- Compiling package fifo_generator_v3_3_xst_comp
-- Loading package pkg_baseblox_v9_0
-- Compiling entity c_shift_ram_v9_0
-- Compiling architecture behavioral of c_shift_ram_v9_0
-- Compiling package c_shift_ram_v9_0_comp
-- Loading package c_shift_ram_v9_0_comp
-- Compiling entity c_shift_ram_v9_0_xst
-- Compiling architecture behavioral of c_shift_ram_v9_0_xst
-- Compiling package c_shift_ram_v9_0_xst_comp
-- Compiling package decode_8b10b_v5_0_pkg
-- Compiling package body decode_8b10b_v5_0_pkg
-- Loading package decode_8b10b_v5_0_pkg
-- Loading package decode_8b10b_v5_0_pkg
-- Compiling entity decode_8b10b_v5_0_base
-- Compiling architecture behavioral of decode_8b10b_v5_0_base
-- Loading entity decode_8b10b_v5_0_base
-- Compiling entity decode_8b10b_v5_0
-- Compiling architecture behavioral of decode_8b10b_v5_0
-- Compiling package decode_8b10b_v5_0_comp
-- Compiling package decode_8b10b_v7_0_pkg
-- Compiling package body decode_8b10b_v7_0_pkg
-- Loading package decode_8b10b_v7_0_pkg
-- Loading package decode_8b10b_v7_0_pkg
-- Compiling entity decode_8b10b_v7_0_base
-- Compiling architecture behavioral of decode_8b10b_v7_0_base
-- Loading entity decode_8b10b_v7_0_base
-- Compiling entity decode_8b10b_v7_0
-- Compiling architecture behavioral of decode_8b10b_v7_0
-- Compiling package decode_8b10b_v7_0_comp
-- Compiling package decode_8b10b_v7_1_pkg
-- Compiling package body decode_8b10b_v7_1_pkg
-- Loading package decode_8b10b_v7_1_pkg
-- Loading package decode_8b10b_v7_1_pkg
-- Compiling entity decode_8b10b_v7_1_base
-- Compiling architecture behavioral of decode_8b10b_v7_1_base
-- Loading entity decode_8b10b_v7_1_base
-- Compiling entity decode_8b10b_v7_1
-- Compiling architecture behavioral of decode_8b10b_v7_1
-- Compiling package decode_8b10b_v7_1_comp
-- Compiling package decode_8b10b_v6_0_pkg
-- Compiling package body decode_8b10b_v6_0_pkg
-- Loading package decode_8b10b_v6_0_pkg
-- Loading package decode_8b10b_v6_0_pkg
-- Compiling entity decode_8b10b_v6_0_base
-- Compiling architecture behavioral of decode_8b10b_v6_0_base
-- Loading entity decode_8b10b_v6_0_base
-- Compiling entity decode_8b10b_v6_0
-- Compiling architecture behavioral of decode_8b10b_v6_0
-- Compiling package decode_8b10b_v6_0_comp
-- Compiling entity encode_8b10b_v4_0_base
-- Compiling architecture behavioral of encode_8b10b_v4_0_base
-- Loading entity encode_8b10b_v4_0_base
-- Compiling entity encode_8b10b_v4_0
-- Compiling architecture behavioral of encode_8b10b_v4_0
-- Compiling package encode_8b10b_v4_0_comp
-- Loading package vcomponents
-- Loading package vital_primitives
-- Loading package vpkg
-- Compiling entity pci_exp_4_lane_64b_dsport
-- Compiling architecture structure of pci_exp_4_lane_64b_dsport
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package vcomponents
-- Loading package textio
-- Loading package vital_timing
-- Loading package vital_primitives
-- Loading package vpkg
-- Compiling entity pci_exp_1_lane_64b_dsport
-- Compiling architecture structure of pci_exp_1_lane_64b_dsport
-- Loading package iputils_conv
-- Compiling entity encode_8b10b_v5_0_base
-- Compiling architecture behavioral of encode_8b10b_v5_0_base
-- Loading entity encode_8b10b_v5_0_base
-- Compiling entity encode_8b10b_v5_0
-- Compiling architecture behavioral of encode_8b10b_v5_0
-- Compiling package encode_8b10b_v5_0_comp
-- Compiling package tcc_decoder_3gpp_top_level_pkg_v2_0
-- Compiling package body tcc_decoder_3gpp_top_level_pkg_v2_0
-- Loading package tcc_decoder_3gpp_top_level_pkg_v2_0
-- Loading package tcc_decoder_3gpp_top_level_pkg_v2_0
-- Compiling entity tcc_decoder_3gpp_v2_0
-- Compiling architecture behavioral of tcc_decoder_3gpp_v2_0
-- Compiling package tcc_decoder_3gpp_v2_0_comp
-- Compiling package body tcc_decoder_3gpp_v2_0_comp
-- Loading package tcc_decoder_3gpp_v2_0_comp
-- Compiling entity tcc_decoder_3gpp_v2_0_xst
-- Compiling architecture behavioral of tcc_decoder_3gpp_v2_0_xst
-- Compiling package tcc_decoder_3gpp_v2_0_xst_comp
-- Compiling package body tcc_decoder_3gpp_v2_0_xst_comp
-- Loading package tcc_decoder_3gpp_v2_0_xst_comp
-- Compiling package rs_ftns_pkg_v5_1
-- Compiling package body rs_ftns_pkg_v5_1
-- Loading package rs_ftns_pkg_v5_1
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(668174): IO1OIOI0I1l11O0IllIOllII1llIIOIIII>0 AND IO1OIOI0I1l11O0IllIOllII1llIIOIIII<=IIlO0IOl0I0I0lI0OOll1l1l1lO0IIIIII)THEN II0Ol0OI111lIO001O0IIlO110IlIOIIII:=IO1OIOI0I1l11O0IllIOllII1llIIOIIII;ELSE II0Ol0OI111lIO001O0IIlO110IlIOIIII:=IIlO0IOl0I0I0lI0OOll1l1l1lO0IIIIII;END IF;II1ll00lO01110lOI1I0IOO0IlO0IIIIII:=0;IOIIOIIO1lIIOOl0IlO11I00II110IIIII:=0;WHILE(NOT(ENDFILE(MEMINITFILE
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(668174): (vcom-1283) Cannot reference file "meminitfile" inside pure function "io01l1ll0iloll0i00lll11l0olliiiiii".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(668175): ))AND(II1ll00lO01110lOI1I0IOO0IlO0IIIIII<II0Ol0OI111lIO001O0IIlO110IlIOIIII))LOOP READLINE(MEMINITFILE,IO00lII1lIll0OllOlI1l1O0OI100IIIII);READ(IO00lII1lIll0OllOlI1l1O0OI100IIIII,IO0I011OOl0OOO000O0I0O0OO0OllIIIII,II10ll00IlO1IIOIOIO10II0lI1l0IIIII);ASSERT II10ll00IlO1IIOIOIO10II0lI1l0IIIII REPORT
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(668175): (vcom-1283) Cannot reference file "meminitfile" inside pure function "io01l1ll0iloll0i00lll11l0olliiiiii".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(668180):  TO(II0IOOI1Il101lO1O010O0O0IO10IOIIII-1));BEGIN IF(II0IOOI1Il101lO1O010O0O0IO10IOIIII>0)THEN III1O0Ol0IOOO0IllIOOO000O1lO0IIIII:=IO01l1ll0IlOll0I00lll11l0OllIIIIII(IOO1l1010O10O10I0llO11O100O1IOIIII,II0IOOI1Il101lO1O010O0O0IO10IOIIII,IOIlOIOl1lO1l001Ol10IO01OIlI1IIIII,II0IOOI1Il101lO1O010O0O0IO10IOIIII);IIl1IIO111llI0l1O1OI00lIl1I0OIIIII:=
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(668180): (vcom-1284) Cannot call side-effect function "io01l1ll0iloll0i00lll11l0olliiiiii" from pure function "iol0l10li11io10li1oi1ioi01oo0iiiii".
-- Loading package rs_ftns_pkg_v5_1
-- Loading package iputils_std_logic_arith
-- Loading package iputils_std_logic_unsigned
-- Compiling entity rs_decoder_v5_1
-- Loading package standard
-- Compiling architecture behavioral of rs_decoder_v5_1
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-- Loading package rs_ftns_pkg_v5_1
-- Loading package iputils_std_logic_arith
-- Loading package iputils_std_logic_unsigned
-- Loading entity rs_decoder_v5_1
-- Compiling package rs_decoder_v5_1_comp
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-- Loading package ul_utils
-- Compiling package mac_fir_v3_0_comp
-- Compiling package fir_compiler_v1_0_xst_comp
-- Compiling package fir_compiler_v1_0_comp
-- Compiling entity addr_gen_802_16e_v1_1
-- Compiling architecture behavioral of addr_gen_802_16e_v1_1
-- Compiling package addr_gen_802_16e_v1_1_comp
-- Loading package addr_gen_802_16e_v1_1_comp
-- Compiling entity addr_gen_802_16e_v1_1_xst
-- Compiling architecture behavioral of addr_gen_802_16e_v1_1_xst
-- Compiling package addr_gen_802_16e_v1_1_xst_comp
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling entity sdivider_v3_0
-- Compiling architecture behavioral of sdivider_v3_0
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-- Loading package std_logic_signed
-- Compiling package ddc_v1_0_pack
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-- Compiling package ddc_v1_0_comp
-- Compiling package tcc_enc_802_16e_v2_0_comp
-- Loading package tcc_enc_802_16e_v2_0_comp
-- Compiling entity tcc_enc_802_16e_v2_0_xst
-- Compiling architecture behavioral of tcc_enc_802_16e_v2_0_xst
-- Compiling package tcc_enc_802_16e_v2_0_xst_comp
-- Compiling package addr_gen_3gpp_top_level_pkg_v4_1
-- Loading package addr_gen_3gpp_top_level_pkg_v4_1
-- Compiling package addr_gen_3gpp_v4_1_xst_comp
-- Compiling package body addr_gen_3gpp_v4_1_xst_comp
-- Loading package addr_gen_3gpp_v4_1_xst_comp
-- Compiling package addr_gen_3gpp_v4_1_comp
-- Compiling package body addr_gen_3gpp_v4_1_comp
-- Loading package addr_gen_3gpp_v4_1_comp
-- Compiling package tcc_encoder_3gpp2_v2_0_xst_comp
-- Compiling package tcc_encoder_3gpp2_v2_0_comp
-- Loading package numeric_std
-- Loading package mem_init_file_pack_v5_0
-- Loading package prims_constants_v4_0
-- Loading package prims_utils_v4_0
-- Loading package c_reg_fd_v4_0_comp
-- Compiling entity c_shift_ram_v4_0
-- Compiling architecture behavioral of c_shift_ram_v4_0
-- Compiling package c_shift_ram_v4_0_comp
-- Compiling entity c_twos_comp_v4_0
-- Compiling architecture behavioral of c_twos_comp_v4_0
-- Compiling package c_twos_comp_v4_0_comp
-- Loading package prims_constants_v5_0
-- Compiling package mult_const_pkg_v4_0
-- Loading package mult_const_pkg_v4_0
-- Compiling package parm_v4_0_services
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-- Loading package parm_v4_0_services
-- Loading package parm_v4_0_services
-- Compiling package ccm_v4_0_services
-- Compiling package body ccm_v4_0_services
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-- Compiling package sqm_v4_0_services
-- Compiling package body sqm_v4_0_services
-- Loading package sqm_v4_0_services
-- Loading package sqm_v4_0_services
-- Compiling package mult_gen_v4_0_services
-- Compiling package body mult_gen_v4_0_services
-- Loading package mult_gen_v4_0_services
-- Loading package mult_gen_v4_0_services
-- Compiling package mult_pkg_v4_0
-- Compiling package body mult_pkg_v4_0
-- Loading package mult_pkg_v4_0
-- Loading package mult_pkg_v4_0
-- Compiling entity mult_gen_v4_0
-- Compiling architecture behavioral of mult_gen_v4_0
-- Compiling package mult_gen_v4_0_comp
-- Loading package prims_utils_v5_0
-- Loading package c_reg_fd_v5_0_comp
-- Compiling entity c_mux_bit_v5_0
-- Compiling architecture behavioral of c_mux_bit_v5_0
-- Compiling package c_mux_bit_v5_0_comp
-- Loading package c_mux_bit_v5_0_comp
-- Compiling entity c_shift_fd_v5_0
-- Compiling architecture behavioral of c_shift_fd_v5_0
-- Compiling package c_shift_fd_v5_0_comp
-- Loading package math_real
-- Compiling package c_sin_cos_v4_0_pack
-- Compiling package body c_sin_cos_v4_0_pack
-- Loading package c_sin_cos_v4_0_pack
-- Compiling entity pipe_bhv_v4_0
-- Compiling architecture behavioral of pipe_bhv_v4_0
-- Compiling package pipe_bhv_v4_0_comp
-- Loading package c_shift_fd_v5_0_comp
-- Loading package c_sin_cos_v4_0_pack
-- Loading package pipe_bhv_v4_0_comp
-- Compiling entity c_sin_cos_v4_0
-- Compiling architecture behavioral of c_sin_cos_v4_0
-- Compiling package c_sin_cos_v4_0_comp
-- Compiling package vfft32_pkg_v3
-- Compiling package body vfft32_pkg_v3
-- Loading package vfft32_pkg_v3
-- Loading package vfft32_pkg_v3
-- Compiling package vfft32_comps_v3
-- Loading package vfft32_comps_v3
-- Compiling entity flip_flop_v3
-- Compiling architecture behavioral of flip_flop_v3
-- Compiling entity flip_flop_sclr_v3
-- Compiling architecture behavioral of flip_flop_sclr_v3
-- Compiling entity flip_flop_sclr_sset_v3
-- Compiling architecture behavioral of flip_flop_sclr_sset_v3
-- Compiling entity flip_flop_ainit_sclr_v3
-- Compiling architecture behavioral of flip_flop_ainit_sclr_v3
-- Compiling entity state_machine_v3
-- Compiling architecture behavioral of state_machine_v3
-- Loading package c_gate_bit_v4_0_comp
-- Compiling entity or_a_b_32_v3
-- Compiling architecture behavioral of or_a_b_32_v3
-- Compiling entity or_a_b_c_32_v3
-- Compiling architecture behavioral of or_a_b_c_32_v3
-- Compiling entity xor_a_b_32_v3
-- Compiling architecture behavioral of xor_a_b_32_v3
-- Compiling entity nand_a_b_32_v3
-- Compiling architecture behavioral of nand_a_b_32_v3
-- Compiling entity and_a_b_32_v3
-- Compiling architecture behavioral of and_a_b_32_v3
-- Compiling entity and_a_notb_32_v3
-- Compiling architecture behavioral of and_a_notb_32_v3
-- Compiling entity srflop_v3
-- Compiling architecture behavioral of srflop_v3
-- Loading package c_shift_ram_v4_0_comp
-- Compiling entity delay_wrapper_v3
-- Compiling architecture behavioral of delay_wrapper_v3
-- Loading package c_mux_bus_v4_0_comp
-- Loading package c_counter_binary_v4_0_comp
-- Compiling entity hand_shaking_v3
-- Compiling architecture behavioral of hand_shaking_v3
-- Loading package c_mux_bit_v4_0_comp
-- Compiling entity addr_gen_v3
-- Compiling architecture behavioral of addr_gen_v3
-- Loading package c_dist_mem_v5_0_comp
-- Compiling entity dmem_wkg_r_i_v3
-- Compiling architecture behavioral of dmem_wkg_r_i_v3
-- Compiling entity mem_address_v3
-- Compiling architecture behavioral of mem_address_v3
-- Loading package c_compare_v4_0_comp
-- Compiling entity mem_ctrl_v3
-- Compiling architecture behavioral of mem_ctrl_v3
-- Loading package blkmemdp_pkg_v4_0
-- Loading package blkmemdp_v4_0_comp
-- Compiling entity mem_wkg_r_i_v3
-- Compiling architecture behavioral of mem_wkg_r_i_v3
-- Compiling entity working_memory_v3
-- Compiling architecture behavioral of working_memory_v3
-- Loading package c_twos_comp_v4_0_comp
-- Compiling entity conj_reg_v3
-- Compiling architecture behavioral of conj_reg_v3
-- Compiling entity input_working_result_memory_v3
-- Compiling architecture behavioral of input_working_result_memory_v3
-- Loading package mult_gen_v4_0_comp
-- Loading package c_addsub_v4_0_comp
-- Compiling entity complex_mult_v3
-- Compiling architecture behavioral of complex_mult_v3
-- Compiling entity complex_reg_conj_v3
-- Compiling architecture behavioral of complex_reg_conj_v3
-- Compiling entity butterfly_v3
-- Compiling architecture behavioral of butterfly_v3
-- Compiling entity butterfly_32_v3
-- Compiling architecture behavioral of butterfly_32_v3
-- Compiling entity bflyw0_v3
-- Compiling architecture behavioral of bflyw0_v3
-- Compiling entity bflyw_j_v3
-- Compiling architecture behavioral of bflyw_j_v3
-- Compiling entity fft4_32_v3
-- Compiling architecture behavioral of fft4_32_v3
-- Compiling entity bfly_buffer_v3
-- Compiling architecture behavioral of bfly_buffer_v3
-- Compiling entity bfly_buf_fft_v3
-- Compiling architecture behavioral of bfly_buf_fft_v3
-- Compiling entity phase_factor_adgen_v3
-- Compiling architecture behavioral of phase_factor_adgen_v3
-- Loading package c_sin_cos_v4_0_comp
-- Compiling entity phase_factors_v3
-- Compiling architecture behavioral of phase_factors_v3
-- Compiling entity result_memory_v3
-- Compiling architecture behavioral of result_memory_v3
-- Compiling entity vfft32_v3_0
-- Compiling architecture behavioral of vfft32_v3_0
-- Compiling package vfft32_v3_0_comp
-- Loading package prims_constants_v7_0
-- Compiling package mult_const_pkg_v7_0
-- Loading package mult_const_pkg_v7_0
-- Compiling package parm_v7_0_services
-- Compiling package body parm_v7_0_services
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-- Compiling package ccm_v7_0_services
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-- Loading package ccm_v7_0_services
-- Compiling package sqm_v7_0_services
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-- Loading package sqm_v7_0_services
-- Compiling package mult_gen_v7_0_services
-- Compiling package body mult_gen_v7_0_services
-- Loading package mult_gen_v7_0_services
-- Compiling package iputils_std_logic_signed
-- Compiling package body iputils_std_logic_signed
-- Loading package iputils_std_logic_signed
-- Compiling entity cordic_v3_0
-- Loading package mult_gen_v7_0_services
-- Compiling package cordic_pack_beh
-- Compiling package body cordic_pack_beh
-- Loading package cordic_pack_beh
-- Loading package cordic_pack_beh
-- Loading package iputils_std_logic_signed
-- Compiling architecture behavioral of cordic_v3_0
-- Compiling package cordic_v3_0_comp
-- Compiling package dafir_pack_v7_0
-- Loading package dafir_pack_v7_0
-- Compiling entity c_da_fir_v7_0
-- Compiling architecture behavioral of c_da_fir_v7_0
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(695231):     WHILE (NOT(endfile(coeffile)) AND (lines <= number_of_values)) LOOP
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(695231): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(695232):       readline(coeffile, hexline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(695232): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(695269):     filter_coefficients := read_coefficients(filename, orig_number_of_taps, nrz_coef );
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(695269): (vcom-1284) Cannot call side-effect function "read_coefficients" from pure function "assign_filter_coefficients".
-- Compiling package c_da_fir_v7_0_comp
-- Compiling package tcc_decoder_3gpp_v3_1_comp
-- Compiling package body tcc_decoder_3gpp_v3_1_comp
-- Loading package tcc_decoder_3gpp_v3_1_comp
-- Compiling package tcc_decoder_3gpp_v3_1_xst_comp
-- Compiling package body tcc_decoder_3gpp_v3_1_xst_comp
-- Loading package tcc_decoder_3gpp_v3_1_xst_comp
-- Compiling package viterbi_v6_0_xst_comp
-- Compiling package viterbi_v6_0_comp
-- Compiling package mult_pkg_v7_0
-- Compiling package body mult_pkg_v7_0
-- Loading package mult_pkg_v7_0
-- Loading package mult_pkg_v7_0
-- Compiling entity mult_gen_v7_0_non_seq
-- Compiling architecture behavioral of mult_gen_v7_0_non_seq
-- Compiling package mult_gen_v7_0_non_seq_comp
-- Loading package mult_gen_v7_0_non_seq_comp
-- Loading package c_reg_fd_v7_0_comp
-- Compiling entity mult_gen_v7_0_seq
-- Compiling architecture behavioral of mult_gen_v7_0_seq
-- Compiling package mult_gen_v7_0_seq_comp
-- Loading package mult_gen_v7_0_seq_comp
-- Compiling entity mult_gen_v7_0
-- Compiling architecture behavioral of mult_gen_v7_0
-- Compiling package mult_gen_v7_0_comp
-- Loading package prims_utils_v7_0
-- Compiling entity c_gate_bus_v7_0
-- Compiling architecture behavioral of c_gate_bus_v7_0
-- Compiling package c_gate_bus_v7_0_comp
-- Compiling entity c_gate_bit_bus_v7_0
-- Compiling architecture behavioral of c_gate_bit_bus_v7_0
-- Compiling package c_gate_bit_bus_v7_0_comp
-- Compiling entity c_twos_comp_v7_0
-- Compiling architecture behavioral of c_twos_comp_v7_0
-- Compiling package c_twos_comp_v7_0_comp
-- Loading package iputils_mem87
-- Compiling entity c_shift_ram_v7_0
-- Compiling architecture behavioral of c_shift_ram_v7_0
-- Compiling package c_shift_ram_v7_0_comp
-- Compiling entity c_mux_bit_v7_0
-- Compiling architecture behavioral of c_mux_bit_v7_0
-- Compiling package c_mux_bit_v7_0_comp
-- Loading package c_mux_bit_v7_0_comp
-- Compiling entity c_shift_fd_v7_0
-- Compiling architecture behavioral of c_shift_fd_v7_0
-- Compiling package c_shift_fd_v7_0_comp
-- Compiling package c_sin_cos_v5_0_pack
-- Compiling package body c_sin_cos_v5_0_pack
-- Loading package c_sin_cos_v5_0_pack
-- Compiling entity pipe_bhv_v5_0
-- Compiling architecture behavioral of pipe_bhv_v5_0
-- Compiling package pipe_bhv_v5_0_comp
-- Loading package c_shift_fd_v7_0_comp
-- Loading package c_sin_cos_v5_0_pack
-- Loading package pipe_bhv_v5_0_comp
-- Compiling entity c_sin_cos_v5_0
-- Compiling architecture behavioral of c_sin_cos_v5_0
-- Loading entity c_shift_fd_v7_0
-- Loading entity pipe_bhv_v5_0
-- Loading entity c_reg_fd_v7_0
-- Compiling package c_sin_cos_v5_0_comp
-- Compiling package blkmemdp_pkg_v6_0
-- Compiling package body blkmemdp_pkg_v6_0
-- Loading package blkmemdp_pkg_v6_0
-- Compiling package blkmemdp_mem_init_file_pack_v6_0
-- Compiling package body blkmemdp_mem_init_file_pack_v6_0
-- Loading package blkmemdp_mem_init_file_pack_v6_0
-- Loading package vital_timing
-- Loading package blkmemdp_mem_init_file_pack_v6_0
-- Loading package blkmemdp_pkg_v6_0
-- Compiling entity blkmemdp_v6_0
-- Compiling architecture behavioral of blkmemdp_v6_0
-- Compiling package blkmemdp_v6_0_comp
-- Loading package c_addsub_v7_0_comp
-- Compiling entity c_accum_v7_0
-- Compiling architecture behavioral of c_accum_v7_0
-- Compiling package c_accum_v7_0_comp
-- Compiling entity c_dist_mem_v7_0
-- Compiling architecture behavioral of c_dist_mem_v7_0
-- Compiling package c_dist_mem_v7_0_comp
-- Compiling package cmpy_pkg
-- Compiling package body cmpy_pkg
-- Loading package cmpy_pkg
-- Loading package cmpy_pkg
-- Compiling entity cmpy_v1_0
-- Compiling architecture behavioral of cmpy_v1_0
-- Compiling package cmpy_v1_0_comp
-- Loading package c_mux_bus_v7_0_comp
-- Loading package mult_gen_v7_0_comp
-- Loading package c_gate_bus_v7_0_comp
-- Loading package prims_comps_v7_0
-- Loading package c_compare_v7_0_comp
-- Loading package c_gate_bit_v7_0_comp
-- Loading package c_gate_bit_bus_v7_0_comp
-- Loading package c_twos_comp_v7_0_comp
-- Loading package c_shift_ram_v7_0_comp
-- Loading package c_sin_cos_v5_0_comp
-- Loading package blkmemdp_v6_0_comp
-- Loading package c_accum_v7_0_comp
-- Loading package c_dist_mem_v7_0_comp
-- Loading package cmpy_v1_0_comp
-- Loading package family
-- Compiling package fft30_synth_pkg
-- Compiling package body fft30_synth_pkg
-- Loading package fft30_synth_pkg
-- Compiling package fft30_pkg
-- Compiling package body fft30_pkg
-- Loading package fft30_pkg
-- Compiling package fft30_bb_comps
-- Compiling package fft30_synth_comps
-- Compiling package fft30_comps
-- Compiling entity fft30_equ_rtl
-- Compiling architecture xilinx of fft30_equ_rtl
-- Compiling entity fft30_fde_rtl
-- Compiling architecture xilinx of fft30_fde_rtl
-- Compiling entity fft30_fdre_rtl
-- Compiling architecture xilinx of fft30_fdre_rtl
-- Loading package fft30_synth_comps
-- Compiling entity fft30_cnt_tc_rtl
-- Compiling architecture xilinx of fft30_cnt_tc_rtl
-- Compiling entity fft30_cnt_tc_rtl_a
-- Compiling architecture xilinx of fft30_cnt_tc_rtl_a
-- Compiling entity fft30_r22_cnt_ctrl
-- Compiling architecture xilinx of fft30_r22_cnt_ctrl
-- Compiling entity fft30_reg_rs_rtl
-- Compiling architecture xilinx of fft30_reg_rs_rtl
-- Loading package vcomponents
-- Compiling entity fft30_reg_re_rtl
-- Compiling architecture xilinx of fft30_reg_re_rtl
-- Loading package fft30_synth_pkg
-- Compiling entity fft30_flow_control_a
-- Compiling architecture xilinx of fft30_flow_control_a
-- Compiling entity fft30_flow_control_b
-- Compiling architecture xilinx of fft30_flow_control_b
-- Compiling entity fft30_flow_control_c
-- Compiling architecture xilinx of fft30_flow_control_c
-- Compiling entity fft30_r22_flow_ctrl
-- Compiling architecture xilinx of fft30_r22_flow_ctrl
-- Compiling entity fft30_fde
-- Compiling architecture xilinx of fft30_fde
-- Compiling entity fft30_reg_fde
-- Compiling architecture xilinx of fft30_reg_fde
-- Compiling entity fft30_reg_fde_sclr
-- Compiling architecture xilinx of fft30_reg_fde_sclr
-- Compiling entity fft30_reg_fde_sr_1
-- Compiling architecture xilinx of fft30_reg_fde_sr_1
-- Compiling entity fft30_mux_bus
-- Compiling architecture xilinx of fft30_mux_bus
-- Compiling entity fft30_mux_bus_sclr
-- Compiling architecture xilinx of fft30_mux_bus_sclr
-- Compiling entity fft30_mux_bus2
-- Compiling architecture xilinx of fft30_mux_bus2
-- Compiling entity fft30_mux_bus2_1
-- Compiling architecture xilinx of fft30_mux_bus2_1
-- Compiling entity fft30_mux_bus16
-- Compiling architecture xilinx of fft30_mux_bus16
-- Compiling entity fft30_mux_bus8
-- Compiling architecture xilinx of fft30_mux_bus8
-- Compiling entity fft30_twos_comp
-- Compiling architecture xilinx of fft30_twos_comp
-- Compiling entity fft30_adder
-- Compiling architecture xilinx of fft30_adder
-- Compiling entity fft30_adder_bypass
-- Compiling architecture xilinx of fft30_adder_bypass
-- Compiling entity fft30_subtracter
-- Compiling architecture xilinx of fft30_subtracter
-- Compiling entity fft30_sub_byp
-- Compiling architecture xilinx of fft30_sub_byp
-- Compiling entity fft30_sub_byp_j
-- Compiling architecture xilinx of fft30_sub_byp_j
-- Loading package fft30_comps
-- Compiling entity fft30_butterfly
-- Compiling architecture xilinx of fft30_butterfly
-- Compiling entity fft30_bfly_byp
-- Compiling architecture xilinx of fft30_bfly_byp
-- Compiling entity fft30_butterfly_j
-- Compiling architecture xilinx of fft30_butterfly_j
-- Compiling entity fft30_bfly_byp_j
-- Compiling architecture xilinx of fft30_bfly_byp_j
-- Loading package fft30_pkg
-- Compiling entity fft30_mult
-- Compiling architecture xilinx of fft30_mult
-- Compiling entity fft30_shift_ram
-- Compiling architecture xilinx of fft30_shift_ram
-- Compiling entity fft30_complex_mult3
-- Compiling architecture xilinx of fft30_complex_mult3
-- Compiling entity fft30_complex_mult4
-- Compiling architecture xilinx of fft30_complex_mult4
-- Compiling entity fft30_dragonfly
-- Compiling architecture xilinx of fft30_dragonfly
-- Compiling entity fft30_dfly_byp
-- Compiling architecture xilinx of fft30_dfly_byp
-- Compiling entity fft30_and2
-- Compiling architecture xilinx of fft30_and2
-- Compiling entity fft30_and_gate
-- Compiling architecture xilinx of fft30_and_gate
-- Compiling entity fft30_and_bus_gate
-- Compiling architecture xilinx of fft30_and_bus_gate
-- Compiling entity fft30_shift_ram_1
-- Compiling architecture xilinx of fft30_shift_ram_1
-- Compiling entity fft30_shift_ram_sclr
-- Compiling architecture xilinx of fft30_shift_ram_sclr
-- Compiling entity fft30_shift_ram_1_sclr
-- Compiling architecture xilinx of fft30_shift_ram_1_sclr
-- Compiling entity fft30_c_lut
-- Compiling architecture xilinx of fft30_c_lut
-- Compiling entity fft30_c_lut_reg
-- Compiling architecture xilinx of fft30_c_lut_reg
-- Compiling entity fft30_c_lut_reg_sclr
-- Compiling architecture xilinx of fft30_c_lut_reg_sclr
-- Compiling entity fft30_compare
-- Compiling architecture xilinx of fft30_compare
-- Compiling entity fft30_xor_bit_gate
-- Compiling architecture xilinx of fft30_xor_bit_gate
-- Compiling entity fft30_xnor_bit_gate
-- Compiling architecture xilinx of fft30_xnor_bit_gate
-- Compiling entity fft30_io_addr_gen
-- Compiling architecture xilinx of fft30_io_addr_gen
-- Compiling entity fft30_out_addr_gen
-- Compiling architecture xilinx of fft30_out_addr_gen
-- Compiling entity fft30_out_addr_gen_b
-- Compiling architecture xilinx of fft30_out_addr_gen_b
-- Compiling entity fft30_rw_addr_gen
-- Compiling architecture xilinx of fft30_rw_addr_gen
-- Compiling entity fft30_rw_addr_gen_b
-- Compiling architecture xilinx of fft30_rw_addr_gen_b
-- Compiling entity fft30_tw_gen_p2
-- Compiling architecture xilinx of fft30_tw_gen_p2
-- Compiling entity fft30_tw_gen_p4
-- Compiling architecture xilinx of fft30_tw_gen_p4
-- Compiling entity fft30_in_switch4
-- Compiling architecture xilinx of fft30_in_switch4
-- Compiling entity fft30_tw_addr_gen
-- Compiling architecture xilinx of fft30_tw_addr_gen
-- Compiling entity fft30_out_switch4
-- Compiling architecture xilinx of fft30_out_switch4
-- Compiling entity fft30_max2_2
-- Compiling architecture xilinx of fft30_max2_2
-- Compiling entity fft30_comp8
-- Compiling architecture xilinx of fft30_comp8
-- Compiling entity fft30_range_r4
-- Compiling architecture xilinx of fft30_range_r4
-- Compiling entity fft30_range_r2
-- Compiling architecture xilinx of fft30_range_r2
-- Compiling entity fft30_in_ranger
-- Compiling architecture xilinx of fft30_in_ranger
-- Compiling entity fft30_r4_ranger
-- Compiling architecture xilinx of fft30_r4_ranger
-- Compiling entity fft30_arith_shift3
-- Compiling architecture xilinx of fft30_arith_shift3
-- Compiling entity fft30_arith_shift1
-- Compiling architecture xilinx of fft30_arith_shift1
-- Compiling entity fft30_overflow_gen
-- Compiling architecture xilinx of fft30_overflow_gen
-- Compiling entity fft30_unbiased_round
-- Compiling architecture xilinx of fft30_unbiased_round
-- Compiling entity fft30_pe4
-- Compiling architecture xilinx of fft30_pe4
-- Compiling entity fft30_sin_cos
-- Compiling architecture xilinx of fft30_sin_cos
-- Compiling entity fft30_dpm
-- Compiling architecture xilinx of fft30_dpm
-- Compiling entity fft30_dist_mem
-- Compiling architecture xilinx of fft30_dist_mem
-- Compiling entity fft30_scale_logic
-- Compiling architecture xilinx of fft30_scale_logic
-- Compiling entity fft30_r2_in_addr
-- Compiling architecture xilinx of fft30_r2_in_addr
-- Compiling entity fft30_r2_ovflo_gen
-- Compiling architecture xilinx of fft30_r2_ovflo_gen
-- Compiling entity fft30_r2_pe
-- Compiling architecture xilinx of fft30_r2_pe
-- Compiling entity fft30_r2_ranger
-- Compiling architecture xilinx of fft30_r2_ranger
-- Compiling entity fft30_r2_rw_addr
-- Compiling architecture xilinx of fft30_r2_rw_addr
-- Compiling entity fft30_r2_tw_addr
-- Compiling architecture xilinx of fft30_r2_tw_addr
-- Compiling entity fft30_r22_cmplx_mult
-- Compiling architecture xilinx of fft30_r22_cmplx_mult
-- Compiling entity fft30_r22_bfly_byp
-- Compiling architecture xilinx of fft30_r22_bfly_byp
-- Compiling entity fft30_r22_memory
-- Compiling architecture xilinx of fft30_r22_memory
-- Compiling entity fft30_r22_tw_gen
-- Compiling architecture xilinx of fft30_r22_tw_gen
-- Compiling entity fft30_r22_ovflo
-- Compiling architecture xilinx of fft30_r22_ovflo
-- Compiling entity fft30_r22_bf1_last_even
-- Compiling architecture xilinx of fft30_r22_bf1_last_even
-- Compiling entity fft30_r22_bf1_last_odd
-- Compiling architecture xilinx of fft30_r22_bf1_last_odd
-- Compiling entity fft30_r22_bf1_penult_odd
-- Compiling architecture xilinx of fft30_r22_bf1_penult_odd
-- Compiling entity fft30_r22_bf1_sp
-- Compiling architecture xilinx of fft30_r22_bf1_sp
-- Compiling entity fft30_r22_bf1
-- Compiling architecture xilinx of fft30_r22_bf1
-- Compiling entity fft30_r22_bf2_last_even
-- Compiling architecture xilinx of fft30_r22_bf2_last_even
-- Compiling entity fft30_r22_bf2_penult_even
-- Compiling architecture xilinx of fft30_r22_bf2_penult_even
-- Compiling entity fft30_r22_bf2_penult_odd
-- Compiling architecture xilinx of fft30_r22_bf2_penult_odd
-- Compiling entity fft30_r22_bf2_sp
-- Compiling architecture xilinx of fft30_r22_bf2_sp
-- Compiling entity fft30_r22_bf2
-- Compiling architecture xilinx of fft30_r22_bf2
-- Compiling entity fft30_r22_pe
-- Compiling architecture xilinx of fft30_r22_pe
-- Compiling entity fft30_r22_pe_last
-- Compiling architecture xilinx of fft30_r22_pe_last
-- Loading package fft30_bb_comps
-- Compiling entity xfft_v3_0_a
-- Compiling architecture xilinx of xfft_v3_0_a
-- Compiling entity xfft_v3_0_b
-- Compiling architecture xilinx of xfft_v3_0_b
-- Compiling entity xfft_v3_0_c
-- Compiling architecture xilinx of xfft_v3_0_c
-- Compiling entity xfft_v3_0_d
-- Compiling architecture xilinx of xfft_v3_0_d
-- Compiling entity xfft_v3_0
-- Compiling architecture behavioral of xfft_v3_0
-- Compiling package xfft_v3_0_comp
-- Compiling package body xfft_v3_0_comp
-- Loading package xfft_v3_0_comp
-- Compiling package dvb_s2_fec_encoder_v1_3_xst_comp
-- Compiling entity dvb_s2_fec_encoder_v1_3
-- Compiling architecture behavioral of dvb_s2_fec_encoder_v1_3
-- Compiling package dvb_s2_fec_encoder_v1_3_comp
-- Compiling package tcc_decoder_toplevel_pkg
-- Compiling package body tcc_decoder_toplevel_pkg
-- Loading package tcc_decoder_toplevel_pkg
-- Loading package tcc_decoder_toplevel_pkg
-- Compiling entity tcc_decoder_v2_1
-- Compiling architecture behavioral of tcc_decoder_v2_1
-- Compiling package tcc_decoder_v2_1_comp
-- Loading package tcc_decoder_v2_1_comp
-- Compiling entity tcc_decoder_v2_1_xst
-- Compiling architecture behavioral of tcc_decoder_v2_1_xst
-- Compiling package tcc_decoder_v2_1_xst_comp
-- Compiling package convolution_v5_0_xst_comp
-- Loading package prims_constants_v8_0
-- Compiling package convolution_pack_v5_0
-- Compiling package body convolution_pack_v5_0
-- Loading package convolution_pack_v5_0
-- Loading package convolution_pack_v5_0
-- Compiling entity convolution_v5_0
-- Compiling architecture behavioral of convolution_v5_0
-- Compiling package convolution_v5_0_comp
-- Compiling package mac_fir_v5_0_comp
-- Compiling package c_sin_cos_v5_1_pack
-- Compiling package body c_sin_cos_v5_1_pack
-- Loading package c_sin_cos_v5_1_pack
-- Compiling entity pipe_bhv_v5_1
-- Compiling architecture behavioral of pipe_bhv_v5_1
-- Compiling package pipe_bhv_v5_1_comp
-- Loading package c_sin_cos_v5_1_pack
-- Loading package pipe_bhv_v5_1_comp
-- Compiling entity c_sin_cos_v5_1
-- Compiling architecture behavioral of c_sin_cos_v5_1
-- Loading entity pipe_bhv_v5_1
-- Compiling package c_sin_cos_v5_1_comp
-- Compiling package dvb_s2_fec_encoder_v1_2_xst_comp
-- Compiling entity dvb_s2_fec_encoder_v1_2
-- Compiling architecture behavioral of dvb_s2_fec_encoder_v1_2
-- Compiling package dvb_s2_fec_encoder_v1_2_comp
-- Compiling package tcc_encoder_3gpp_v2_0_comp
-- Compiling package fir_compiler_v2_0_comp
-- Compiling package fir_compiler_v2_0_xst_comp
-- Compiling package floating_point_v1_0_consts
-- Loading package floating_point_v1_0_consts
-- Compiling package floating_point_pkg_v1_0
-- Compiling package body floating_point_pkg_v1_0
-- Loading package floating_point_pkg_v1_0
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(744508):   end function;
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(744508): Function 'flt_pt_get_embedded' may complete without a RETURN at line 744493.
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(744508): Function 'flt_pt_get_embedded' may complete without a RETURN at line 744503.
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(744526):   end function;
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(744526): Function 'flt_pt_get_usedsp48' may complete without a RETURN at line 744519.
-- Loading package floating_point_pkg_v1_0
-- Compiling entity flt_pt_operator
-- Compiling architecture behavioral of flt_pt_operator
-- Compiling entity floating_point_v1_0_xst
-- Compiling architecture behavioral of floating_point_v1_0_xst
-- Compiling package floating_point_v1_0_xst_comp
-- Loading package floating_point_v1_0_xst_comp
-- Compiling entity floating_point_v1_0
-- Compiling architecture behavioral of floating_point_v1_0
-- Compiling package floating_point_v1_0_comp
-- Loading package c_addsub_v5_0_comp
-- Compiling entity c_accum_v5_0
-- Compiling architecture behavioral of c_accum_v5_0
-- Compiling package c_accum_v5_0_comp
-- Compiling entity dither_v4_0
-- Compiling architecture rtl of dither_v4_0
-- Compiling package dither_v4_0_comp
-- Loading package dither_v4_0_comp
-- Compiling entity dither_add_v4_0
-- Compiling architecture structural of dither_add_v4_0
-- Loading entity dither_v4_0
-- Loading entity c_reg_fd_v5_0
-- Loading entity c_addsub_v5_0
-- Compiling package dither_add_v4_0_comp
-- Compiling package c_dds_v4_0_pack
-- Compiling package body c_dds_v4_0_pack
-- Loading package c_dds_v4_0_pack
-- Loading package c_accum_v5_0_comp
-- Loading package dither_add_v4_0_comp
-- Loading package c_dds_v4_0_pack
-- Compiling entity c_dds_v4_0
-- Compiling architecture behavioral of c_dds_v4_0
-- Loading entity c_accum_v5_0
-- Loading entity c_sin_cos_v4_0
-- Loading entity dither_add_v4_0
-- Compiling package dds_v4_0_comp
-- Loading package prims_constants_v2_0
-- Compiling package mac_v4_0_comp
-- Compiling package addr_gen_3gpp_top_level_pkg_v3_0
-- Loading package addr_gen_3gpp_top_level_pkg_v3_0
-- Compiling package addr_gen_3gpp_v3_0_xst_comp
-- Compiling package body addr_gen_3gpp_v3_0_xst_comp
-- Loading package addr_gen_3gpp_v3_0_xst_comp
-- Compiling package addr_gen_3gpp_v3_0_comp
-- Compiling package body addr_gen_3gpp_v3_0_comp
-- Loading package addr_gen_3gpp_v3_0_comp
-- Compiling entity addr_gen_802_16e_v2_0
-- Compiling architecture behavioral of addr_gen_802_16e_v2_0
-- Compiling package addr_gen_802_16e_v2_0_comp
-- Loading package addr_gen_802_16e_v2_0_comp
-- Compiling entity addr_gen_802_16e_v2_0_xst
-- Compiling architecture behavioral of addr_gen_802_16e_v2_0_xst
-- Compiling package addr_gen_802_16e_v2_0_xst_comp
-- Compiling package vfft_utils
-- Compiling entity xdsp_cnt10
-- Compiling architecture behv of xdsp_cnt10
-- Compiling entity xdsp_cnt11
-- Compiling architecture behv of xdsp_cnt11
-- Compiling entity xdsp_cnt12
-- Compiling architecture behv of xdsp_cnt12
-- Compiling entity xdsp_cnt2
-- Compiling architecture behv of xdsp_cnt2
-- Compiling entity xdsp_cnt4
-- Compiling architecture behv of xdsp_cnt4
-- Compiling entity xdsp_cnt5
-- Compiling architecture behv of xdsp_cnt5
-- Compiling entity xdsp_cnt8
-- Compiling architecture behv of xdsp_cnt8
-- Compiling entity xdsp_cnt9
-- Compiling architecture behv of xdsp_cnt9
-- Compiling entity xdsp_cos1024
-- Compiling architecture behv of xdsp_cos1024
-- Compiling entity xdsp_cos256
-- Compiling architecture behv of xdsp_cos256
-- Compiling entity xdsp_cos64
-- Compiling architecture behv of xdsp_cos64
-- Compiling entity xdsp_coss16
-- Compiling architecture behv of xdsp_coss16
-- Compiling entity xdsp_mul16x17
-- Compiling architecture behv of xdsp_mul16x17
-- Compiling entity xdsp_mul16x17z4
-- Compiling architecture behv of xdsp_mul16x17z4
-- Compiling entity xdsp_mux2w1
-- Compiling architecture mux1 of xdsp_mux2w1
-- Compiling entity xdsp_mux2w16
-- Compiling architecture behv of xdsp_mux2w16
-- Compiling entity xdsp_mux2w16r
-- Compiling architecture behv of xdsp_mux2w16r
-- Compiling entity xdsp_mux2w4
-- Compiling architecture behv of xdsp_mux2w4
-- Compiling entity xdsp_mux2w4r
-- Compiling architecture behv of xdsp_mux2w4r
-- Compiling entity xdsp_mux3w1
-- Compiling architecture mux1 of xdsp_mux3w1
-- Compiling entity xdsp_mux4w16
-- Compiling architecture behv of xdsp_mux4w16
-- Compiling entity xdsp_mux4w16r
-- Compiling architecture behv of xdsp_mux4w16r
-- Compiling entity xdsp_radd16
-- Compiling architecture behv of xdsp_radd16
-- Compiling entity xdsp_radd16c
-- Compiling architecture behv of xdsp_radd16c
-- Compiling entity xdsp_radd17
-- Compiling architecture behv of xdsp_radd17
-- Compiling entity xdsp_ramd16a4
-- Compiling architecture behv of xdsp_ramd16a4
-- Compiling entity xdsp_reg16
-- Compiling architecture behavioral of xdsp_reg16
-- Compiling entity xdsp_reg16b
-- Compiling architecture behavioral of xdsp_reg16b
-- Compiling entity xdsp_reg16l
-- Compiling architecture behavioral of xdsp_reg16l
-- Compiling entity xdsp_reg4
-- Compiling architecture behavioral of xdsp_reg4
-- Compiling entity xdsp_rsub16
-- Compiling architecture behv of xdsp_rsub16
-- Compiling entity xdsp_rsub16b
-- Compiling architecture behv of xdsp_rsub16b
-- Compiling entity xdsp_rsub16c
-- Compiling architecture behv of xdsp_rsub16c
-- Compiling entity xdsp_rsub17
-- Compiling architecture behv of xdsp_rsub17
-- Compiling entity xdsp_rsub17b
-- Compiling architecture behv of xdsp_rsub17b
-- Compiling entity xdsp_sin1024
-- Compiling architecture behv of xdsp_sin1024
-- Compiling entity xdsp_sin256
-- Compiling architecture behv of xdsp_sin256
-- Compiling entity xdsp_sin64
-- Compiling architecture behv of xdsp_sin64
-- Compiling entity xdsp_sinn16
-- Compiling architecture behv of xdsp_sinn16
-- Compiling entity xdsp_tcompw16
-- Compiling architecture behv of xdsp_tcompw16
-- Compiling entity xdsp_tcompw16b
-- Compiling architecture behv of xdsp_tcompw16b
-- Compiling entity xdsp_tcompw17
-- Compiling architecture behv of xdsp_tcompw17
-- Compiling entity xdsp_triginv
-- Compiling architecture behv of xdsp_triginv
-- Compiling package fft_defsx_1024
-- Loading package fft_defsx_1024
-- Compiling entity cmplx_reg16_conj
-- Compiling architecture struct of cmplx_reg16_conj
-- Compiling entity cmplx_reg16_conjb
-- Compiling architecture struct of cmplx_reg16_conjb
-- Compiling entity cmplx_reg16_conjc
-- Compiling architecture struct of cmplx_reg16_conjc
-- Compiling entity state_mach
-- Compiling architecture behavioral of state_mach
-- Compiling entity fflce
-- Compiling architecture fflce_arch of fflce
-- Compiling entity ffrce
-- Compiling architecture ffrce_arch of ffrce
-- Compiling entity z19w1
-- Compiling architecture z19w1_arch of z19w1
-- Compiling entity z20w1
-- Compiling architecture struct of z20w1
-- Compiling entity z47w1
-- Compiling architecture struct of z47w1
-- Compiling entity z49w1
-- Compiling architecture struct of z49w1
-- Compiling entity z17w1
-- Compiling architecture struct of z17w1
-- Compiling entity xmul16x17
-- Compiling architecture struct of xmul16x17
-- Compiling entity shift_reg2b
-- Compiling architecture shift_reg2b_arch of shift_reg2b
-- Compiling entity xmux4w16r
-- Compiling architecture behv of xmux4w16r
-- Compiling entity xmux4w16rb
-- Compiling architecture behv of xmux4w16rb
-- Compiling entity xmux2w16r
-- Compiling architecture struct of xmux2w16r
-- Compiling entity bflyw0_16
-- Compiling architecture struct of bflyw0_16
-- Compiling entity bflywj_16
-- Compiling architecture struct of bflywj_16
-- Compiling entity bflyw0_17
-- Compiling architecture struct of bflyw0_17
-- Compiling entity fft4
-- Compiling architecture struct of fft4
-- Compiling entity dragonfly_1024
-- Compiling architecture struct of dragonfly_1024
-- Compiling entity phase_agen_1024
-- Compiling architecture phase_agen_arch of phase_agen_1024
-- Compiling entity phase_factors_1024
-- Compiling architecture phase_factors_arch of phase_factors_1024
-- Compiling entity fft_dbl_bufr_1024
-- Compiling architecture struct of fft_dbl_bufr_1024
-- Compiling entity fft4_engine
-- Compiling architecture struct of fft4_engine
-- Compiling entity index_map_1024
-- Compiling architecture behv of index_map_1024
-- Compiling entity fft_cntrlx_1024
-- Compiling architecture behv of fft_cntrlx_1024
-- Compiling entity fft_rd_agenx_1024
-- Compiling architecture fft_rd_agen1 of fft_rd_agenx_1024
-- Compiling entity fft_wr_agenx_1024
-- Compiling architecture fft_wr_agen1 of fft_wr_agenx_1024
-- Compiling package fft_defs_64
-- Compiling entity z16w1
-- Compiling architecture struct of z16w1
-- Compiling entity z18w1
-- Compiling architecture struct of z18w1
-- Compiling entity xmul16x17z
-- Compiling architecture struct of xmul16x17z
-- Compiling entity xmux2w16
-- Compiling architecture struct of xmux2w16
-- Compiling entity xmux4w16
-- Compiling architecture struct of xmux4w16
-- Loading package fft_defs_64
-- Compiling entity dragonfly_64
-- Compiling architecture struct of dragonfly_64
-- Compiling entity fft_rd_agen_64
-- Compiling architecture struct of fft_rd_agen_64
-- Compiling entity fft_wr_agen_64
-- Compiling architecture struct of fft_wr_agen_64
-- Compiling entity phase_agen_64
-- Compiling architecture behv of phase_agen_64
-- Compiling entity fft_cntrl_64
-- Compiling architecture virtex_fft_cntrl of fft_cntrl_64
-- Compiling entity phase_factors_64
-- Compiling architecture phase_factors_arch of phase_factors_64
-- Compiling package fft_defsx_256
-- Compiling entity dragonfly_256
-- Compiling architecture struct of dragonfly_256
-- Loading package fft_defsx_256
-- Compiling entity phase_agen_256
-- Compiling architecture phase_agen_arch of phase_agen_256
-- Compiling entity phase_factors_256
-- Compiling architecture phase_factors_arch of phase_factors_256
-- Compiling entity fft_dbl_bufr
-- Compiling architecture struct of fft_dbl_bufr
-- Compiling entity index_map_256
-- Compiling architecture behv of index_map_256
-- Compiling entity fft_cntrlx_256
-- Compiling architecture behv of fft_cntrlx_256
-- Compiling entity fft_rd_agenx_256
-- Compiling architecture fft_rd_agen_256 of fft_rd_agenx_256
-- Compiling entity fft_wr_agenx_256
-- Compiling architecture fft_wr_agen_256 of fft_wr_agenx_256
-- Compiling package fft_defs_16
-- Compiling entity z4w1
-- Compiling architecture struct of z4w1
-- Compiling entity z36w1
-- Compiling architecture struct of z36w1
-- Compiling entity z46w1
-- Compiling architecture struct of z46w1
-- Compiling entity xmux4w16br
-- Compiling architecture behv of xmux4w16br
-- Loading package fft_defs_16
-- Compiling entity fft4_16
-- Compiling architecture struct of fft4_16
-- Compiling entity fft4b
-- Compiling architecture struct of fft4b
-- Compiling entity dragonfly_16
-- Compiling architecture struct of dragonfly_16
-- Compiling entity input_dbl_bufr
-- Compiling architecture struct of input_dbl_bufr
-- Compiling entity fft_dbl_bufr_16
-- Compiling architecture struct of fft_dbl_bufr_16
-- Compiling entity bitrev_bufr
-- Compiling architecture struct of bitrev_bufr
-- Compiling entity fft_cntrl_16
-- Compiling architecture virtex_fft_cntrl of fft_cntrl_16
-- Loading package vfft_utils
-- Compiling entity vfft256
-- Compiling architecture behavioral of vfft256
-- Compiling package vfft256_comp
-- Compiling entity vfft16
-- Compiling architecture behavioral of vfft16
-- Compiling package vfft16_comp
-- Compiling entity vfft1024
-- Compiling architecture behavioral of vfft1024
-- Compiling package vfft1024_comp
-- Compiling entity vfft64
-- Compiling architecture behavioral of vfft64
-- Compiling package vfft64_comp
-- Compiling package viterbi_pack_v4
-- Compiling package body viterbi_pack_v4
-- Loading package viterbi_pack_v4
-- Loading package viterbi_pack_v4
-- Compiling entity viterbi_v4_0
-- Compiling architecture behavioral of viterbi_v4_0
-- Compiling package viterbi_v4_0_comp
-- Compiling package sid_const_pkg_behav_v4_0
-- Compiling package sid_mif_pkg_behav_v4_0
-- Compiling package body sid_mif_pkg_behav_v4_0
-- Loading package sid_mif_pkg_behav_v4_0
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(769139): :=0;IO0OOOI1IIIlIOIIOO0Il00I1lOOlIIIII:=0;WHILE(NOT(ENDFILE(MEMINITFILE))AND(IOl1I1O0IIO001llOlll1I1lOI1l0IIIII<IOl0I10010lIIIl000I1O1IO1IlOIIIIII))LOOP READLINE(MEMINITFILE,IIl1O1I0001l1001OllOOII0I10l1IIIII);READ(IIl1O1I0001l1001OllOOII0I10l1IIIII,IOl1Ol11IlIl0110l0OOll000lI11IIIII,
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(769139): (vcom-1283) Cannot reference file "meminitfile" inside pure function "iooiooi00l1oooli1ooo0i00ol0iliiiii".
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(769139): (vcom-1283) Cannot reference file "meminitfile" inside pure function "iooiooi00l1oooli1ooo0i00ol0iliiiii".
-- Loading package sid_const_pkg_behav_v4_0
-- Loading package sid_mif_pkg_behav_v4_0
-- Compiling package sid_pkg_behav_v4_0
-- Compiling package body sid_pkg_behav_v4_0
-- Loading package sid_pkg_behav_v4_0
-- Loading package sid_pkg_behav_v4_0
-- Compiling entity sid_bhv_forney_v4_0
-- Compiling architecture behavioral of sid_bhv_forney_v4_0
-- Compiling entity sid_bhv_rectangular_block_v4_0
-- Compiling architecture behavioral of sid_bhv_rectangular_block_v4_0
-- Compiling entity sid_v4_0
-- Compiling architecture behavioral of sid_v4_0
-- Compiling package sid_v4_0_comp
-- Compiling package body sid_v4_0_comp
-- Loading package sid_v4_0_comp
-- Loading package prims_constants_v6_0
-- Compiling package tcc_encoder_v1_0_comp
-- Compiling package tcc_decoder_3gpp_behv_pkg_v1_0
-- Compiling package body tcc_decoder_3gpp_behv_pkg_v1_0
-- Loading package tcc_decoder_3gpp_behv_pkg_v1_0
-- Loading package tcc_decoder_3gpp_behv_pkg_v1_0
-- Compiling entity tcc_decoder_3gpp_v1_0
-- Compiling architecture behavioral of tcc_decoder_3gpp_v1_0
-- Compiling package tcc_decoder_3gpp_v1_0_comp
-- Compiling package body tcc_decoder_3gpp_v1_0_comp
-- Loading package tcc_decoder_3gpp_v1_0_comp
-- Compiling entity inverter
-- Compiling architecture virtexii of inverter
-- Compiling entity cmplx_butterfly
-- Compiling architecture virtexii of cmplx_butterfly
-- Compiling entity dragonfly
-- Compiling architecture virtexii of dragonfly
-- Compiling entity cmplx_mult
-- Compiling architecture virtexii of cmplx_mult
-- Compiling entity arithmetic_shift
-- Compiling architecture virtexii of arithmetic_shift
-- Compiling entity unbias_round
-- Compiling architecture virtexii of unbias_round
-- Compiling entity pe0
-- Compiling architecture virtexii of pe0
-- Compiling entity pe1
-- Compiling architecture virtexii of pe1
-- Compiling entity xfft1024_v1_1
-- Compiling architecture behav_vhdl of xfft1024_v1_1
-- Compiling package xfft1024_v1_1_comp
-- Compiling package rs_ftns_pkg_v5_0
-- Compiling package body rs_ftns_pkg_v5_0
-- Loading package rs_ftns_pkg_v5_0
-- Loading package rs_ftns_pkg_v5_0
-- Compiling entity rs_decoder_v5_0
-- Compiling architecture behavioral of rs_decoder_v5_0
-- Compiling package rs_decoder_v5_0_comp
-- Compiling package body rs_decoder_v5_0_comp
-- Loading package rs_decoder_v5_0_comp
-- Compiling package rs_encoder_v6_1_consts
-- Compiling package body rs_encoder_v6_1_consts
-- Loading package rs_encoder_v6_1_consts
-- Loading package rs_encoder_v6_1_consts
-- Compiling entity rs_encoder_v6_1
-- Compiling architecture behavioral of rs_encoder_v6_1
-- Compiling package rs_encoder_v6_1_comp
-- Loading package rs_encoder_v6_1_comp
-- Compiling entity rs_encoder_v6_1_xst
-- Compiling architecture behavioral of rs_encoder_v6_1_xst
-- Compiling package rs_encoder_v6_1_xst_comp
-- Compiling package sid_v5_0_comp_pkg
-- Compiling package body sid_v5_0_comp_pkg
-- Loading package sid_v5_0_comp_pkg
-- Loading package prims_constants_v9_0
-- Loading package prims_utils_v9_0
-- Compiling package sid_const_pkg_behav_v5_0
-- Compiling package sid_mif_pkg_behav_v5_0
-- Compiling package body sid_mif_pkg_behav_v5_0
-- Loading package sid_mif_pkg_behav_v5_0
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(774382):         WHILE (NOT(ENDFILE(meminitfile)) AND (num_lines < total_lines)) LOOP
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(774382): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_meminit_file".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(774383):           READLINE(meminitfile, bitline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(774383): (vcom-1283) Cannot reference file "meminitfile" inside pure function "read_meminit_file".
-- Loading package sid_const_pkg_behav_v5_0
-- Loading package sid_mif_pkg_behav_v5_0
-- Compiling package sid_pkg_behav_v5_0
-- Compiling package body sid_pkg_behav_v5_0
-- Loading package sid_pkg_behav_v5_0
-- Loading package sid_pkg_behav_v5_0
-- Compiling entity sid_bhv_forney_v5_0
-- Compiling architecture behavioral of sid_bhv_forney_v5_0
-- Compiling entity sid_bhv_rectangular_block_v5_0
-- Compiling architecture behavioral of sid_bhv_rectangular_block_v5_0
-- Compiling entity sid_v5_0
-- Compiling architecture behavioral of sid_v5_0
-- Loading package sid_v5_0_comp_pkg
-- Compiling package sid_v5_0_comp
-- Loading package sid_v5_0_comp
-- Compiling entity sid_v5_0_xst
-- Compiling architecture behavioral of sid_v5_0_xst
-- Compiling package sid_v5_0_xst_comp
-- Compiling entity xfft_v4_0
-- Compiling architecture behavioral of xfft_v4_0
-- Compiling package xfft_v4_0_comp
-- Loading package xfft_v4_0_comp
-- Compiling entity xfft_v4_0_xst
-- Loading package standard
-- Compiling architecture behavioral of xfft_v4_0_xst
-- Loading package std_logic_1164
-- Loading package xfft_v4_0_comp
-- Loading entity xfft_v4_0_xst
-- Compiling package xfft_v4_0_xst_comp
-- Compiling package tcc_decoder_3gpp_v3_0_xst_comp
-- Compiling package body tcc_decoder_3gpp_v3_0_xst_comp
-- Loading package tcc_decoder_3gpp_v3_0_xst_comp
-- Compiling package tcc_decoder_3gpp_v3_0_comp
-- Compiling package body tcc_decoder_3gpp_v3_0_comp
-- Loading package tcc_decoder_3gpp_v3_0_comp
-- Compiling package c_dds_v5_0_comp
-- Compiling package viterbi_v6_1_comp
-- Compiling package viterbi_v6_1_xst_comp
-- Loading package prims_constants_v2_0
-- Compiling package c_mac_v3_1_comp
-- Loading package prims_constants_v6_0
-- Compiling package mult_const_pkg_v6_0
-- Loading package mult_const_pkg_v6_0
-- Compiling package parm_v6_0_services
-- Compiling package body parm_v6_0_services
-- Loading package parm_v6_0_services
-- Loading package parm_v6_0_services
-- Compiling package ccm_v6_0_services
-- Compiling package body ccm_v6_0_services
-- Loading package ccm_v6_0_services
-- Loading package ccm_v6_0_services
-- Compiling package sqm_v6_0_services
-- Compiling package body sqm_v6_0_services
-- Loading package sqm_v6_0_services
-- Loading package sqm_v6_0_services
-- Compiling package mult_gen_v6_0_services
-- Compiling package body mult_gen_v6_0_services
-- Loading package mult_gen_v6_0_services
-- Loading package textio
-- Loading package mult_gen_v6_0_services
-- Compiling package mult_pkg_v6_0
-- Compiling package body mult_pkg_v6_0
-- Loading package mult_pkg_v6_0
-- Loading package mult_pkg_v6_0
-- Compiling entity mult_gen_v6_0_non_seq
-- Compiling architecture behavioral of mult_gen_v6_0_non_seq
-- Compiling package mult_gen_v6_0_non_seq_comp
-- Loading package mult_gen_v6_0_non_seq_comp
-- Loading package c_reg_fd_v6_0_comp
-- Compiling entity mult_gen_v6_0_seq
-- Compiling architecture behavioral of mult_gen_v6_0_seq
-- Compiling package mult_gen_v6_0_seq_comp
-- Loading package mult_gen_v6_0_seq_comp
-- Compiling entity mult_gen_v6_0
-- Compiling architecture behavioral of mult_gen_v6_0
-- Compiling package mult_gen_v6_0_comp
-- Loading package prims_utils_v6_0
-- Loading package numeric_std
-- Compiling entity c_gate_bus_v6_0
-- Compiling architecture behavioral of c_gate_bus_v6_0
-- Compiling package c_gate_bus_v6_0_comp
-- Compiling entity c_gate_bit_bus_v6_0
-- Compiling architecture behavioral of c_gate_bit_bus_v6_0
-- Compiling package c_gate_bit_bus_v6_0_comp
-- Compiling entity c_twos_comp_v6_0
-- Compiling architecture behavioral of c_twos_comp_v6_0
-- Compiling package c_twos_comp_v6_0_comp
-- Loading package ul_utils
-- Loading package iputils_mem87
-- Compiling entity c_shift_ram_v6_0
-- Compiling architecture behavioral of c_shift_ram_v6_0
-- Compiling package c_shift_ram_v6_0_comp
-- Compiling entity c_mux_bit_v6_0
-- Compiling architecture behavioral of c_mux_bit_v6_0
-- Compiling package c_mux_bit_v6_0_comp
-- Loading package c_mux_bit_v6_0_comp
-- Compiling entity c_shift_fd_v6_0
-- Compiling architecture behavioral of c_shift_fd_v6_0
-- Compiling package c_shift_fd_v6_0_comp
-- Loading package math_real
-- Compiling package c_sin_cos_v4_2_pack
-- Loading package iputils_std_logic_arith
-- Compiling package body c_sin_cos_v4_2_pack
-- Loading package c_sin_cos_v4_2_pack
-- Compiling entity pipe_bhv_v4_2
-- Compiling architecture behavioral of pipe_bhv_v4_2
-- Compiling package pipe_bhv_v4_2_comp
-- Loading package iputils_std_logic_unsigned
-- Loading package c_shift_fd_v6_0_comp
-- Loading package c_sin_cos_v4_2_pack
-- Loading package pipe_bhv_v4_2_comp
-- Compiling entity c_sin_cos_v4_2
-- Compiling architecture behavioral of c_sin_cos_v4_2
-- Loading entity c_shift_fd_v6_0
-- Loading entity pipe_bhv_v4_2
-- Loading entity c_reg_fd_v6_0
-- Compiling package c_sin_cos_v4_2_comp
-- Compiling package blkmemdp_pkg_v5_0
-- Compiling package body blkmemdp_pkg_v5_0
-- Loading package blkmemdp_pkg_v5_0
-- Compiling package blkmemdp_mem_init_file_pack_v5_0
-- Compiling package body blkmemdp_mem_init_file_pack_v5_0
-- Loading package blkmemdp_mem_init_file_pack_v5_0
-- Loading package vital_timing
-- Loading package blkmemdp_mem_init_file_pack_v5_0
-- Loading package blkmemdp_pkg_v5_0
-- Compiling entity blkmemdp_v5_0
-- Compiling architecture behavioral of blkmemdp_v5_0
-- Compiling package blkmemdp_v5_0_comp
-- Loading package c_addsub_v6_0_comp
-- Compiling entity c_accum_v6_0
-- Compiling architecture behavioral of c_accum_v6_0
-- Compiling package c_accum_v6_0_comp
-- Compiling entity c_dist_mem_v6_0
-- Compiling architecture behavioral of c_dist_mem_v6_0
-- Compiling package c_dist_mem_v6_0_comp
-- Loading package c_mux_bus_v6_0_comp
-- Loading package mult_gen_v6_0_comp
-- Loading package c_gate_bus_v6_0_comp
-- Loading package prims_comps_v6_0
-- Loading package c_compare_v6_0_comp
-- Loading package c_gate_bit_v6_0_comp
-- Loading package c_gate_bit_bus_v6_0_comp
-- Loading package c_twos_comp_v6_0_comp
-- Loading package c_shift_ram_v6_0_comp
-- Loading package c_sin_cos_v4_2_comp
-- Loading package blkmemdp_v5_0_comp
-- Loading package c_accum_v6_0_comp
-- Loading package c_dist_mem_v6_0_comp
-- Compiling package fft20_synth_pkg
-- Compiling package body fft20_synth_pkg
-- Loading package fft20_synth_pkg
-- Compiling package fft20_pkg
-- Compiling package body fft20_pkg
-- Loading package fft20_pkg
-- Compiling package fft20_bb_comps
-- Compiling package fft20_synth_comps
-- Compiling package fft20_comps
-- Compiling entity fft20_equ_rtl
-- Compiling architecture xilinx of fft20_equ_rtl
-- Compiling entity fft20_fde_rtl
-- Compiling architecture xilinx of fft20_fde_rtl
-- Compiling entity fft20_fdre_rtl
-- Compiling architecture xilinx of fft20_fdre_rtl
-- Loading package fft20_synth_comps
-- Compiling entity fft20_cnt_tc_rtl
-- Compiling architecture xilinx of fft20_cnt_tc_rtl
-- Compiling entity fft20_cnt_tc_rtl_a
-- Compiling architecture xilinx of fft20_cnt_tc_rtl_a
-- Compiling entity fft20_reg_rs_rtl
-- Compiling architecture xilinx of fft20_reg_rs_rtl
-- Loading package fft20_synth_pkg
-- Compiling entity fft20_flow_control_a
-- Compiling architecture xilinx of fft20_flow_control_a
-- Compiling entity fft20_flow_control_b
-- Compiling architecture xilinx of fft20_flow_control_b
-- Compiling entity fft20_flow_control_c
-- Compiling architecture xilinx of fft20_flow_control_c
-- Compiling entity fft20_fde
-- Compiling architecture xilinx of fft20_fde
-- Compiling entity fft20_reg_fde
-- Compiling architecture xilinx of fft20_reg_fde
-- Compiling entity fft20_reg_fde_sclr
-- Compiling architecture xilinx of fft20_reg_fde_sclr
-- Compiling entity fft20_reg_fde_sr_1
-- Compiling architecture xilinx of fft20_reg_fde_sr_1
-- Compiling entity fft20_mux_bus
-- Compiling architecture xilinx of fft20_mux_bus
-- Compiling entity fft20_mux_bus_sclr
-- Compiling architecture xilinx of fft20_mux_bus_sclr
-- Compiling entity fft20_mux_bus2
-- Compiling architecture xilinx of fft20_mux_bus2
-- Compiling entity fft20_mux_bus16
-- Compiling architecture xilinx of fft20_mux_bus16
-- Compiling entity fft20_mux_bus8
-- Compiling architecture xilinx of fft20_mux_bus8
-- Compiling entity fft20_adder
-- Compiling architecture xilinx of fft20_adder
-- Compiling entity fft20_adder_bypass
-- Compiling architecture xilinx of fft20_adder_bypass
-- Compiling entity fft20_subtracter
-- Compiling architecture xilinx of fft20_subtracter
-- Compiling entity fft20_sub_byp
-- Compiling architecture xilinx of fft20_sub_byp
-- Compiling entity fft20_sub_byp_j
-- Compiling architecture xilinx of fft20_sub_byp_j
-- Loading package fft20_comps
-- Compiling entity fft20_butterfly
-- Compiling architecture xilinx of fft20_butterfly
-- Compiling entity fft20_bfly_byp
-- Compiling architecture xilinx of fft20_bfly_byp
-- Compiling entity fft20_butterfly_j
-- Compiling architecture xilinx of fft20_butterfly_j
-- Compiling entity fft20_bfly_byp_j
-- Compiling architecture xilinx of fft20_bfly_byp_j
-- Compiling entity fft20_mult
-- Compiling architecture xilinx of fft20_mult
-- Loading package fft20_pkg
-- Compiling entity fft20_complex_mult3
-- Compiling architecture xilinx of fft20_complex_mult3
-- Compiling entity fft20_dragonfly
-- Compiling architecture xilinx of fft20_dragonfly
-- Compiling entity fft20_dfly_byp
-- Compiling architecture xilinx of fft20_dfly_byp
-- Compiling entity fft20_and2
-- Compiling architecture xilinx of fft20_and2
-- Compiling entity fft20_and_gate
-- Compiling architecture xilinx of fft20_and_gate
-- Compiling entity fft20_and_bus_gate
-- Compiling architecture xilinx of fft20_and_bus_gate
-- Compiling entity fft20_shift_ram
-- Compiling architecture xilinx of fft20_shift_ram
-- Compiling entity fft20_shift_ram_1
-- Compiling architecture xilinx of fft20_shift_ram_1
-- Compiling entity fft20_shift_ram_sclr
-- Compiling architecture xilinx of fft20_shift_ram_sclr
-- Compiling entity fft20_shift_ram_1_sclr
-- Compiling architecture xilinx of fft20_shift_ram_1_sclr
-- Compiling entity fft20_c_lut
-- Compiling architecture xilinx of fft20_c_lut
-- Compiling entity fft20_c_lut_reg
-- Compiling architecture xilinx of fft20_c_lut_reg
-- Compiling entity fft20_c_lut_reg_sclr
-- Compiling architecture xilinx of fft20_c_lut_reg_sclr
-- Compiling entity fft20_compare
-- Compiling architecture xilinx of fft20_compare
-- Compiling entity fft20_xor_bit_gate
-- Compiling architecture xilinx of fft20_xor_bit_gate
-- Compiling entity fft20_xnor_bit_gate
-- Compiling architecture xilinx of fft20_xnor_bit_gate
-- Compiling entity fft20_io_addr_gen
-- Compiling architecture xilinx of fft20_io_addr_gen
-- Compiling entity fft20_out_addr_gen
-- Compiling architecture xilinx of fft20_out_addr_gen
-- Compiling entity fft20_rw_addr_gen
-- Compiling architecture xilinx of fft20_rw_addr_gen
-- Compiling entity fft20_tw_gen_p2
-- Compiling architecture xilinx of fft20_tw_gen_p2
-- Compiling entity fft20_tw_gen_p4
-- Compiling architecture xilinx of fft20_tw_gen_p4
-- Compiling entity fft20_in_switch4
-- Compiling architecture xilinx of fft20_in_switch4
-- Compiling entity fft20_tw_addr_gen
-- Compiling architecture xilinx of fft20_tw_addr_gen
-- Compiling entity fft20_out_switch4
-- Compiling architecture xilinx of fft20_out_switch4
-- Compiling entity fft20_max2_2
-- Compiling architecture xilinx of fft20_max2_2
-- Compiling entity fft20_arith_shift3
-- Compiling architecture xilinx of fft20_arith_shift3
-- Compiling entity fft20_ranger
-- Compiling architecture xilinx of fft20_ranger
-- Compiling entity fft20_ranger3
-- Compiling architecture xilinx of fft20_ranger3
-- Compiling entity fft20_overflow_gen
-- Compiling architecture xilinx of fft20_overflow_gen
-- Compiling entity fft20_unbiased_round
-- Compiling architecture xilinx of fft20_unbiased_round
-- Compiling entity fft20_pe4
-- Compiling architecture xilinx of fft20_pe4
-- Compiling entity fft20_sin_cos
-- Compiling architecture xilinx of fft20_sin_cos
-- Compiling entity fft20_dpm
-- Compiling architecture xilinx of fft20_dpm
-- Compiling entity fft20_dist_mem
-- Compiling architecture xilinx of fft20_dist_mem
-- Compiling entity fft20_exp_growth
-- Compiling architecture xilinx of fft20_exp_growth
-- Compiling entity fft20_scale_logic
-- Compiling architecture xilinx of fft20_scale_logic
-- Compiling entity fft20_r2_in_addr
-- Compiling architecture xilinx of fft20_r2_in_addr
-- Compiling entity fft20_r2_ovflo_gen
-- Compiling architecture xilinx of fft20_r2_ovflo_gen
-- Compiling entity fft20_r2_pe
-- Compiling architecture xilinx of fft20_r2_pe
-- Compiling entity fft20_r2_ranger
-- Compiling architecture xilinx of fft20_r2_ranger
-- Compiling entity fft20_r2_scale_logic
-- Compiling architecture xilinx of fft20_r2_scale_logic
-- Compiling entity fft20_r2_rw_addr
-- Compiling architecture xilinx of fft20_r2_rw_addr
-- Compiling entity fft20_r2_tw_addr
-- Compiling architecture xilinx of fft20_r2_tw_addr
-- Loading package fft20_bb_comps
-- Compiling entity xfft_v2_0_a
-- Compiling architecture xilinx of xfft_v2_0_a
-- Compiling entity xfft_v2_0_b
-- Compiling architecture xilinx of xfft_v2_0_b
-- Compiling entity xfft_v2_0_c
-- Compiling architecture xilinx of xfft_v2_0_c
-- Compiling entity xfft_v2_0
-- Compiling architecture behavioral of xfft_v2_0
-- Compiling package xfft_v2_0_comp
-- Compiling package body xfft_v2_0_comp
-- Loading package xfft_v2_0_comp
-- Compiling package tcc_encoder_3gpp_v3_0_comp
-- Compiling package tcc_encoder_3gpp_v3_0_xst_comp
-- Compiling package c_sin_cos_v4_1_pack
-- Compiling package body c_sin_cos_v4_1_pack
-- Loading package c_sin_cos_v4_1_pack
-- Compiling entity pipe_bhv_v4_1
-- Compiling architecture behavioral of pipe_bhv_v4_1
-- Compiling package pipe_bhv_v4_1_comp
-- Loading package prims_constants_v5_0
-- Loading package c_shift_fd_v5_0_comp
-- Loading package c_reg_fd_v5_0_comp
-- Loading package c_sin_cos_v4_1_pack
-- Loading package pipe_bhv_v4_1_comp
-- Compiling entity c_sin_cos_v4_1
-- Compiling architecture behavioral of c_sin_cos_v4_1
-- Loading package c_mux_bit_v5_0_comp
-- Loading entity c_shift_fd_v5_0
-- Loading entity pipe_bhv_v4_1
-- Loading package prims_utils_v5_0
-- Loading entity c_reg_fd_v5_0
-- Compiling package c_sin_cos_v4_1_comp
-- Loading package iputils_std_logic_signed
-- Compiling entity dither_v4_1
-- Compiling architecture rtl of dither_v4_1
-- Compiling package dither_v4_1_comp
-- Loading package c_addsub_v5_0_comp
-- Loading package dither_v4_1_comp
-- Compiling entity dither_add_v4_1
-- Compiling architecture structural of dither_add_v4_1
-- Loading entity dither_v4_1
-- Loading entity c_addsub_v5_0
-- Compiling package dither_add_v4_1_comp
-- Compiling package mult_const_pkg_v5_0
-- Loading package mult_const_pkg_v5_0
-- Compiling package parm_v5_0_services
-- Compiling package body parm_v5_0_services
-- Loading package parm_v5_0_services
-- Loading package parm_v5_0_services
-- Compiling package ccm_v5_0_services
-- Compiling package body ccm_v5_0_services
-- Loading package ccm_v5_0_services
-- Loading package ccm_v5_0_services
-- Compiling package sqm_v5_0_services
-- Compiling package body sqm_v5_0_services
-- Loading package sqm_v5_0_services
-- Loading package sqm_v5_0_services
-- Compiling package mult_gen_v5_0_services
-- Compiling package body mult_gen_v5_0_services
-- Loading package mult_gen_v5_0_services
-- Loading package mult_gen_v5_0_services
-- Compiling package c_dds_v4_1_pack
-- Compiling package body c_dds_v4_1_pack
-- Loading package c_dds_v4_1_pack
-- Loading package mem_init_file_pack_v5_0
-- Compiling entity c_shift_ram_v5_0
-- Compiling architecture behavioral of c_shift_ram_v5_0
-- Compiling package c_shift_ram_v5_0_comp
-- Compiling package mult_pkg_v5_0
-- Compiling package body mult_pkg_v5_0
-- Loading package mult_pkg_v5_0
-- Loading package mult_pkg_v5_0
-- Compiling entity mult_gen_v5_0_non_seq
-- Compiling architecture behavioral of mult_gen_v5_0_non_seq
-- Compiling package mult_gen_v5_0_non_seq_comp
-- Loading package mult_gen_v5_0_non_seq_comp
-- Compiling entity mult_gen_v5_0_seq
-- Compiling architecture behavioral of mult_gen_v5_0_seq
-- Compiling package mult_gen_v5_0_seq_comp
-- Loading package mult_gen_v5_0_seq_comp
-- Compiling entity mult_gen_v5_0
-- Compiling architecture behavioral of mult_gen_v5_0
-- Compiling package mult_gen_v5_0_comp
-- Compiling entity c_twos_comp_v5_0
-- Compiling architecture behavioral of c_twos_comp_v5_0
-- Compiling package c_twos_comp_v5_0_comp
-- Loading package c_twos_comp_v5_0_comp
-- Compiling entity dds_round_v4_1
-- Compiling architecture structural of dds_round_v4_1
-- Loading entity c_twos_comp_v5_0
-- Compiling package dds_round_v4_1_comp
-- Loading package c_shift_ram_v5_0_comp
-- Loading package c_dds_v4_1_pack
-- Loading package mult_gen_v5_0_comp
-- Loading package dds_round_v4_1_comp
-- Compiling entity c_eff_v4_1
-- Compiling architecture c_eff_v4_1 of c_eff_v4_1
-- Loading entity c_shift_ram_v5_0
-- Loading entity dds_round_v4_1
-- Loading entity mult_gen_v5_0
-- Compiling package c_eff_v4_1_comp
-- Loading package c_sin_cos_v4_1_comp
-- Loading package c_accum_v5_0_comp
-- Loading package dither_add_v4_1_comp
-- Loading package c_eff_v4_1_comp
-- Compiling entity c_dds_v4_1
-- Compiling architecture behavioral of c_dds_v4_1
-- Loading entity dither_add_v4_1
-- Loading entity c_eff_v4_1
-- Loading entity c_accum_v5_0
-- Loading entity c_sin_cos_v4_1
-- Compiling package c_dds_v4_1_comp
-- Compiling package bit_correlator_comps
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling package bit_correlator_pack_v3_0
-- Compiling package body bit_correlator_pack_v3_0
-- Loading package bit_correlator_pack_v3_0
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(825496):                WHILE (NOT(endfile(pattern_file)) AND (lines <= number_of_values)) LOOP
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(825496): (vcom-1283) Cannot reference file "pattern_file" inside pure function "read_pattern_mask".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(825497):                        readline(pattern_file, hexline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(825497): (vcom-1283) Cannot reference file "pattern_file" inside pure function "read_pattern_mask".
-- Loading package bit_correlator_pack_v3_0
-- Compiling entity c_bit_correlator_v3_0
-- Compiling architecture behavioral of c_bit_correlator_v3_0
-- Compiling entity rs_encoder_v4_0
-- Compiling architecture behavioral of rs_encoder_v4_0
-- Compiling package rs_encoder_v4_0_comp
-- Compiling package convolution_pack_v3_0
-- Compiling package body convolution_pack_v3_0
-- Loading package convolution_pack_v3_0
-- Loading package convolution_pack_v3_0
-- Compiling entity convolution_v3_0
-- Compiling architecture behavioral of convolution_v3_0
-- Compiling package convolution_v3_0_comp
-- Compiling package tcc_encoder_3gpp_v1_0_comp
-- Compiling package body tcc_encoder_3gpp_v1_0_comp
-- Loading package tcc_encoder_3gpp_v1_0_comp
-- Loading package prims_constants_v7_0
-- Loading package tcc_encoder_3gpp_v1_0_comp
-- Compiling entity tcc_encoder_3gpp_v1_0
-- Compiling architecture behavioral of tcc_encoder_3gpp_v1_0
-- Compiling package mac_fir_v5_1_comp
-- Loading package mac_fir_v5_1_comp
-- Compiling entity mac_fir_v5_1_xst
-- Compiling architecture xilinx of mac_fir_v5_1_xst
-- Compiling package mac_fir_v5_1_xst_comp
-- Compiling package rs_ftns_pkg_v4_0
-- Compiling package body rs_ftns_pkg_v4_0
-- Loading package rs_ftns_pkg_v4_0
-- Loading package rs_ftns_pkg_v4_0
-- Compiling entity rs_decoder_v4_0
-- Compiling architecture behavioral of rs_decoder_v4_0
-- Compiling package rs_decoder_v4_0_comp
-- Compiling package body rs_decoder_v4_0_comp
-- Loading package rs_decoder_v4_0_comp
-- Compiling package xcc_utils_v9_0
-- Compiling package body xcc_utils_v9_0
-- Loading package xcc_utils_v9_0
-- Loading package std_logic_signed
-- Compiling package pkg_dds_compiler_v1_0
-- Compiling package body pkg_dds_compiler_v1_0
-- Loading package pkg_dds_compiler_v1_0
-- Compiling package dds_compiler_v1_0_sim_comps
-- Loading package prims_constants_v9_0
-- Loading package prims_utils_v9_0
-- Loading package xcc_utils_v9_0
-- Loading package iputils_conv
-- Loading package pkg_dds_compiler_v1_0
-- Loading package dds_compiler_v1_0_sim_comps
-- Compiling entity dds_compiler_v1_0
-- Compiling architecture behavioral of dds_compiler_v1_0
-- Compiling package dds_compiler_v1_0_comp
-- Loading package dds_compiler_v1_0_comp
-- Compiling entity dds_compiler_v1_0_xst
-- Compiling architecture behavioral of dds_compiler_v1_0_xst
-- Compiling package dds_compiler_v1_0_xst_comp
-- Loading package c_reg_fd_v9_0_comp
-- Compiling entity c_reg_fd_v9_0_xst
-- Compiling architecture behavioral of c_reg_fd_v9_0_xst
-- Compiling package c_reg_fd_v9_0_xst_comp
-- Loading package pkg_baseblox_v9_0
-- Loading package c_reg_fd_v9_0_xst_comp
-- Compiling entity reg_wrap
-- Compiling architecture synth of reg_wrap
-- Compiling entity xfft_v4_1
-- Compiling architecture behavioral of xfft_v4_1
-- Compiling package xfft_v4_1_comp
-- Loading package xfft_v4_1_comp
-- Compiling entity xfft_v4_1_xst
-- Compiling architecture behavioral of xfft_v4_1_xst
-- Compiling package xfft_v4_1_xst_comp
-- Compiling package rs_encoder_v4_1_comp
-- Loading package rs_encoder_v4_1_comp
-- Compiling entity rs_encoder_v4_1
-- Compiling architecture behavioral of rs_encoder_v4_1
-- Compiling entity addr_gen_3gpp2_v2_0
-- Compiling architecture behavioral of addr_gen_3gpp2_v2_0
-- Compiling package addr_gen_3gpp2_v2_0_comp
-- Loading package addr_gen_3gpp2_v2_0_comp
-- Compiling entity addr_gen_3gpp2_v2_0_xst
-- Compiling architecture behavioral of addr_gen_3gpp2_v2_0_xst
-- Compiling package addr_gen_3gpp2_v2_0_xst_comp
-- Compiling package cic_pack_v3_0
-- Loading package cic_pack_v3_0
-- Compiling entity c_cic_v3_0
-- Compiling architecture behavioral of c_cic_v3_0
-- Compiling package c_cic_v3_0_comp
-- Compiling package tcc_enc_802_16e_v2_1_xst_comp
-- Compiling package tcc_enc_802_16e_v2_1_comp
-- Compiling package c_mac_v3_0_comp
-- Compiling package sid_const_pkg_behav_v3_1
-- Compiling package sid_mif_pkg_behav_v3_1
-- Compiling package body sid_mif_pkg_behav_v3_1
-- Loading package sid_mif_pkg_behav_v3_1
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(833095): :=0;IO0OOOI1IIIlIOIIOO0Il00I1lOOlIIIII:=0;WHILE(NOT(ENDFILE(MEMINITFILE))AND(IOl1I1O0IIO001llOlll1I1lOI1l0IIIII<IOl0I10010lIIIl000I1O1IO1IlOIIIIII))LOOP READLINE(MEMINITFILE,IIl1O1I0001l1001OllOOII0I10l1IIIII);READ(IIl1O1I0001l1001OllOOII0I10l1IIIII,IOl1Ol11IlIl0110l0OOll000lI11IIIII,
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(833095): (vcom-1283) Cannot reference file "meminitfile" inside pure function "iooiooi00l1oooli1ooo0i00ol0iliiiii".
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(833095): (vcom-1283) Cannot reference file "meminitfile" inside pure function "iooiooi00l1oooli1ooo0i00ol0iliiiii".
-- Loading package sid_const_pkg_behav_v3_1
-- Loading package sid_mif_pkg_behav_v3_1
-- Compiling package sid_pkg_behav_v3_1
-- Compiling package body sid_pkg_behav_v3_1
-- Loading package sid_pkg_behav_v3_1
-- Loading package sid_pkg_behav_v3_1
-- Compiling entity sid_bhv_forney_v3_1
-- Compiling architecture behavioral of sid_bhv_forney_v3_1
-- Compiling entity sid_bhv_rectangular_block_v3_1
-- Compiling architecture behavioral of sid_bhv_rectangular_block_v3_1
-- Compiling entity sid_v3_1
-- Compiling architecture behavioral of sid_v3_1
-- Compiling package sid_v3_1_comp
-- Compiling package body sid_v3_1_comp
-- Loading package sid_v3_1_comp
-- Compiling entity tcc_enc_802_16e_v1_1
-- Compiling architecture behavioral of tcc_enc_802_16e_v1_1
-- Compiling package tcc_enc_802_16e_v1_1_comp
-- Loading package tcc_enc_802_16e_v1_1_comp
-- Compiling entity tcc_enc_802_16e_v1_1_xst
-- Compiling architecture behavioral of tcc_enc_802_16e_v1_1_xst
-- Compiling package tcc_enc_802_16e_v1_1_xst_comp
-- Loading package prims_constants_v9_1
-- Loading package c_reg_fd_v9_1_comp
-- Compiling entity c_reg_fd_v9_1_xst
-- Compiling architecture behavioral of c_reg_fd_v9_1_xst
-- Compiling package c_reg_fd_v9_1_xst_comp
-- Loading package prims_utils_v9_1
-- Loading package pkg_baseblox_v9_1
-- Loading package c_reg_fd_v9_1_xst_comp
-- Compiling entity dds_compiler_v2_0_reg
-- Compiling architecture synth of dds_compiler_v2_0_reg
-- Compiling package xcc_utils_v9_1
-- Compiling package body xcc_utils_v9_1
-- Loading package xcc_utils_v9_1
-- Compiling package pkg_dds_compiler_v2_0
-- Compiling package body pkg_dds_compiler_v2_0
-- Loading package pkg_dds_compiler_v2_0
-- Compiling package dds_compiler_v2_0_sim_comps
-- Loading package xcc_utils_v9_1
-- Loading package pkg_dds_compiler_v2_0
-- Loading package dds_compiler_v2_0_sim_comps
-- Compiling entity dds_compiler_v2_0
-- Compiling architecture behavioral of dds_compiler_v2_0
-- Compiling package dds_compiler_v2_0_comp
-- Loading package dds_compiler_v2_0_comp
-- Compiling entity dds_compiler_v2_0_xst
-- Compiling architecture behavioral of dds_compiler_v2_0_xst
-- Compiling package dds_compiler_v2_0_xst_comp
-- Compiling package convolution_v6_1_xst_comp
-- Compiling package convolution_pack_v6_1
-- Compiling package body convolution_pack_v6_1
-- Loading package convolution_pack_v6_1
-- Loading package convolution_pack_v6_1
-- Compiling entity convolution_v6_1
-- Compiling architecture behavioral of convolution_v6_1
-- Compiling package convolution_v6_1_comp
-- Compiling package addr_gen_802_16e_v2_1_comp
-- Compiling package addr_gen_802_16e_v2_1_xst_comp
-- Compiling entity dds_compiler_v1_1_reg
-- Compiling architecture synth of dds_compiler_v1_1_reg
-- Compiling package pkg_dds_compiler_v1_1
-- Compiling package body pkg_dds_compiler_v1_1
-- Loading package pkg_dds_compiler_v1_1
-- Compiling package dds_compiler_v1_1_sim_comps
-- Loading package pkg_dds_compiler_v1_1
-- Loading package dds_compiler_v1_1_sim_comps
-- Compiling entity dds_compiler_v1_1
-- Compiling architecture behavioral of dds_compiler_v1_1
-- Compiling package dds_compiler_v1_1_comp
-- Loading package dds_compiler_v1_1_comp
-- Compiling entity dds_compiler_v1_1_xst
-- Compiling architecture behavioral of dds_compiler_v1_1_xst
-- Compiling package dds_compiler_v1_1_xst_comp
-- Compiling entity cordic_v2_0
-- Compiling package cordic_pack_beh_v2_0
-- Compiling package body cordic_pack_beh_v2_0
-- Loading package cordic_pack_beh_v2_0
-- Loading package cordic_pack_beh_v2_0
-- Compiling architecture behavioral of cordic_v2_0
-- Compiling package cordic_v2_0_comp
-- Loading package family
-- Loading package mult_const_pkg_v7_0
-- Loading package parm_v7_0_services
-- Loading package ccm_v7_0_services
-- Loading package sqm_v7_0_services
-- Loading package mult_gen_v7_0_services
-- Compiling package cmpy_v2_0_pkg
-- Compiling package body cmpy_v2_0_pkg
-- Loading package cmpy_v2_0_pkg
-- Loading package cmpy_v2_0_pkg
-- Compiling entity cmpy_v2_0
-- Compiling architecture behavioral of cmpy_v2_0
-- Compiling package cmpy_v2_0_comp
-- Loading package c_addsub_v7_0_comp
-- Loading package c_gate_bus_v7_0_comp
-- Loading package c_gate_bit_v7_0_comp
-- Loading package prims_comps_v7_0
-- Loading package c_reg_fd_v7_0_comp
-- Loading package c_compare_v7_0_comp
-- Loading package c_dist_mem_v7_1_comp
-- Loading package blkmemdp_pkg_v6_1
-- Loading package blkmemdp_v6_1_comp
-- Loading package mult_gen_v7_0_comp
-- Loading package c_mux_bus_v7_0_comp
-- Loading package c_shift_ram_v7_0_comp
-- Loading package cmpy_v2_0_comp
-- Loading package c_twos_comp_v7_0_comp
-- Loading package c_sin_cos_v5_0_comp
-- Loading package c_gate_bit_bus_v7_0_comp
-- Loading package c_accum_v7_0_comp
-- Loading package prims_utils_v7_0
-- Compiling package fft31_pkg
-- Compiling package body fft31_pkg
-- Loading package fft31_pkg
-- Compiling package fft31_synth_pkg
-- Compiling package body fft31_synth_pkg
-- Loading package fft31_synth_pkg
-- Compiling package fft31_bb_comps
-- Compiling package fft31_synth_comps
-- Compiling package fft31_comps
-- Compiling entity fft31_equ_rtl
-- Compiling architecture xilinx of fft31_equ_rtl
-- Compiling entity fft31_fde_rtl
-- Compiling architecture xilinx of fft31_fde_rtl
-- Compiling entity fft31_fdre_rtl
-- Compiling architecture xilinx of fft31_fdre_rtl
-- Compiling entity fft31_reg_rs_rtl
-- Compiling architecture xilinx of fft31_reg_rs_rtl
-- Loading package vcomponents
-- Compiling entity fft31_reg_re_rtl
-- Compiling architecture xilinx of fft31_reg_re_rtl
-- Loading package fft31_synth_comps
-- Compiling entity fft31_cnt_tc_rtl
-- Compiling architecture xilinx of fft31_cnt_tc_rtl
-- Compiling entity fft31_cnt_tc_rtl_a
-- Compiling architecture xilinx of fft31_cnt_tc_rtl_a
-- Compiling entity fft31_r22_cnt_ctrl
-- Compiling architecture xilinx of fft31_r22_cnt_ctrl
-- Loading package fft31_synth_pkg
-- Compiling entity fft31_r22_flow_ctrl
-- Compiling architecture xilinx of fft31_r22_flow_ctrl
-- Compiling entity fft31_flow_control_a
-- Compiling architecture xilinx of fft31_flow_control_a
-- Compiling entity fft31_flow_control_b
-- Compiling architecture xilinx of fft31_flow_control_b
-- Compiling entity fft31_flow_control_c
-- Compiling architecture xilinx of fft31_flow_control_c
-- Compiling entity fft31_c_lut
-- Compiling architecture xilinx of fft31_c_lut
-- Loading package fft31_comps
-- Compiling entity fft31_c_lut_reg
-- Compiling architecture xilinx of fft31_c_lut_reg
-- Compiling entity fft31_c_lut_reg_sclr
-- Compiling architecture xilinx of fft31_c_lut_reg_sclr
-- Compiling entity fft31_fde
-- Compiling architecture xilinx of fft31_fde
-- Compiling entity fft31_reg_fde
-- Compiling architecture xilinx of fft31_reg_fde
-- Compiling entity fft31_reg_fde_sclr
-- Compiling architecture xilinx of fft31_reg_fde_sclr
-- Compiling entity fft31_reg_fde_sr_1
-- Compiling architecture xilinx of fft31_reg_fde_sr_1
-- Compiling entity fft31_adder
-- Compiling architecture xilinx of fft31_adder
-- Compiling entity fft31_adder_bypass
-- Compiling architecture xilinx of fft31_adder_bypass
-- Compiling entity fft31_compare
-- Compiling architecture xilinx of fft31_compare
-- Compiling entity fft31_sub_byp
-- Compiling architecture xilinx of fft31_sub_byp
-- Compiling entity fft31_sub_byp_j
-- Compiling architecture xilinx of fft31_sub_byp_j
-- Compiling entity fft31_subtracter
-- Compiling architecture xilinx of fft31_subtracter
-- Compiling entity fft31_xor_bit_gate
-- Compiling architecture xilinx of fft31_xor_bit_gate
-- Compiling entity fft31_xnor_bit_gate
-- Compiling architecture xilinx of fft31_xnor_bit_gate
-- Compiling entity fft31_mux_bus
-- Compiling architecture xilinx of fft31_mux_bus
-- Compiling entity fft31_mux_bus_sclr
-- Compiling architecture xilinx of fft31_mux_bus_sclr
-- Compiling entity fft31_mux_bus16
-- Compiling architecture xilinx of fft31_mux_bus16
-- Compiling entity fft31_mux_bus2
-- Compiling architecture xilinx of fft31_mux_bus2
-- Compiling entity fft31_mux_bus8
-- Compiling architecture xilinx of fft31_mux_bus8
-- Compiling entity fft31_mux_bus2_1
-- Compiling architecture xilinx of fft31_mux_bus2_1
-- Compiling entity fft31_ones_comp
-- Compiling architecture xilinx of fft31_ones_comp
-- Compiling entity fft31_twos_comp
-- Compiling architecture xilinx of fft31_twos_comp
-- Compiling entity fft31_and_gate
-- Compiling architecture xilinx of fft31_and_gate
-- Compiling entity fft31_and_bus_gate
-- Compiling architecture xilinx of fft31_and_bus_gate
-- Compiling entity fft31_and2
-- Compiling architecture xilinx of fft31_and2
-- Compiling entity fft31_shift_ram
-- Compiling architecture xilinx of fft31_shift_ram
-- Compiling entity fft31_shift_ram_1
-- Compiling architecture xilinx of fft31_shift_ram_1
-- Compiling entity fft31_shift_ram_sclr
-- Compiling architecture xilinx of fft31_shift_ram_sclr
-- Compiling entity fft31_shift_ram_1_sclr
-- Compiling architecture xilinx of fft31_shift_ram_1_sclr
-- Loading package fft31_pkg
-- Compiling entity fft31_mult
-- Compiling architecture xilinx of fft31_mult
-- Compiling entity fft31_dpm
-- Compiling architecture xilinx of fft31_dpm
-- Compiling entity fft31_dist_mem
-- Compiling architecture xilinx of fft31_dist_mem
-- Compiling entity fft31_sin_cos
-- Compiling architecture xilinx of fft31_sin_cos
-- Compiling entity fft31_max2_2
-- Compiling architecture xilinx of fft31_max2_2
-- Compiling entity fft31_comp8
-- Compiling architecture xilinx of fft31_comp8
-- Compiling entity fft31_range_r2
-- Compiling architecture xilinx of fft31_range_r2
-- Compiling entity fft31_range_r4
-- Compiling architecture xilinx of fft31_range_r4
-- Compiling entity fft31_arith_shift1
-- Compiling architecture xilinx of fft31_arith_shift1
-- Compiling entity fft31_arith_shift3
-- Compiling architecture xilinx of fft31_arith_shift3
-- Compiling entity fft31_r2_ranger
-- Compiling architecture xilinx of fft31_r2_ranger
-- Compiling entity fft31_in_ranger
-- Compiling architecture xilinx of fft31_in_ranger
-- Compiling entity fft31_r4_ranger
-- Compiling architecture xilinx of fft31_r4_ranger
-- Compiling entity fft31_scale_logic
-- Compiling architecture xilinx of fft31_scale_logic
-- Compiling entity fft31_r2_ovflo_gen
-- Compiling architecture xilinx of fft31_r2_ovflo_gen
-- Compiling entity fft31_overflow_gen
-- Compiling architecture xilinx of fft31_overflow_gen
-- Compiling entity fft31_butterfly_dsp48
-- Compiling architecture xilinx of fft31_butterfly_dsp48
-- Compiling entity fft31_butterfly_dsp48_bypass
-- Compiling architecture xilinx of fft31_butterfly_dsp48_bypass
-- Compiling entity fft31_butterfly
-- Compiling architecture xilinx of fft31_butterfly
-- Compiling entity fft31_butterfly_j
-- Compiling architecture xilinx of fft31_butterfly_j
-- Compiling entity fft31_bfly_byp
-- Compiling architecture xilinx of fft31_bfly_byp
-- Compiling entity fft31_bfly_byp_j
-- Compiling architecture xilinx of fft31_bfly_byp_j
-- Compiling entity fft31_complex_mult3
-- Compiling architecture xilinx of fft31_complex_mult3
-- Compiling entity fft31_complex_mult4
-- Compiling architecture xilinx of fft31_complex_mult4
-- Compiling entity fft31_dragonfly_dsp48
-- Compiling architecture xilinx of fft31_dragonfly_dsp48
-- Compiling entity fft31_dragonfly_dsp48_bypass
-- Compiling architecture xilinx of fft31_dragonfly_dsp48_bypass
-- Compiling entity fft31_dragonfly
-- Compiling architecture xilinx of fft31_dragonfly
-- Compiling entity fft31_dfly_byp
-- Compiling architecture xilinx of fft31_dfly_byp
-- Compiling entity fft31_unbiased_round
-- Compiling architecture xilinx of fft31_unbiased_round
-- Compiling entity fft31_pe4
-- Compiling architecture xilinx of fft31_pe4
-- Compiling entity fft31_io_addr_gen
-- Compiling architecture xilinx of fft31_io_addr_gen
-- Compiling entity fft31_rw_addr_gen
-- Compiling architecture xilinx of fft31_rw_addr_gen
-- Compiling entity fft31_rw_addr_gen_b
-- Compiling architecture xilinx of fft31_rw_addr_gen_b
-- Compiling entity fft31_tw_gen_p2
-- Compiling architecture xilinx of fft31_tw_gen_p2
-- Compiling entity fft31_tw_gen_p4
-- Compiling architecture xilinx of fft31_tw_gen_p4
-- Loading package fft31_bb_comps
-- Compiling entity fft31_tw_addr_gen
-- Compiling architecture xilinx of fft31_tw_addr_gen
-- Compiling entity fft31_out_addr_gen
-- Compiling architecture xilinx of fft31_out_addr_gen
-- Compiling entity fft31_out_addr_gen_b
-- Compiling architecture xilinx of fft31_out_addr_gen_b
-- Compiling entity fft31_in_switch4
-- Compiling architecture xilinx of fft31_in_switch4
-- Compiling entity fft31_out_switch4
-- Compiling architecture xilinx of fft31_out_switch4
-- Compiling entity fft31_r2_pe
-- Compiling architecture xilinx of fft31_r2_pe
-- Compiling entity fft31_r2_tw_addr
-- Compiling architecture xilinx of fft31_r2_tw_addr
-- Compiling entity fft31_r2_in_addr
-- Compiling architecture xilinx of fft31_r2_in_addr
-- Compiling entity fft31_r2_rw_addr
-- Compiling architecture xilinx of fft31_r2_rw_addr
-- Compiling entity fft31_r22_cmplx_mult
-- Compiling architecture xilinx of fft31_r22_cmplx_mult
-- Compiling entity fft31_r22_bfly_byp
-- Compiling architecture xilinx of fft31_r22_bfly_byp
-- Compiling entity fft31_r22_memory
-- Compiling architecture xilinx of fft31_r22_memory
-- Compiling entity fft31_r22_tw_gen
-- Compiling architecture xilinx of fft31_r22_tw_gen
-- Compiling entity fft31_r22_ovflo
-- Compiling architecture xilinx of fft31_r22_ovflo
-- Compiling entity fft31_r22_bf1_last_even
-- Compiling architecture xilinx of fft31_r22_bf1_last_even
-- Compiling entity fft31_r22_bf1_last_odd
-- Compiling architecture xilinx of fft31_r22_bf1_last_odd
-- Compiling entity fft31_r22_bf1_penult_odd
-- Compiling architecture xilinx of fft31_r22_bf1_penult_odd
-- Compiling entity fft31_r22_bf1_sp
-- Compiling architecture xilinx of fft31_r22_bf1_sp
-- Compiling entity fft31_r22_bf1
-- Compiling architecture xilinx of fft31_r22_bf1
-- Compiling entity fft31_r22_bf2_last_even
-- Compiling architecture xilinx of fft31_r22_bf2_last_even
-- Compiling entity fft31_r22_bf2_penult_even
-- Compiling architecture xilinx of fft31_r22_bf2_penult_even
-- Compiling entity fft31_r22_bf2_penult_odd
-- Compiling architecture xilinx of fft31_r22_bf2_penult_odd
-- Compiling entity fft31_r22_bf2_sp
-- Compiling architecture xilinx of fft31_r22_bf2_sp
-- Compiling entity fft31_r22_bf2
-- Compiling architecture xilinx of fft31_r22_bf2
-- Compiling entity fft31_r22_pe
-- Compiling architecture xilinx of fft31_r22_pe
-- Compiling entity fft31_r22_pe_last
-- Compiling architecture xilinx of fft31_r22_pe_last
-- Compiling entity xfft_v3_1_a
-- Compiling architecture xilinx of xfft_v3_1_a
-- Compiling entity xfft_v3_1_b
-- Compiling architecture xilinx of xfft_v3_1_b
-- Compiling entity xfft_v3_1_c
-- Compiling architecture xilinx of xfft_v3_1_c
-- Compiling entity xfft_v3_1_d
-- Compiling architecture xilinx of xfft_v3_1_d
-- Compiling entity xfft_v3_1
-- Compiling architecture behavioral of xfft_v3_1
-- Compiling package xfft_v3_1_comp
-- Compiling package body xfft_v3_1_comp
-- Loading package xfft_v3_1_comp
-- Compiling package rs_encoder_v6_0_consts
-- Compiling package body rs_encoder_v6_0_consts
-- Loading package rs_encoder_v6_0_consts
-- Loading package rs_encoder_v6_0_consts
-- Compiling entity rs_encoder_v6_0
-- Compiling architecture behavioral of rs_encoder_v6_0
-- Compiling package rs_encoder_v6_0_comp
-- Loading package rs_encoder_v6_0_comp
-- Compiling entity rs_encoder_v6_0_xst
-- Compiling architecture behavioral of rs_encoder_v6_0_xst
-- Compiling package rs_encoder_v6_0_xst_comp
-- Compiling package sim_pkg
-- Compiling package body sim_pkg
-- Loading package sim_pkg
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878664):     file_open(mif_status,filepointer,mif_file,read_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878664): (vcom-1283) Cannot reference file "filepointer" inside pure function "ram_content".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878666):     while (not(endfile(filepointer)) and (lines < depth)) loop
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878666): (vcom-1283) Cannot reference file "filepointer" inside pure function "ram_content".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878668):       readline(filepointer, dataline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878668): (vcom-1283) Cannot reference file "filepointer" inside pure function "ram_content".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878669):       exit when endfile(filepointer);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878669): (vcom-1283) Cannot reference file "filepointer" inside pure function "ram_content".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878705):     file_close(filepointer);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(878705): (vcom-1283) Cannot reference file "filepointer" inside pure function "ram_content".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879071):   file_open(mif_status,filepointer,filename,read_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879071): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879073):   while (not(endfile(filepointer)) and (lines < number_of_values+offset)) loop
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879073): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879074):     readline(filepointer, dataline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879074): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879086):   file_close(filepointer);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879086): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879112):   file_open(mif_status,filepointer,filename,read_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879112): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data_bin".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879114):   while (not(endfile(filepointer)) and (lines < number_of_values+offset)) loop
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879114): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data_bin".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879115):     readline(filepointer, dataline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879115): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data_bin".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879126):   file_close(filepointer);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879126): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_coef_data_bin".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879147):   file_open(mif_status,filepointer,filename,write_mode); 
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879147): (vcom-1283) Cannot reference file "filepointer" inside pure function "write_coef_data_hex".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879156):     writeline(filepointer,write_line);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879156): (vcom-1283) Cannot reference file "filepointer" inside pure function "write_coef_data_hex".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879159):   file_close(filepointer);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879159): (vcom-1283) Cannot reference file "filepointer" inside pure function "write_coef_data_hex".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879179):   file_open(mif_status,filepointer,filename,write_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879179): (vcom-1283) Cannot reference file "filepointer" inside pure function "write_coef_data".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879197):     writeline(filepointer,write_line);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879197): (vcom-1283) Cannot reference file "filepointer" inside pure function "write_coef_data".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879200):   file_close(filepointer);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879200): (vcom-1283) Cannot reference file "filepointer" inside pure function "write_coef_data".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879219):         file_open(mif_status,filepointer,filename,read_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879219): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_mem_mif_file".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879223):         while (not(endfile(filepointer)) and (lines < number_of_values+offset)) loop
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879223): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_mem_mif_file".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879228):                 readline(filepointer, dataline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879228): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_mem_mif_file".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879250):         file_close(filepointer);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879250): (vcom-1283) Cannot reference file "filepointer" inside pure function "read_mem_mif_file".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879266):         file_open(mif_status,inpfile,filename,read_mode);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879266): (vcom-1283) Cannot reference file "inpfile" inside pure function "get_number_of_inputs".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879268):         while (not(endfile(inpfile))) loop
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879268): (vcom-1283) Cannot reference file "inpfile" inside pure function "get_number_of_inputs".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879269):                 readline(inpfile, oneline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879269): (vcom-1283) Cannot reference file "inpfile" inside pure function "get_number_of_inputs".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879273):         file_close(inpfile);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879273): (vcom-1283) Cannot reference file "inpfile" inside pure function "get_number_of_inputs".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879708):   if (get_number_of_inputs(elab_dir&mif_file)<param.num_taps*param.num_filts) then
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879708): (vcom-1284) Cannot call side-effect function "get_number_of_inputs" from pure function "gen_mif_files".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879713):     report int_to_str(get_number_of_inputs(elab_dir&mif_file) ) severity note;
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879713): (vcom-1284) Cannot call side-effect function "get_number_of_inputs" from pure function "gen_mif_files".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879729):                                      filter*param.num_taps);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(879729): (vcom-1284) Cannot call side-effect function "read_coef_data" from pure function "gen_mif_files".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(880204):                                     mac_coefficients(mac)                  );
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(880204): (vcom-1284) Cannot call side-effect function "write_coef_data" from pure function "gen_mif_files".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(880223):                                     half_band_centre_value);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(880223): (vcom-1284) Cannot call side-effect function "write_coef_data" from pure function "gen_mif_files".
-- Compiling package fir_compiler_v3_0_xst_comp
-- Compiling package pkg_name
-- Compiling package body pkg_name
-- Loading package pkg_name
-- Compiling package fir_compiler_v3_0_comp
-- Compiling package dafir_pack_v8_0
-- Loading package dafir_pack_v8_0
-- Compiling entity c_da_fir_v8_0
-- Compiling architecture behavioral of c_da_fir_v8_0
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(887131):     WHILE (NOT(endfile(coeffile)) AND (lines <= number_of_values)) LOOP
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(887131): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(887132):       readline(coeffile, hexline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(887132): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(887169):     filter_coefficients := read_coefficients(filename, orig_number_of_taps, nrz_coef );
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(887169): (vcom-1284) Cannot call side-effect function "read_coefficients" from pure function "assign_filter_coefficients".
-- Compiling package c_da_fir_v8_0_comp
-- Compiling package dafir_pack_v6_0
-- Loading package dafir_pack_v6_0
-- Compiling entity c_da_fir_v6_0
-- Compiling architecture behavioral of c_da_fir_v6_0
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(888580):     WHILE (NOT(endfile(coeffile)) AND (lines <= number_of_values)) LOOP
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(888580): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(888581):       readline(coeffile, hexline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(888581): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(888619):     filter_coefficients := read_coefficients(filename, orig_number_of_taps, nrz_coef );
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(888619): (vcom-1284) Cannot call side-effect function "read_coefficients" from pure function "assign_filter_coefficients".
-- Compiling package da_fir_comps
-- Compiling package convolution_pack_v4_0
-- Compiling package body convolution_pack_v4_0
-- Loading package convolution_pack_v4_0
-- Loading package convolution_pack_v4_0
-- Compiling entity convolution_v4_0
-- Compiling architecture behavioral of convolution_v4_0
-- Compiling package convolution_v4_0_comp
-- Compiling package da_2d_dct_pack_v2_0
-- Compiling package body da_2d_dct_pack_v2_0
-- Loading package da_2d_dct_pack_v2_0
-- Compiling package da_1d_dct_pack_v2_1
-- Compiling package body da_1d_dct_pack_v2_1
-- Loading package da_1d_dct_pack_v2_1
-- Loading package da_1d_dct_pack_v2_1
-- Compiling entity c_da_1d_dct_v2_1
-- Compiling architecture behavioral of c_da_1d_dct_v2_1
-- Compiling package da_1d_dct_v2_1_comp
-- Loading package da_1d_dct_v2_1_comp
-- Loading package da_2d_dct_pack_v2_0
-- Compiling entity c_da_2d_dct_v2_0
-- Compiling architecture behavioral of c_da_2d_dct_v2_0
-- Compiling package da_2d_dct_v2_0_comp
-- Compiling package fft21_synth_pkg
-- Compiling package body fft21_synth_pkg
-- Loading package fft21_synth_pkg
-- Compiling package fft21_pkg
-- Compiling package body fft21_pkg
-- Loading package fft21_pkg
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling package fft21_bb_comps
-- Compiling package fft21_synth_comps
-- Compiling package fft21_comps
-- Compiling entity fft21_equ_rtl
-- Compiling architecture xilinx of fft21_equ_rtl
-- Compiling entity fft21_fde_rtl
-- Compiling architecture xilinx of fft21_fde_rtl
-- Compiling entity fft21_fdre_rtl
-- Compiling architecture xilinx of fft21_fdre_rtl
-- Loading package fft21_synth_comps
-- Compiling entity fft21_cnt_tc_rtl
-- Compiling architecture xilinx of fft21_cnt_tc_rtl
-- Compiling entity fft21_cnt_tc_rtl_a
-- Compiling architecture xilinx of fft21_cnt_tc_rtl_a
-- Compiling entity fft21_reg_rs_rtl
-- Compiling architecture xilinx of fft21_reg_rs_rtl
-- Loading package prims_constants_v6_0
-- Loading package c_reg_fd_v6_0_comp
-- Loading package c_mux_bus_v6_0_comp
-- Loading package mult_const_pkg_v6_0
-- Loading package mult_gen_v6_0_comp
-- Loading package c_gate_bus_v6_0_comp
-- Loading package prims_comps_v6_0
-- Loading package prims_utils_v6_0
-- Loading package numeric_std
-- Loading package textio
-- Loading package c_compare_v6_0_comp
-- Loading package c_gate_bit_v6_0_comp
-- Loading package c_gate_bit_bus_v6_0_comp
-- Loading package c_addsub_v6_0_comp
-- Loading package c_twos_comp_v6_0_comp
-- Loading package c_shift_ram_v6_0_comp
-- Loading package c_sin_cos_v4_2_comp
-- Loading package blkmemdp_pkg_v5_0
-- Loading package blkmemdp_v5_0_comp
-- Loading package c_accum_v6_0_comp
-- Loading package c_dist_mem_v6_0_comp
-- Loading package fft21_synth_pkg
-- Compiling entity fft21_flow_control_a
-- Compiling architecture xilinx of fft21_flow_control_a
-- Compiling entity fft21_flow_control_b
-- Compiling architecture xilinx of fft21_flow_control_b
-- Compiling entity fft21_flow_control_c
-- Compiling architecture xilinx of fft21_flow_control_c
-- Compiling entity fft21_fde
-- Compiling architecture xilinx of fft21_fde
-- Compiling entity fft21_reg_fde
-- Compiling architecture xilinx of fft21_reg_fde
-- Compiling entity fft21_reg_fde_sclr
-- Compiling architecture xilinx of fft21_reg_fde_sclr
-- Compiling entity fft21_reg_fde_sr_1
-- Compiling architecture xilinx of fft21_reg_fde_sr_1
-- Compiling entity fft21_mux_bus
-- Compiling architecture xilinx of fft21_mux_bus
-- Compiling entity fft21_mux_bus_sclr
-- Compiling architecture xilinx of fft21_mux_bus_sclr
-- Compiling entity fft21_mux_bus2
-- Compiling architecture xilinx of fft21_mux_bus2
-- Compiling entity fft21_mux_bus16
-- Compiling architecture xilinx of fft21_mux_bus16
-- Compiling entity fft21_mux_bus8
-- Compiling architecture xilinx of fft21_mux_bus8
-- Compiling entity fft21_adder
-- Compiling architecture xilinx of fft21_adder
-- Compiling entity fft21_adder_bypass
-- Compiling architecture xilinx of fft21_adder_bypass
-- Compiling entity fft21_subtracter
-- Compiling architecture xilinx of fft21_subtracter
-- Compiling entity fft21_sub_byp
-- Compiling architecture xilinx of fft21_sub_byp
-- Compiling entity fft21_sub_byp_j
-- Compiling architecture xilinx of fft21_sub_byp_j
-- Loading package fft21_comps
-- Compiling entity fft21_butterfly
-- Compiling architecture xilinx of fft21_butterfly
-- Compiling entity fft21_bfly_byp
-- Compiling architecture xilinx of fft21_bfly_byp
-- Compiling entity fft21_butterfly_j
-- Compiling architecture xilinx of fft21_butterfly_j
-- Compiling entity fft21_bfly_byp_j
-- Compiling architecture xilinx of fft21_bfly_byp_j
-- Compiling entity fft21_mult
-- Compiling architecture xilinx of fft21_mult
-- Loading package fft21_pkg
-- Compiling entity fft21_complex_mult3
-- Compiling architecture xilinx of fft21_complex_mult3
-- Compiling entity fft21_dragonfly
-- Compiling architecture xilinx of fft21_dragonfly
-- Compiling entity fft21_dfly_byp
-- Compiling architecture xilinx of fft21_dfly_byp
-- Compiling entity fft21_and2
-- Compiling architecture xilinx of fft21_and2
-- Compiling entity fft21_and_gate
-- Compiling architecture xilinx of fft21_and_gate
-- Compiling entity fft21_and_bus_gate
-- Compiling architecture xilinx of fft21_and_bus_gate
-- Compiling entity fft21_shift_ram
-- Compiling architecture xilinx of fft21_shift_ram
-- Compiling entity fft21_shift_ram_1
-- Compiling architecture xilinx of fft21_shift_ram_1
-- Compiling entity fft21_shift_ram_sclr
-- Compiling architecture xilinx of fft21_shift_ram_sclr
-- Compiling entity fft21_shift_ram_1_sclr
-- Compiling architecture xilinx of fft21_shift_ram_1_sclr
-- Compiling entity fft21_c_lut
-- Compiling architecture xilinx of fft21_c_lut
-- Compiling entity fft21_c_lut_reg
-- Compiling architecture xilinx of fft21_c_lut_reg
-- Compiling entity fft21_c_lut_reg_sclr
-- Compiling architecture xilinx of fft21_c_lut_reg_sclr
-- Compiling entity fft21_compare
-- Compiling architecture xilinx of fft21_compare
-- Compiling entity fft21_xor_bit_gate
-- Compiling architecture xilinx of fft21_xor_bit_gate
-- Compiling entity fft21_xnor_bit_gate
-- Compiling architecture xilinx of fft21_xnor_bit_gate
-- Compiling entity fft21_io_addr_gen
-- Compiling architecture xilinx of fft21_io_addr_gen
-- Compiling entity fft21_out_addr_gen
-- Compiling architecture xilinx of fft21_out_addr_gen
-- Compiling entity fft21_rw_addr_gen
-- Compiling architecture xilinx of fft21_rw_addr_gen
-- Compiling entity fft21_tw_gen_p2
-- Compiling architecture xilinx of fft21_tw_gen_p2
-- Compiling entity fft21_tw_gen_p4
-- Compiling architecture xilinx of fft21_tw_gen_p4
-- Compiling entity fft21_in_switch4
-- Compiling architecture xilinx of fft21_in_switch4
-- Compiling entity fft21_tw_addr_gen
-- Compiling architecture xilinx of fft21_tw_addr_gen
-- Compiling entity fft21_out_switch4
-- Compiling architecture xilinx of fft21_out_switch4
-- Compiling entity fft21_max2_2
-- Compiling architecture xilinx of fft21_max2_2
-- Loading package vcomponents
-- Compiling entity fft21_comp8
-- Compiling architecture xilinx of fft21_comp8
-- Compiling entity fft21_range_r4
-- Compiling architecture xilinx of fft21_range_r4
-- Compiling entity fft21_range_r2
-- Compiling architecture xilinx of fft21_range_r2
-- Compiling entity fft21_in_ranger
-- Compiling architecture xilinx of fft21_in_ranger
-- Compiling entity fft21_r4_ranger
-- Compiling architecture xilinx of fft21_r4_ranger
-- Compiling entity fft21_arith_shift3
-- Compiling architecture xilinx of fft21_arith_shift3
-- Compiling entity fft21_overflow_gen
-- Compiling architecture xilinx of fft21_overflow_gen
-- Compiling entity fft21_unbiased_round
-- Compiling architecture xilinx of fft21_unbiased_round
-- Compiling entity fft21_pe4
-- Compiling architecture xilinx of fft21_pe4
-- Compiling entity fft21_sin_cos
-- Compiling architecture xilinx of fft21_sin_cos
-- Compiling entity fft21_dpm
-- Compiling architecture xilinx of fft21_dpm
-- Compiling entity fft21_dist_mem
-- Compiling architecture xilinx of fft21_dist_mem
-- Compiling entity fft21_scale_logic
-- Compiling architecture xilinx of fft21_scale_logic
-- Compiling entity fft21_r2_in_addr
-- Compiling architecture xilinx of fft21_r2_in_addr
-- Compiling entity fft21_r2_ovflo_gen
-- Compiling architecture xilinx of fft21_r2_ovflo_gen
-- Compiling entity fft21_r2_pe
-- Compiling architecture xilinx of fft21_r2_pe
-- Compiling entity fft21_r2_ranger
-- Compiling architecture xilinx of fft21_r2_ranger
-- Compiling entity fft21_r2_rw_addr
-- Compiling architecture xilinx of fft21_r2_rw_addr
-- Compiling entity fft21_r2_tw_addr
-- Compiling architecture xilinx of fft21_r2_tw_addr
-- Loading package fft21_bb_comps
-- Compiling entity xfft_v2_1_a
-- Compiling architecture xilinx of xfft_v2_1_a
-- Compiling entity xfft_v2_1_b
-- Compiling architecture xilinx of xfft_v2_1_b
-- Compiling entity xfft_v2_1_c
-- Compiling architecture xilinx of xfft_v2_1_c
-- Compiling entity xfft_v2_1
-- Compiling architecture behavioral of xfft_v2_1
-- Compiling package xfft_v2_1_comp
-- Compiling package body xfft_v2_1_comp
-- Loading package xfft_v2_1_comp
-- Loading package prims_constants_v7_0
-- Compiling package viterbi_pack_v5
-- Compiling package body viterbi_pack_v5
-- Loading package viterbi_pack_v5
-- Loading package iputils_std_logic_arith
-- Loading package viterbi_pack_v5
-- Compiling entity viterbi_v5_0
-- Compiling architecture behavioral of viterbi_v5_0
-- Compiling package viterbi_v5_0_comp
-- Compiling package dafir_pack_v9_0
-- Loading package dafir_pack_v9_0
-- Loading package ul_utils
-- Compiling entity c_da_fir_v9_0
-- Compiling architecture behavioral of c_da_fir_v9_0
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(914319):     WHILE (NOT(endfile(coeffile)) AND (lines <= number_of_values)) LOOP
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(914319): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(914320):       readline(coeffile, hexline);
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(914320): (vcom-1283) Cannot reference file "coeffile" inside pure function "read_coefficients".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(914357):     filter_coefficients := read_coefficients(filename, orig_number_of_taps, nrz_coef );
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(914357): (vcom-1284) Cannot call side-effect function "read_coefficients" from pure function "assign_filter_coefficients".
-- Compiling package c_da_fir_v9_0_comp
-- Loading package c_da_fir_v9_0_comp
-- Compiling entity c_da_fir_v9_0_xst
-- Compiling architecture xilinx of c_da_fir_v9_0_xst
-- Compiling package c_da_fir_v9_0_xst_comp
-- Compiling package c_dds_v4_2_comp
-- Compiling package tcc_decoder_behv_pkg_v1_0
-- Compiling package body tcc_decoder_behv_pkg_v1_0
-- Loading package tcc_decoder_behv_pkg_v1_0
-- Loading package tcc_decoder_behv_pkg_v1_0
-- Compiling entity tcc_decoder_v1_0
-- Compiling architecture behavioral of tcc_decoder_v1_0
-- Compiling package tcc_decoder_v1_0_comp
-- Compiling package body tcc_decoder_v1_0_comp
-- Loading package tcc_decoder_v1_0_comp
-- Compiling package viterbi_pack_v3
-- Compiling package body viterbi_pack_v3
-- Loading package viterbi_pack_v3
-- Loading package viterbi_pack_v3
-- Compiling entity viterbi_v3_0
-- Compiling architecture behavioral of viterbi_v3_0
-- Compiling package viterbi_v3_0_comp
-- Loading package family
-- Loading package mult_const_pkg_v7_0
-- Loading package parm_v7_0_services
-- Loading package ccm_v7_0_services
-- Loading package sqm_v7_0_services
-- Loading package mult_gen_v7_0_services
-- Compiling package cmpy_v2_1_pkg
-- Compiling package body cmpy_v2_1_pkg
-- Loading package cmpy_v2_1_pkg
-- Loading package cmpy_v2_1_pkg
-- Loading package iputils_std_logic_signed
-- Compiling entity cmpy_v2_1
-- Compiling architecture behavioral of cmpy_v2_1
-- Compiling package cmpy_v2_1_comp
-- Compiling package rs_encoder_v5_0_comp
-- Compiling package body rs_encoder_v5_0_comp
-- Loading package rs_encoder_v5_0_comp
-- Loading package rs_encoder_v5_0_comp
-- Compiling entity rs_encoder_v5_0
-- Compiling architecture behavioral of rs_encoder_v5_0
-- Loading package prims_constants_v9_0
-- Compiling package convolution_pack_v6_0
-- Compiling package body convolution_pack_v6_0
-- Loading package convolution_pack_v6_0
-- Loading package convolution_pack_v6_0
-- Compiling entity convolution_v6_0
-- Compiling architecture behavioral of convolution_v6_0
-- Compiling package convolution_v6_0_comp
-- Compiling package convolution_v6_0_xst_comp
-- Compiling package mac_fir_v4_0_comp
-- Compiling package rs_ftns_pkg_v4_1
-- Compiling package body rs_ftns_pkg_v4_1
-- Loading package rs_ftns_pkg_v4_1
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Loading package rs_ftns_pkg_v4_1
-- Compiling entity rs_decoder_v4_1
-- Compiling architecture behavioral of rs_decoder_v4_1
-- Compiling package rs_decoder_v4_1_comp
-- Compiling package body rs_decoder_v4_1_comp
-- Loading package rs_decoder_v4_1_comp
-- Compiling package sid_const_pkg_behav_v3_0
-- Compiling package sid_mif_pkg_behav_v3_0
-- Compiling package body sid_mif_pkg_behav_v3_0
-- Loading package sid_mif_pkg_behav_v3_0
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(920160):  IIIO10O1ll1l0O0IOl0l1lllO0lI1IIIII:=II0IOOI1Il101lO1O010O0O0IO10IOIIII;ELSE IIIO10O1ll1l0O0IOl0l1lllO0lI1IIIII:=IOO1l1010O10O10I0llO11O100O1IOIIII;END IF;IIIlOO0OOl101Ol0Oll10O1lOIIO0IIIII:=0;IIIIlI10IO0IlIll11O0O1OII0OIIOIIII:=0;WHILE(NOT(ENDFILE(MEMINITFILE))AND(IIIlOO0OOl101Ol0Oll10O1lOIIO0IIIII<IIIO10O1ll1l0O0IOl0l1lllO0lI1IIIII))
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(920160): (vcom-1283) Cannot reference file "meminitfile" inside pure function "ioo1i1li11ol1l1oollliiii1l1ioiiiii".
###### /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(920161): LOOP READLINE(MEMINITFILE,IOOIOOI00l1OOOlI1OOO0I00Ol0IlIIIII);READ(IOOIOOI00l1OOOlI1OOO0I00Ol0IlIIIII,IIl1O1I0001l1001OllOOII0I10l1IIIII,III0OI0OlIOOl1Ol1I0l00O0lI1IIIIIII);ASSERT III0OI0OlIOOl1Ol1I0l00O0lI1IIIIIII REPORT
** Warning: /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/XilinxCoreLib_source.vhd(920161): (vcom-1283) Cannot reference file "meminitfile" inside pure function "ioo1i1li11ol1l1oollliiii1l1ioiiiii".
-- Loading package sid_const_pkg_behav_v3_0
-- Loading package sid_mif_pkg_behav_v3_0
-- Compiling package sid_pkg_behav_v3_0
-- Compiling package body sid_pkg_behav_v3_0
-- Loading package sid_pkg_behav_v3_0
-- Loading package sid_pkg_behav_v3_0
-- Compiling entity sid_bhv_forney_v3_0
-- Compiling architecture behavioral of sid_bhv_forney_v3_0
-- Compiling entity sid_bhv_rectangular_block_v3_0
-- Compiling architecture behavioral of sid_bhv_rectangular_block_v3_0
-- Compiling entity sid_v3_0
-- Compiling architecture behavioral of sid_v3_0
-- Compiling package sid_v3_0_comp
-- Compiling package body sid_v3_0_comp
-- Loading package sid_v3_0_comp
-- Compiling package mac_fir_v2_0_comp
-- Compiling package mac_fir_v2_0_pack
-- Compiling package floating_point_v2_0_consts
-- Loading package floating_point_v2_0_consts
-- Compiling package floating_point_pkg_v2_0
-- Compiling package body floating_point_pkg_v2_0
-- Loading package floating_point_pkg_v2_0
-- Loading package floating_point_pkg_v2_0
-- Compiling entity flt_pt_operator_v2_0
-- Compiling architecture behavioral of flt_pt_operator_v2_0
-- Compiling entity floating_point_v2_0_xst
-- Compiling architecture behavioral of floating_point_v2_0_xst
-- Compiling package floating_point_v2_0_xst_comp
-- Loading package floating_point_v2_0_xst_comp
-- Compiling entity floating_point_v2_0
-- Compiling architecture behavioral of floating_point_v2_0
-- Compiling package floating_point_v2_0_comp
-- Compiling package addr_gen_3gpp_top_level_pkg_v4_0
-- Loading package addr_gen_3gpp_top_level_pkg_v4_0
-- Compiling package addr_gen_3gpp_v4_0_comp
-- Compiling package body addr_gen_3gpp_v4_0_comp
-- Loading package addr_gen_3gpp_v4_0_comp
-- Compiling package addr_gen_3gpp_v4_0_xst_comp
-- Compiling package body addr_gen_3gpp_v4_0_xst_comp
-- Loading package addr_gen_3gpp_v4_0_xst_comp
-- Compiling package xfft_v3_2_comp
-- Compiling package body xfft_v3_2_comp
-- Loading package xfft_v3_2_comp
-- Compiling entity ldpc_802_16_enc_v1_0
-- Compiling architecture behavioral of ldpc_802_16_enc_v1_0
-- Compiling package ldpc_802_16_enc_v1_0_comp
-- Compiling package ldpc_802_16_enc_v1_0_xst_comp
-- Compiling package sid_const_pkg_behav_turbo_v1_0
-- Loading package sid_const_pkg_behav_turbo_v1_0
-- Compiling package sid_pkg_behav_turbo_v1_0
-- Compiling package body sid_pkg_behav_turbo_v1_0
-- Loading package sid_pkg_behav_turbo_v1_0
-- Loading package sid_pkg_behav_turbo_v1_0
-- Compiling entity sid_turbo_v1_0
-- Compiling architecture behavioral of sid_turbo_v1_0
-- Compiling package sid_turbo_v1_0_comp

END_COMPILE:XilinxCoreLib

==============================================================================

    > Log file /home/habea2/Geccko3com/gecko3com_v04/lib/XilinxCoreLib/cxl_XilinxCoreLib.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[XilinxCoreLib]: No error(s), 105 warning(s)

**************************************************************************
*                         COMPILATION SUMMARY                            *
*                                                                        *
*  Simulator used: mti_se                                                *
*  Compiled on: Mon Jun 15 18:07:27 2009                                 *
*                                                                        *
**************************************************************************
*     Library      |  Lang   |  Mapped Name(s)   | Err#(s)  |  Warn#(s)  *
*------------------------------------------------------------------------*
*  unisim          | vhdl    | unisim            | 0        | 0          *
*------------------------------------------------------------------------*
*  simprim         | vhdl    | simprim           | 0        | 986        *
*------------------------------------------------------------------------*
*  XilinxCoreLib   | vhdl    | XilinxCoreLib     | 0        | 105        *
*------------------------------------------------------------------------*