Subversion Repositories gecko3

(edif coregenerator_fifo_send
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timestamp 2010 2 14 18 31 32)
      (program "Xilinx ngc2edif" (version "L.33"))
      (author "Xilinx. Inc ")
      (comment "This EDIF netlist is to be used within supported synthesis tools")
      (comment "for determining resource/timing estimates of the design component")
      (comment "represented by this netlist.")
      (comment "Command line: -nolog -w /home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/coregenerator/_cg/coregenerator_fifo_send.ngc /home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/coregenerator/_cg/coregenerator_fifo_send.ndf ")))
  (external UNISIMS
    (edifLevel 0)
    (technology (numberDefinition))
    (cell VCC
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port P
              (direction OUTPUT)
            )
            (property TYPE (string "VCC") (owner "Xilinx"))
          )
      )
    )
    (cell GND
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port G
              (direction OUTPUT)
            )
            (property TYPE (string "GND") (owner "Xilinx"))
          )
      )
    )
    (cell FDP
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port C
              (direction INPUT)
            )
            (port D
              (direction INPUT)
            )
            (port PRE
              (direction INPUT)
            )
            (port Q
              (direction OUTPUT)
            )
            (property TYPE (string "FDP") (owner "Xilinx"))
            (property XSTLIB (boolean (true)) (owner "Xilinx"))
            (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
          )
      )
    )
    (cell FDPE
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port C
              (direction INPUT)
            )
            (port CE
              (direction INPUT)
            )
            (port D
              (direction INPUT)
            )
            (port PRE
              (direction INPUT)
            )
            (port Q
              (direction OUTPUT)
            )
            (property TYPE (string "FDPE") (owner "Xilinx"))
            (property XSTLIB (boolean (true)) (owner "Xilinx"))
            (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
          )
      )
    )
    (cell FDCE
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port C
              (direction INPUT)
            )
            (port CE
              (direction INPUT)
            )
            (port CLR
              (direction INPUT)
            )
            (port D
              (direction INPUT)
            )
            (port Q
              (direction OUTPUT)
            )
            (property TYPE (string "FDCE") (owner "Xilinx"))
            (property XSTLIB (boolean (true)) (owner "Xilinx"))
          )
      )
    )
    (cell MUXCY
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port CI
              (direction INPUT)
            )
            (port DI
              (direction INPUT)
            )
            (port S
              (direction INPUT)
            )
            (port O
              (direction OUTPUT)
            )
            (property TYPE (string "MUXCY") (owner "Xilinx"))
            (property XSTLIB (boolean (true)) (owner "Xilinx"))
          )
      )
    )
    (cell XORCY
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port CI
              (direction INPUT)
            )
            (port LI
              (direction INPUT)
            )
            (port O
              (direction OUTPUT)
            )
            (property TYPE (string "XORCY") (owner "Xilinx"))
            (property XSTLIB (boolean (true)) (owner "Xilinx"))
          )
      )
    )
    (cell FDC
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port C
              (direction INPUT)
            )
            (port CLR
              (direction INPUT)
            )
            (port D
              (direction INPUT)
            )
            (port Q
              (direction OUTPUT)
            )
            (property TYPE (string "FDC") (owner "Xilinx"))
            (property XSTLIB (boolean (true)) (owner "Xilinx"))
          )
      )
    )
    (cell LUT2
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port I0
              (direction INPUT)
            )
            (port I1
              (direction INPUT)
            )
            (port O
              (direction OUTPUT)
            )
            (property TYPE (string "LUT2") (owner "Xilinx"))
            (property XSTLIB (boolean (true)) (owner "Xilinx"))
          )
      )
    )
    (cell LUT3
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port I0
              (direction INPUT)
            )
            (port I1
              (direction INPUT)
            )
            (port I2
              (direction INPUT)
            )
            (port O
              (direction OUTPUT)
            )
            (property TYPE (string "LUT3") (owner "Xilinx"))
            (property XSTLIB (boolean (true)) (owner "Xilinx"))
          )
      )
    )
    (cell LUT4
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port I0
              (direction INPUT)
            )
            (port I1
              (direction INPUT)
            )
            (port I2
              (direction INPUT)
            )
            (port I3
              (direction INPUT)
            )
            (port O
              (direction OUTPUT)
            )
            (property TYPE (string "LUT4") (owner "Xilinx"))
            (property XSTLIB (boolean (true)) (owner "Xilinx"))
          )
      )
    )
    (cell LUT1
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port I0
              (direction INPUT)
            )
            (port O
              (direction OUTPUT)
            )
            (property TYPE (string "LUT1") (owner "Xilinx"))
            (property XSTLIB (boolean (true)) (owner "Xilinx"))
          )
      )
    )
    (cell INV
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port I
              (direction INPUT)
            )
            (port O
              (direction OUTPUT)
            )
            (property TYPE (string "INV") (owner "Xilinx"))
            (property XSTLIB (boolean (true)) (owner "Xilinx"))
          )
      )
    )
    (cell RAMB16_S18_S36
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port CLKA
              (direction INPUT)
            )
            (port CLKB
              (direction INPUT)
            )
            (port ENA
              (direction INPUT)
            )
            (port ENB
              (direction INPUT)
            )
            (port SSRA
              (direction INPUT)
            )
            (port SSRB
              (direction INPUT)
            )
            (port WEA
              (direction INPUT)
            )
            (port WEB
              (direction INPUT)
            )
            (port (array (rename ADDRA "ADDRA<9:0>") 10)
              (direction INPUT))
            (port (array (rename ADDRB "ADDRB<8:0>") 9)
              (direction INPUT))
            (port (array (rename DIA "DIA<15:0>") 16)
              (direction INPUT))
            (port (array (rename DIB "DIB<31:0>") 32)
              (direction INPUT))
            (port (array (rename DIPA "DIPA<1:0>") 2)
              (direction INPUT))
            (port (array (rename DIPB "DIPB<3:0>") 4)
              (direction INPUT))
            (port (array (rename DOA "DOA<15:0>") 16)
              (direction OUTPUT))
            (port (array (rename DOPA "DOPA<1:0>") 2)
              (direction OUTPUT))
            (port (array (rename DOB "DOB<31:0>") 32)
              (direction OUTPUT))
            (port (array (rename DOPB "DOPB<3:0>") 4)
              (direction OUTPUT))
            (property TYPE (string "RAMB16_S18_S36") (owner "Xilinx"))
            (property XSTLIB (boolean (true)) (owner "Xilinx"))
            (property BUS_INFO (string "10:INPUT:ADDRA<9:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:INPUT:ADDRB<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "16:INPUT:DIA<15:0>") (owner "Xilinx"))
            (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
            (property BUS_INFO (string "2:INPUT:DIPA<1:0>") (owner "Xilinx"))
            (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
            (property BUS_INFO (string "16:OUTPUT:DOA<15:0>") (owner "Xilinx"))
            (property BUS_INFO (string "2:OUTPUT:DOPA<1:0>") (owner "Xilinx"))
            (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
            (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
            (property SIM_COLLISION_CHECK (string "NONE") (owner "Xilinx"))
          )
      )
    )
    (cell LUT2_L
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port I0
              (direction INPUT)
            )
            (port I1
              (direction INPUT)
            )
            (port LO
              (direction OUTPUT)
            )
            (property TYPE (string "LUT2_L") (owner "Xilinx"))
            (property XSTLIB (boolean (true)) (owner "Xilinx"))
          )
      )
    )
    (cell LUT3_L
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port I0
              (direction INPUT)
            )
            (port I1
              (direction INPUT)
            )
            (port I2
              (direction INPUT)
            )
            (port LO
              (direction OUTPUT)
            )
            (property TYPE (string "LUT3_L") (owner "Xilinx"))
            (property XSTLIB (boolean (true)) (owner "Xilinx"))
          )
      )
    )
  )

  (library coregenerator_fifo_send_lib
    (edifLevel 0)
    (technology (numberDefinition))
    (cell (rename fifo_generator_v3_3_as_U0_gen_as_fgas "fifo_generator_v3_3_as")
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port DEBUG_RAM_RD_EN
              (direction OUTPUT)
            )
            (port DEBUG_RAM_FULL
              (direction OUTPUT)
            )
            (port RD_EN
              (direction INPUT)
            )
            (port ALMOST_FULL
              (direction OUTPUT)
            )
            (port RST
              (direction INPUT)
            )
            (port DEBUG_RAM_EMPTY
              (direction OUTPUT)
            )
            (port DEBUG_RAM_WR_EN
              (direction OUTPUT)
            )
            (port WR_ACK
              (direction OUTPUT)
            )
            (port EMPTY
              (direction OUTPUT)
            )
            (port WR_EN
              (direction INPUT)
            )
            (port UNDERFLOW
              (direction OUTPUT)
            )
            (port ALMOST_EMPTY
              (direction OUTPUT)
            )
            (port RD_CLK
              (direction INPUT)
            )
            (port OVERFLOW
              (direction OUTPUT)
            )
            (port VALID
              (direction OUTPUT)
            )
            (port FULL
              (direction OUTPUT)
            )
            (port PROG_EMPTY
              (direction OUTPUT)
            )
            (port WR_CLK
              (direction INPUT)
            )
            (port PROG_FULL
              (direction OUTPUT)
            )
            (port (array (rename debug_wr_pntr_r "debug_wr_pntr_r<8:0>") 9)
              (direction OUTPUT))
            (port (array (rename debug_wr_pntr_w "debug_wr_pntr_w<8:0>") 9)
              (direction OUTPUT))
            (port (array (rename debug_rd_pntr_plus1_r "debug_rd_pntr_plus1_r<9:0>") 10)
              (direction OUTPUT))
            (port (array (rename debug_rd_pntr_r "debug_rd_pntr_r<9:0>") 10)
              (direction OUTPUT))
            (port (array (rename debug_rd_pntr_w "debug_rd_pntr_w<9:0>") 10)
              (direction OUTPUT))
            (port (array (rename DEBUG_WR_PNTR "DEBUG_WR_PNTR<8:0>") 9)
              (direction OUTPUT))
            (port (array (rename WR_DATA_COUNT "WR_DATA_COUNT<8:0>") 9)
              (direction OUTPUT))
            (port (array (rename debug_wr_pntr_plus1_w "debug_wr_pntr_plus1_w<8:0>") 9)
              (direction OUTPUT))
            (port (array (rename DEBUG_RD_PNTR "DEBUG_RD_PNTR<9:0>") 10)
              (direction OUTPUT))
            (port (array (rename debug_wr_pntr_plus2_w "debug_wr_pntr_plus2_w<8:0>") 9)
              (direction OUTPUT))
            (port (array (rename DOUT "DOUT<15:0>") 16)
              (direction OUTPUT))
            (port (array (rename RD_DATA_COUNT "RD_DATA_COUNT<8:0>") 9)
              (direction OUTPUT))
            (port (array (rename PROG_EMPTY_THRESH_ASSERT "PROG_EMPTY_THRESH_ASSERT<9:0>") 10)
              (direction INPUT))
            (port (array (rename DIN "DIN<31:0>") 32)
              (direction INPUT))
            (port (array (rename PROG_FULL_THRESH_NEGATE "PROG_FULL_THRESH_NEGATE<8:0>") 9)
              (direction INPUT))
            (port (array (rename PROG_FULL_THRESH_ASSERT "PROG_FULL_THRESH_ASSERT<8:0>") 9)
              (direction INPUT))
            (port (array (rename PROG_FULL_THRESH "PROG_FULL_THRESH<8:0>") 9)
              (direction INPUT))
            (port (array (rename PROG_EMPTY_THRESH_NEGATE "PROG_EMPTY_THRESH_NEGATE<9:0>") 10)
              (direction INPUT))
            (port (array (rename PROG_EMPTY_THRESH "PROG_EMPTY_THRESH<9:0>") 10)
              (direction INPUT))
            (property TYPE (string "fifo_generator_v3_3_as") (owner "Xilinx"))
            (property BUS_INFO (string "9:OUTPUT:debug_wr_pntr_r<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:OUTPUT:debug_wr_pntr_w<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "10:OUTPUT:debug_rd_pntr_plus1_r<9:0>") (owner "Xilinx"))
            (property BUS_INFO (string "10:OUTPUT:debug_rd_pntr_r<9:0>") (owner "Xilinx"))
            (property BUS_INFO (string "10:OUTPUT:debug_rd_pntr_w<9:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:OUTPUT:DEBUG_WR_PNTR<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:OUTPUT:WR_DATA_COUNT<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:OUTPUT:debug_wr_pntr_plus1_w<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "10:OUTPUT:DEBUG_RD_PNTR<9:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:OUTPUT:debug_wr_pntr_plus2_w<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "16:OUTPUT:DOUT<15:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:OUTPUT:RD_DATA_COUNT<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "10:INPUT:PROG_EMPTY_THRESH_ASSERT<9:0>") (owner "Xilinx"))
            (property BUS_INFO (string "32:INPUT:DIN<31:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:INPUT:PROG_FULL_THRESH_NEGATE<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:INPUT:PROG_FULL_THRESH_ASSERT<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:INPUT:PROG_FULL_THRESH<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "10:INPUT:PROG_EMPTY_THRESH_NEGATE<9:0>") (owner "Xilinx"))
            (property BUS_INFO (string "10:INPUT:PROG_EMPTY_THRESH<9:0>") (owner "Xilinx"))
            (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
            (property NLW_MACRO_TAG (integer 2) (owner "Xilinx"))
            (property NLW_MACRO_ALIAS (string "fifo_generator_v3_3_as_U0/gen_as.fgas") (owner "Xilinx"))
          )
          (contents
            (instance XST_GND
              (viewRef view_1 (cellRef GND (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance XST_VCC
              (viewRef view_1 (cellRef VCC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_inblk_rd_rst_int_0 "normgen.inblk/rd_rst_int_0")
              (viewRef view_1 (cellRef FDP (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_inblk_wr_rst_reg_renamed_0 "normgen.inblk/wr_rst_reg")
              (viewRef view_1 (cellRef FDPE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_inblk_wr_rst_fb_renamed_1 "normgen.inblk/wr_rst_fb")
              (viewRef view_1 (cellRef FDP (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_inblk_rd_rst_reg_renamed_2 "normgen.inblk/rd_rst_reg")
              (viewRef view_1 (cellRef FDPE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_1")
              (viewRef view_1 (cellRef FDPE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_0")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_4")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_2")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_3")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_7")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_5")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_6")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_8")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_9")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<0>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<0>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<1>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<2>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<3>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<4>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<5>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<6>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<7>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<8>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<8>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<9>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_1")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_0")
              (viewRef view_1 (cellRef FDPE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_4")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_2")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_3")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_7")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_5")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_6")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_8")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_9")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<0>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<0>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<1>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<2>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<3>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<4>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<5>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<6>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<7>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<8>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<8>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<9>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_0")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_1")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_2")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_3")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_4")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_5")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_6")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_7")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_8")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_9")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<0>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<0>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<1>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<2>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<3>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<4>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<5>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<6>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<7>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<8>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<8>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<9>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_1")
              (viewRef view_1 (cellRef FDPE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_0")
              (viewRef view_1 (cellRef FDPE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_2")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_3")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_6")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_4")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_5")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_7")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_8")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<0>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<0>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<1>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<2>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<3>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<4>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<5>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<6>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<7>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<8>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_1")
              (viewRef view_1 (cellRef FDPE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_0")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_2")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_3")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_6")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_4")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_5")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_7")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_8")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<0>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<0>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<1>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<2>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<3>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<4>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<5>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<6>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<7>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<8>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_1")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_0")
              (viewRef view_1 (cellRef FDPE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_2")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_3")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_6")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_4")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_5")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_7")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_8")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<0>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<0>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<1>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<2>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<3>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<4>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<5>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<6>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<7>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<8>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_0")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_1")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_2")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_3")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_4")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_5")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_6")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_7")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count_8")
              (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<0>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<0>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<1>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<2>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<3>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<4>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<5>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<6>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<7>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<8>")
              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_0__fst_mfirst "normgen.flblk/thrmod/elogic/c1/eqcase.big.mlp[0].fst.mfirst")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_1__mid_mcy "normgen.flblk/thrmod/elogic/c1/eqcase.big.mlp[1].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_2__mid_mcy "normgen.flblk/thrmod/elogic/c1/eqcase.big.mlp[2].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_3__mid_mcy "normgen.flblk/thrmod/elogic/c1/eqcase.big.mlp[3].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_4__mid_mcy "normgen.flblk/thrmod/elogic/c1/eqcase.big.mlp[4].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_0__fst_mfirst "normgen.flblk/thrmod/elogic/c2/eqcase.big.mlp[0].fst.mfirst")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_1__mid_mcy "normgen.flblk/thrmod/elogic/c2/eqcase.big.mlp[1].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_2__mid_mcy "normgen.flblk/thrmod/elogic/c2/eqcase.big.mlp[2].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_3__mid_mcy "normgen.flblk/thrmod/elogic/c2/eqcase.big.mlp[3].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_4__mid_mcy "normgen.flblk/thrmod/elogic/c2/eqcase.big.mlp[4].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_RAM_EMPTY_i "normgen.flblk/thrmod/elogic/RAM_EMPTY_i")
              (viewRef view_1 (cellRef FDP (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_0__fst_mfirst "normgen.flblk/thrmod/flogic/comp1/eqcase.big.mlp[0].fst.mfirst")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_1__mid_mcy "normgen.flblk/thrmod/flogic/comp1/eqcase.big.mlp[1].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_2__mid_mcy "normgen.flblk/thrmod/flogic/comp1/eqcase.big.mlp[2].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_3__mid_mcy "normgen.flblk/thrmod/flogic/comp1/eqcase.big.mlp[3].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_4__mid_mcy "normgen.flblk/thrmod/flogic/comp1/eqcase.big.mlp[4].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_0__fst_mfirst "normgen.flblk/thrmod/flogic/comp2/eqcase.big.mlp[0].fst.mfirst")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_1__mid_mcy "normgen.flblk/thrmod/flogic/comp2/eqcase.big.mlp[1].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_2__mid_mcy "normgen.flblk/thrmod/flogic/comp2/eqcase.big.mlp[2].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_3__mid_mcy "normgen.flblk/thrmod/flogic/comp2/eqcase.big.mlp[3].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_4__mid_mcy "normgen.flblk/thrmod/flogic/comp2/eqcase.big.mlp[4].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_RAM_FULL_i "normgen.flblk/thrmod/flogic/RAM_FULL_i")
              (viewRef view_1 (cellRef FDP (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_0__fst_mfirst "normgen.flblk/thrmod/aelogic/cae1/eqcase.big.mlp[0].fst.mfirst")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_1__mid_mcy "normgen.flblk/thrmod/aelogic/cae1/eqcase.big.mlp[1].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_2__mid_mcy "normgen.flblk/thrmod/aelogic/cae1/eqcase.big.mlp[2].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_3__mid_mcy "normgen.flblk/thrmod/aelogic/cae1/eqcase.big.mlp[3].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_4__mid_mcy "normgen.flblk/thrmod/aelogic/cae1/eqcase.big.mlp[4].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_0__fst_mfirst "normgen.flblk/thrmod/aelogic/cae2/eqcase.big.mlp[0].fst.mfirst")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_1__mid_mcy "normgen.flblk/thrmod/aelogic/cae2/eqcase.big.mlp[1].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_2__mid_mcy "normgen.flblk/thrmod/aelogic/cae2/eqcase.big.mlp[2].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_3__mid_mcy "normgen.flblk/thrmod/aelogic/cae2/eqcase.big.mlp[3].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_4__mid_mcy "normgen.flblk/thrmod/aelogic/cae2/eqcase.big.mlp[4].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_almost_empty_i_renamed_3 "normgen.flblk/thrmod/aelogic/almost_empty_i")
              (viewRef view_1 (cellRef FDPE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_0__fst_mfirst "normgen.flblk/thrmod/aflogic/caf1/eqcase.big.mlp[0].fst.mfirst")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_1__mid_mcy "normgen.flblk/thrmod/aflogic/caf1/eqcase.big.mlp[1].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_2__mid_mcy "normgen.flblk/thrmod/aflogic/caf1/eqcase.big.mlp[2].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_3__mid_mcy "normgen.flblk/thrmod/aflogic/caf1/eqcase.big.mlp[3].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_4__mid_mcy "normgen.flblk/thrmod/aflogic/caf1/eqcase.big.mlp[4].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_0__fst_mfirst "normgen.flblk/thrmod/aflogic/caf2/eqcase.big.mlp[0].fst.mfirst")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_1__mid_mcy "normgen.flblk/thrmod/aflogic/caf2/eqcase.big.mlp[1].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_2__mid_mcy "normgen.flblk/thrmod/aflogic/caf2/eqcase.big.mlp[2].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_3__mid_mcy "normgen.flblk/thrmod/aflogic/caf2/eqcase.big.mlp[3].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_4__mid_mcy "normgen.flblk/thrmod/aflogic/caf2/eqcase.big.mlp[4].mid.mcy")
              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_almost_full_i_renamed_4 "normgen.flblk/thrmod/aflogic/almost_full_i")
              (viewRef view_1 (cellRef FDPE (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_8 "normgen.flblk/clkmod/cx.wrx/PNTR_B_8")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_7 "normgen.flblk/clkmod/cx.wrx/PNTR_B_7")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_6 "normgen.flblk/clkmod/cx.wrx/PNTR_B_6")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_5 "normgen.flblk/clkmod/cx.wrx/PNTR_B_5")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_4 "normgen.flblk/clkmod/cx.wrx/PNTR_B_4")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_3 "normgen.flblk/clkmod/cx.wrx/PNTR_B_3")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_2 "normgen.flblk/clkmod/cx.wrx/PNTR_B_2")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_1 "normgen.flblk/clkmod/cx.wrx/PNTR_B_1")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_0 "normgen.flblk/clkmod/cx.wrx/PNTR_B_0")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2_8")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2_7")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2_6")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2_5")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2_4")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2_3")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2_2")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2_1")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_0 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2_0")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x_8")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x_7")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x_6")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x_5")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x_4")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x_3")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x_2")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x_1")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_0 "normgen.flblk/clkmod/cx.wrx/pntr_gc_x_0")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_8 "normgen.flblk/clkmod/cx.wrx/pntr_gc_8")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_7 "normgen.flblk/clkmod/cx.wrx/pntr_gc_7")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_6 "normgen.flblk/clkmod/cx.wrx/pntr_gc_6")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_5 "normgen.flblk/clkmod/cx.wrx/pntr_gc_5")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_4 "normgen.flblk/clkmod/cx.wrx/pntr_gc_4")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_3 "normgen.flblk/clkmod/cx.wrx/pntr_gc_3")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_2 "normgen.flblk/clkmod/cx.wrx/pntr_gc_2")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_1 "normgen.flblk/clkmod/cx.wrx/pntr_gc_1")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_0 "normgen.flblk/clkmod/cx.wrx/pntr_gc_0")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_9 "normgen.flblk/clkmod/cx.rdx/PNTR_B_9")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_8 "normgen.flblk/clkmod/cx.rdx/PNTR_B_8")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_7 "normgen.flblk/clkmod/cx.rdx/PNTR_B_7")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_6 "normgen.flblk/clkmod/cx.rdx/PNTR_B_6")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_5 "normgen.flblk/clkmod/cx.rdx/PNTR_B_5")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_4 "normgen.flblk/clkmod/cx.rdx/PNTR_B_4")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_3 "normgen.flblk/clkmod/cx.rdx/PNTR_B_3")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_2 "normgen.flblk/clkmod/cx.rdx/PNTR_B_2")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_1 "normgen.flblk/clkmod/cx.rdx/PNTR_B_1")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2_9")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2_8")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2_7")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2_6")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2_5")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2_4")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2_3")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2_2")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2_1")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x_9")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x_8")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x_7")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x_6")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x_5")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x_4")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x_3")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x_2")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x_1")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_0 "normgen.flblk/clkmod/cx.rdx/pntr_gc_x_0")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property ASYNC_REG (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_9 "normgen.flblk/clkmod/cx.rdx/pntr_gc_9")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_8 "normgen.flblk/clkmod/cx.rdx/pntr_gc_8")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_7 "normgen.flblk/clkmod/cx.rdx/pntr_gc_7")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_6 "normgen.flblk/clkmod/cx.rdx/pntr_gc_6")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_5 "normgen.flblk/clkmod/cx.rdx/pntr_gc_5")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_4 "normgen.flblk/clkmod/cx.rdx/pntr_gc_4")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_3 "normgen.flblk/clkmod/cx.rdx/pntr_gc_3")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_2 "normgen.flblk/clkmod/cx.rdx/pntr_gc_2")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_1 "normgen.flblk/clkmod/cx.rdx/pntr_gc_1")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_0 "normgen.flblk/clkmod/cx.rdx/pntr_gc_0")
              (viewRef view_1 (cellRef FDC (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00001 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor00001")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00001 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor00001")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0007_Result1 "normgen.flblk/clkmod/cx.wrx/Mxor_pntr_gc_xor0007_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0006_Result1 "normgen.flblk/clkmod/cx.wrx/Mxor_pntr_gc_xor0006_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0005_Result1 "normgen.flblk/clkmod/cx.wrx/Mxor_pntr_gc_xor0005_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0004_Result1 "normgen.flblk/clkmod/cx.wrx/Mxor_pntr_gc_xor0004_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0003_Result1 "normgen.flblk/clkmod/cx.wrx/Mxor_pntr_gc_xor0003_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0002_Result1 "normgen.flblk/clkmod/cx.wrx/Mxor_pntr_gc_xor0002_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0001_Result1 "normgen.flblk/clkmod/cx.wrx/Mxor_pntr_gc_xor0001_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0000_Result1 "normgen.flblk/clkmod/cx.wrx/Mxor_pntr_gc_xor0000_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0008_Result1 "normgen.flblk/clkmod/cx.rdx/Mxor_pntr_gc_xor0008_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0007_Result1 "normgen.flblk/clkmod/cx.rdx/Mxor_pntr_gc_xor0007_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0006_Result1 "normgen.flblk/clkmod/cx.rdx/Mxor_pntr_gc_xor0006_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0005_Result1 "normgen.flblk/clkmod/cx.rdx/Mxor_pntr_gc_xor0005_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0004_Result1 "normgen.flblk/clkmod/cx.rdx/Mxor_pntr_gc_xor0004_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0003_Result1 "normgen.flblk/clkmod/cx.rdx/Mxor_pntr_gc_xor0003_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0002_Result1 "normgen.flblk/clkmod/cx.rdx/Mxor_pntr_gc_xor0002_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0001_Result1 "normgen.flblk/clkmod/cx.rdx/Mxor_pntr_gc_xor0001_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0000_Result1 "normgen.flblk/clkmod/cx.rdx/Mxor_pntr_gc_xor0000_Result1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00011 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor00011")
              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00011 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor00011")
              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00021 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor00021")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00021 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor00021")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_wpremod_RAM_WR_EN1 "normgen.flblk/wpremod/RAM_WR_EN1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00032 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor00032")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00032 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor00032")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00041 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor00041")
              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00041 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor00041")
              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00051 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor00051")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00051 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor00051")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_rpremod_RAM_RD_EN1 "normgen.flblk/rpremod/RAM_RD_EN1")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp2_v1_4_not00001 "normgen.flblk/thrmod/flogic/comp2/v1_4_not00001")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp1_v1_4_not00001 "normgen.flblk/thrmod/flogic/comp1/v1_4_not00001")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf2_v1_4_not00001 "normgen.flblk/thrmod/aflogic/caf2/v1_4_not00001")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf1_v1_4_not00001 "normgen.flblk/thrmod/aflogic/caf1/v1_4_not00001")
              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c2_v1_4_and00001 "normgen.flblk/thrmod/elogic/c2/v1_4_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c1_v1_4_and00001 "normgen.flblk/thrmod/elogic/c1/v1_4_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae2_v1_4_and00001 "normgen.flblk/thrmod/aelogic/cae2/v1_4_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae1_v1_4_and00001 "normgen.flblk/thrmod/aelogic/cae1/v1_4_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp2_v1_3_and00001 "normgen.flblk/thrmod/flogic/comp2/v1_3_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp1_v1_3_and00001 "normgen.flblk/thrmod/flogic/comp1/v1_3_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c2_v1_3_and00001 "normgen.flblk/thrmod/elogic/c2/v1_3_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c1_v1_3_and00001 "normgen.flblk/thrmod/elogic/c1/v1_3_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf2_v1_3_and00001 "normgen.flblk/thrmod/aflogic/caf2/v1_3_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf1_v1_3_and00001 "normgen.flblk/thrmod/aflogic/caf1/v1_3_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae2_v1_3_and00001 "normgen.flblk/thrmod/aelogic/cae2/v1_3_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae1_v1_3_and00001 "normgen.flblk/thrmod/aelogic/cae1/v1_3_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp2_v1_2_and00001 "normgen.flblk/thrmod/flogic/comp2/v1_2_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp1_v1_2_and00001 "normgen.flblk/thrmod/flogic/comp1/v1_2_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c2_v1_2_and00001 "normgen.flblk/thrmod/elogic/c2/v1_2_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c1_v1_2_and00001 "normgen.flblk/thrmod/elogic/c1/v1_2_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf2_v1_2_and00001 "normgen.flblk/thrmod/aflogic/caf2/v1_2_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf1_v1_2_and00001 "normgen.flblk/thrmod/aflogic/caf1/v1_2_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae2_v1_2_and00001 "normgen.flblk/thrmod/aelogic/cae2/v1_2_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae1_v1_2_and00001 "normgen.flblk/thrmod/aelogic/cae1/v1_2_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp2_v1_1_and00001 "normgen.flblk/thrmod/flogic/comp2/v1_1_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp1_v1_1_and00001 "normgen.flblk/thrmod/flogic/comp1/v1_1_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c2_v1_1_and00001 "normgen.flblk/thrmod/elogic/c2/v1_1_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c1_v1_1_and00001 "normgen.flblk/thrmod/elogic/c1/v1_1_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf2_v1_1_and00001 "normgen.flblk/thrmod/aflogic/caf2/v1_1_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf1_v1_1_and00001 "normgen.flblk/thrmod/aflogic/caf1/v1_1_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae2_v1_1_and00001 "normgen.flblk/thrmod/aelogic/cae2/v1_1_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae1_v1_1_and00001 "normgen.flblk/thrmod/aelogic/cae1/v1_1_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_EMPTY_NONREG_i1 "normgen.flblk/thrmod/elogic/EMPTY_NONREG_i1")
              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_almost_empty_i_or00001 "normgen.flblk/thrmod/aelogic/almost_empty_i_or00001")
              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c2_v1_0_and00001 "normgen.flblk/thrmod/elogic/c2/v1_0_and00001")
              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_elogic_c1_v1_0_and00001 "normgen.flblk/thrmod/elogic/c1/v1_0_and00001")
              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae2_v1_0_and00001 "normgen.flblk/thrmod/aelogic/cae2/v1_0_and00001")
              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_cae1_v1_0_and00001 "normgen.flblk/thrmod/aelogic/cae1/v1_0_and00001")
              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp2_v1_0_and00001 "normgen.flblk/thrmod/flogic/comp2/v1_0_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_comp1_v1_0_and00001 "normgen.flblk/thrmod/flogic/comp1/v1_0_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf2_v1_0_and00001 "normgen.flblk/thrmod/aflogic/caf2/v1_0_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_caf1_v1_0_and00001 "normgen.flblk/thrmod/aflogic/caf1/v1_0_and00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_5 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_6 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_7 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_8 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_9 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_10 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_11 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__rt_renamed_12 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<8>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_13 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_14 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_15 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_16 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_17 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_18 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_19 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__rt_renamed_20 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<8>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_21 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_22 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_23 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_24 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_25 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_26 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_27 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__rt_renamed_28 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<8>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_29 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_30 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_31 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_32 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_33 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_34 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_35 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_36 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_37 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_38 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_39 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_40 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_41 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_42 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_43 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_44 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_45 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_46 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_47 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_48 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_49 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_50 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_51 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_52 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_53 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_54 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_55 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_56 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__rt_renamed_57 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<9>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__rt_renamed_58 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<9>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__rt_renamed_59 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<9>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt_renamed_60 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<8>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt_renamed_61 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<8>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt_renamed_62 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<8>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt_renamed_63 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<8>_rt")
              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00062 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor00062")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00071 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor00071")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00062 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor00062")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00071 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor00071")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_memblk_tmp_ram_rd_en1 "normgen.memblk/tmp_ram_rd_en1")
              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_flogic_FULL_NONREG_i1 "normgen.flblk/thrmod/flogic/FULL_NONREG_i1")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_almost_full_i_or00001 "normgen.flblk/thrmod/aflogic/almost_full_i_or00001")
              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_lut<0>_INV_0")
              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0 "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_lut<0>_INV_0")
              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0 "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_lut<0>_INV_0")
              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_lut<0>_INV_0")
              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_lut<0>_INV_0")
              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0 "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_lut<0>_INV_0")
              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0 "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_lut<0>_INV_0")
              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aflogic_FULL_inv1_INV_0 "normgen.flblk/thrmod/aflogic/FULL_inv1_INV_0")
              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_thrmod_aelogic_EMPTY_inv1_INV_0 "normgen.flblk/thrmod/aelogic/EMPTY_inv1_INV_0")
              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram "normgen.memblk/bmem.bmg.bmg_inst/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2.ram/dp36x18.ram")
              (viewRef view_1 (cellRef RAMB16_S18_S36 (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
              (property BUS_INFO (string "10:INPUT:ADDRA<9:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:INPUT:ADDRB<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "16:INPUT:DIA<15:0>") (owner "Xilinx"))
              (property BUS_INFO (string "32:INPUT:DIB<31:0>") (owner "Xilinx"))
              (property BUS_INFO (string "2:INPUT:DIPA<1:0>") (owner "Xilinx"))
              (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx"))
              (property BUS_INFO (string "16:OUTPUT:DOA<15:0>") (owner "Xilinx"))
              (property BUS_INFO (string "2:OUTPUT:DOPA<1:0>") (owner "Xilinx"))
              (property BUS_INFO (string "32:OUTPUT:DOB<31:0>") (owner "Xilinx"))
              (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx"))
              (property SIM_COLLISION_CHECK (string "NONE") (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW0 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor000611_SW0")
              (viewRef view_1 (cellRef LUT2_L (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor000611_SW1")
              (viewRef view_1 (cellRef LUT3_L (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW0 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor000611_SW0")
              (viewRef view_1 (cellRef LUT2_L (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor000611_SW1")
              (viewRef view_1 (cellRef LUT3_L (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (net DEBUG_RAM_RD_EN
              (joined
                (portRef DEBUG_RAM_RD_EN)
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9))
                (portRef O (instanceRef normgen_flblk_rpremod_RAM_RD_EN1))
                (portRef I2 (instanceRef normgen_flblk_thrmod_elogic_EMPTY_NONREG_i1))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aelogic_almost_empty_i_or00001))
              )
            )
            (net (rename NlwRenamedSignal_normgen_flblk_thrmod_flogic_RAM_FULL_i "NlwRenamedSignal_normgen.flblk/thrmod/flogic/RAM_FULL_i")
              (joined
                (portRef DEBUG_RAM_FULL)
                (portRef FULL)
                (portRef Q (instanceRef normgen_flblk_thrmod_flogic_RAM_FULL_i))
                (portRef I1 (instanceRef normgen_flblk_wpremod_RAM_WR_EN1))
                (portRef I1 (instanceRef normgen_flblk_thrmod_flogic_FULL_NONREG_i1))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aflogic_almost_full_i_or00001))
                (portRef I (instanceRef normgen_flblk_thrmod_aflogic_FULL_inv1_INV_0))
              )
            )
            (net RD_EN
              (joined
                (portRef RD_EN)
                (portRef I0 (instanceRef normgen_flblk_rpremod_RAM_RD_EN1))
                (portRef I0 (instanceRef normgen_memblk_tmp_ram_rd_en1))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_almost_full_i "normgen.flblk/thrmod/aflogic/almost_full_i")
              (joined
                (portRef ALMOST_FULL)
                (portRef Q (instanceRef normgen_flblk_thrmod_aflogic_almost_full_i_renamed_4))
              )
            )
            (net RST
              (joined
                (portRef RST)
                (portRef PRE (instanceRef normgen_inblk_rd_rst_int_0))
                (portRef PRE (instanceRef normgen_inblk_wr_rst_reg_renamed_0))
                (portRef PRE (instanceRef normgen_inblk_wr_rst_fb_renamed_1))
                (portRef PRE (instanceRef normgen_inblk_rd_rst_reg_renamed_2))
              )
            )
            (net (rename NlwRenamedSignal_normgen_flblk_thrmod_elogic_RAM_EMPTY_i "NlwRenamedSignal_normgen.flblk/thrmod/elogic/RAM_EMPTY_i")
              (joined
                (portRef DEBUG_RAM_EMPTY)
                (portRef EMPTY)
                (portRef Q (instanceRef normgen_flblk_thrmod_elogic_RAM_EMPTY_i))
                (portRef I1 (instanceRef normgen_flblk_rpremod_RAM_RD_EN1))
                (portRef I1 (instanceRef normgen_memblk_tmp_ram_rd_en1))
                (portRef I (instanceRef normgen_flblk_thrmod_aelogic_EMPTY_inv1_INV_0))
              )
            )
            (net DEBUG_RAM_WR_EN
              (joined
                (portRef DEBUG_RAM_WR_EN)
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef CE
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef CE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef O (instanceRef normgen_flblk_wpremod_RAM_WR_EN1))
                (portRef WEB (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_RD_DATA_COUNT_0_ "NlwRenamedSignal_RD_DATA_COUNT<0>")
              (joined
                (portRef WR_ACK)
                (portRef UNDERFLOW)
                (portRef OVERFLOW)
                (portRef VALID)
                (portRef PROG_EMPTY)
                (portRef PROG_FULL)
                (portRef (member WR_DATA_COUNT 0))
                (portRef (member WR_DATA_COUNT 1))
                (portRef (member WR_DATA_COUNT 2))
                (portRef (member WR_DATA_COUNT 3))
                (portRef (member WR_DATA_COUNT 4))
                (portRef (member WR_DATA_COUNT 5))
                (portRef (member WR_DATA_COUNT 6))
                (portRef (member WR_DATA_COUNT 7))
                (portRef (member WR_DATA_COUNT 8))
                (portRef (member RD_DATA_COUNT 0))
                (portRef (member RD_DATA_COUNT 1))
                (portRef (member RD_DATA_COUNT 2))
                (portRef (member RD_DATA_COUNT 3))
                (portRef (member RD_DATA_COUNT 4))
                (portRef (member RD_DATA_COUNT 5))
                (portRef (member RD_DATA_COUNT 6))
                (portRef (member RD_DATA_COUNT 7))
                (portRef (member RD_DATA_COUNT 8))
                (portRef G (instanceRef XST_GND))
                (portRef D (instanceRef normgen_inblk_wr_rst_reg_renamed_0))
                (portRef D (instanceRef normgen_inblk_rd_rst_reg_renamed_2))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef DI (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_0__fst_mfirst))
                (portRef DI (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_1__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_2__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_3__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_4__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_0__fst_mfirst))
                (portRef DI (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_1__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_2__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_3__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_4__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_0__fst_mfirst))
                (portRef DI (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_1__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_2__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_3__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_4__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_0__fst_mfirst))
                (portRef DI (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_1__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_2__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_3__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_4__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_0__fst_mfirst))
                (portRef DI (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_1__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_2__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_3__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_4__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_0__fst_mfirst))
                (portRef DI (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_1__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_2__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_3__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_4__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_0__fst_mfirst))
                (portRef DI (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_1__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_2__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_3__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_4__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_0__fst_mfirst))
                (portRef DI (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_1__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_2__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_3__mid_mcy))
                (portRef DI (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_4__mid_mcy))
                (portRef WEA (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 0) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 1) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 2) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 3) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 4) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 5) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 6) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 7) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 8) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 9) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 10) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 11) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 12) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 13) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 14) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIA 15) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIPA 0) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIPA 1) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIPB 0) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIPB 1) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIPB 2) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
                (portRef (member DIPB 3) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net WR_EN
              (joined
                (portRef WR_EN)
                (portRef I0 (instanceRef normgen_flblk_wpremod_RAM_WR_EN1))
                (portRef I0 (instanceRef normgen_flblk_thrmod_flogic_FULL_NONREG_i1))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aflogic_almost_full_i_or00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_almost_empty_i "normgen.flblk/thrmod/aelogic/almost_empty_i")
              (joined
                (portRef ALMOST_EMPTY)
                (portRef Q (instanceRef normgen_flblk_thrmod_aelogic_almost_empty_i_renamed_3))
              )
            )
            (net RD_CLK
              (joined
                (portRef RD_CLK)
                (portRef C (instanceRef normgen_inblk_rd_rst_int_0))
                (portRef C (instanceRef normgen_inblk_rd_rst_reg_renamed_2))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9))
                (portRef C (instanceRef normgen_flblk_thrmod_elogic_RAM_EMPTY_i))
                (portRef C (instanceRef normgen_flblk_thrmod_aelogic_almost_empty_i_renamed_3))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_8))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_7))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_6))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_5))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_4))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_3))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_2))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_1))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_0))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_0))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_0))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_9))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_8))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_7))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_6))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_5))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_4))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_3))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_2))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_1))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_0))
                (portRef CLKA (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net WR_CLK
              (joined
                (portRef WR_CLK)
                (portRef C (instanceRef normgen_inblk_wr_rst_reg_renamed_0))
                (portRef C (instanceRef normgen_inblk_wr_rst_fb_renamed_1))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef C
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef C (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef C (instanceRef normgen_flblk_thrmod_flogic_RAM_FULL_i))
                (portRef C (instanceRef normgen_flblk_thrmod_aflogic_almost_full_i_renamed_4))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_8))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_7))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_6))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_5))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_4))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_3))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_2))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_1))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_0))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_9))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_8))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_7))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_6))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_5))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_4))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_3))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_2))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_1))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1))
                (portRef C (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_0))
                (portRef CLKB (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_8_ "normgen.flblk/clkmod/cx.wrx/PNTR_B<8>")
              (joined
                (portRef (member debug_wr_pntr_r 0))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_8))
                (portRef I2 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_4_and00001))
                (portRef I2 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_4_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_4_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_4_and00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_7_ "normgen.flblk/clkmod/cx.wrx/PNTR_B<7>")
              (joined
                (portRef (member debug_wr_pntr_r 1))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_7))
                (portRef I3 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_4_and00001))
                (portRef I0 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_4_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_4_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_4_and00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_6_ "normgen.flblk/clkmod/cx.wrx/PNTR_B<6>")
              (joined
                (portRef (member debug_wr_pntr_r 2))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_6))
                (portRef I2 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_3_and00001))
                (portRef I2 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_3_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_3_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_3_and00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_5_ "normgen.flblk/clkmod/cx.wrx/PNTR_B<5>")
              (joined
                (portRef (member debug_wr_pntr_r 3))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_5))
                (portRef I3 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_3_and00001))
                (portRef I0 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_3_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_3_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_3_and00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_4_ "normgen.flblk/clkmod/cx.wrx/PNTR_B<4>")
              (joined
                (portRef (member debug_wr_pntr_r 4))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_4))
                (portRef I2 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_2_and00001))
                (portRef I2 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_2_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_2_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_2_and00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_3_ "normgen.flblk/clkmod/cx.wrx/PNTR_B<3>")
              (joined
                (portRef (member debug_wr_pntr_r 5))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_3))
                (portRef I3 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_2_and00001))
                (portRef I0 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_2_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_2_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_2_and00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_2_ "normgen.flblk/clkmod/cx.wrx/PNTR_B<2>")
              (joined
                (portRef (member debug_wr_pntr_r 6))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_2))
                (portRef I2 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_1_and00001))
                (portRef I2 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_1_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_1_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_1_and00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_1_ "normgen.flblk/clkmod/cx.wrx/PNTR_B<1>")
              (joined
                (portRef (member debug_wr_pntr_r 7))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_1))
                (portRef I3 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_1_and00001))
                (portRef I0 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_1_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_1_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_1_and00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_0_ "normgen.flblk/clkmod/cx.wrx/PNTR_B<0>")
              (joined
                (portRef (member debug_wr_pntr_r 8))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_0))
                (portRef I1 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_0_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_0_and00001))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_0_and00001))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_0_and00001))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<8>")
              (joined
                (portRef (member debug_wr_pntr_w 0))
                (portRef (member DEBUG_WR_PNTR 0))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_8))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0000_Result1))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt_renamed_63))
                (portRef (member ADDRB 0) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<7>")
              (joined
                (portRef (member debug_wr_pntr_w 1))
                (portRef (member DEBUG_WR_PNTR 1))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0001_Result1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0000_Result1))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_56))
                (portRef (member ADDRB 1) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<6>")
              (joined
                (portRef (member debug_wr_pntr_w 2))
                (portRef (member DEBUG_WR_PNTR 2))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0002_Result1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0001_Result1))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_55))
                (portRef (member ADDRB 2) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<5>")
              (joined
                (portRef (member debug_wr_pntr_w 3))
                (portRef (member DEBUG_WR_PNTR 3))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0003_Result1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0002_Result1))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_54))
                (portRef (member ADDRB 3) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<4>")
              (joined
                (portRef (member debug_wr_pntr_w 4))
                (portRef (member DEBUG_WR_PNTR 4))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0004_Result1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0003_Result1))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_53))
                (portRef (member ADDRB 4) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<3>")
              (joined
                (portRef (member debug_wr_pntr_w 5))
                (portRef (member DEBUG_WR_PNTR 5))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0005_Result1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0004_Result1))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_52))
                (portRef (member ADDRB 5) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<2>")
              (joined
                (portRef (member debug_wr_pntr_w 6))
                (portRef (member DEBUG_WR_PNTR 6))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0006_Result1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0005_Result1))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_51))
                (portRef (member ADDRB 6) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<1>")
              (joined
                (portRef (member debug_wr_pntr_w 7))
                (portRef (member DEBUG_WR_PNTR 7))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0007_Result1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0006_Result1))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_50))
                (portRef (member ADDRB 7) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<0>")
              (joined
                (portRef (member debug_wr_pntr_w 8))
                (portRef (member DEBUG_WR_PNTR 8))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0007_Result1))
                (portRef I
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0))
                (portRef (member ADDRB 8) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<9>")
              (joined
                (portRef (member debug_rd_pntr_plus1_r 0))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9))
                (portRef I0 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_4_and00001))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_4_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__rt_renamed_58))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<8>")
              (joined
                (portRef (member debug_rd_pntr_plus1_r 1))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef I1 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_4_and00001))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_4_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__rt_renamed_20))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<7>")
              (joined
                (portRef (member debug_rd_pntr_plus1_r 2))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef I0 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_3_and00001))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_3_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_19))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<6>")
              (joined
                (portRef (member debug_rd_pntr_plus1_r 3))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef I1 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_3_and00001))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_3_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_18))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<5>")
              (joined
                (portRef (member debug_rd_pntr_plus1_r 4))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef I0 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_2_and00001))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_2_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_17))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<4>")
              (joined
                (portRef (member debug_rd_pntr_plus1_r 5))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef I1 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_2_and00001))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_2_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_16))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<3>")
              (joined
                (portRef (member debug_rd_pntr_plus1_r 6))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef I0 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_1_and00001))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_1_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_15))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<2>")
              (joined
                (portRef (member debug_rd_pntr_plus1_r 7))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef I1 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_1_and00001))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_1_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_14))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<1>")
              (joined
                (portRef (member debug_rd_pntr_plus1_r 8))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef I2 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_0_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_0_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_13))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<0>")
              (joined
                (portRef (member debug_rd_pntr_plus1_r 9))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef I0 (instanceRef normgen_flblk_thrmod_elogic_c2_v1_0_and00001))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_0_and00001))
                (portRef I
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<9>")
              (joined
                (portRef (member debug_rd_pntr_r 0))
                (portRef (member DEBUG_RD_PNTR 0))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9))
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_9))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0000_Result1))
                (portRef I3 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_4_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__rt_renamed_59))
                (portRef (member ADDRA 0) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<8>")
              (joined
                (portRef (member debug_rd_pntr_r 1))
                (portRef (member DEBUG_RD_PNTR 1))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0001_Result1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0000_Result1))
                (portRef I1 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_4_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__rt_renamed_28))
                (portRef (member ADDRA 1) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<7>")
              (joined
                (portRef (member debug_rd_pntr_r 2))
                (portRef (member DEBUG_RD_PNTR 2))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0002_Result1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0001_Result1))
                (portRef I3 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_3_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_27))
                (portRef (member ADDRA 2) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<6>")
              (joined
                (portRef (member debug_rd_pntr_r 3))
                (portRef (member DEBUG_RD_PNTR 3))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0003_Result1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0002_Result1))
                (portRef I1 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_3_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_26))
                (portRef (member ADDRA 3) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<5>")
              (joined
                (portRef (member debug_rd_pntr_r 4))
                (portRef (member DEBUG_RD_PNTR 4))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0004_Result1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0003_Result1))
                (portRef I3 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_2_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_25))
                (portRef (member ADDRA 4) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<4>")
              (joined
                (portRef (member debug_rd_pntr_r 5))
                (portRef (member DEBUG_RD_PNTR 5))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0005_Result1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0004_Result1))
                (portRef I1 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_2_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_24))
                (portRef (member ADDRA 5) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<3>")
              (joined
                (portRef (member debug_rd_pntr_r 6))
                (portRef (member DEBUG_RD_PNTR 6))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0006_Result1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0005_Result1))
                (portRef I3 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_1_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_23))
                (portRef (member ADDRA 6) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<2>")
              (joined
                (portRef (member debug_rd_pntr_r 7))
                (portRef (member DEBUG_RD_PNTR 7))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0007_Result1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0006_Result1))
                (portRef I1 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_1_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_22))
                (portRef (member ADDRA 7) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<1>")
              (joined
                (portRef (member debug_rd_pntr_r 8))
                (portRef (member DEBUG_RD_PNTR 8))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0008_Result1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0007_Result1))
                (portRef I2 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_0_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_21))
                (portRef (member ADDRA 8) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename NlwRenamedSignal_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_ "NlwRenamedSignal_normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<0>")
              (joined
                (portRef (member debug_rd_pntr_r 9))
                (portRef (member DEBUG_RD_PNTR 9))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0008_Result1))
                (portRef I0 (instanceRef normgen_flblk_thrmod_elogic_c1_v1_0_and00001))
                (portRef I
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0))
                (portRef (member ADDRA 9) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_9_ "normgen.flblk/clkmod/cx.rdx/PNTR_B<9>")
              (joined
                (portRef (member debug_rd_pntr_w 0))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_9))
                (portRef I1 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_4_not00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_4_not00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_4_not00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_4_not00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_8_ "normgen.flblk/clkmod/cx.rdx/PNTR_B<8>")
              (joined
                (portRef (member debug_rd_pntr_w 1))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_8))
                (portRef I3 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_3_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_3_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_3_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_3_and00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_7_ "normgen.flblk/clkmod/cx.rdx/PNTR_B<7>")
              (joined
                (portRef (member debug_rd_pntr_w 2))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_7))
                (portRef I1 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_3_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_3_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_3_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_3_and00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_6_ "normgen.flblk/clkmod/cx.rdx/PNTR_B<6>")
              (joined
                (portRef (member debug_rd_pntr_w 3))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_6))
                (portRef I3 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_2_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_2_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_2_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_2_and00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_5_ "normgen.flblk/clkmod/cx.rdx/PNTR_B<5>")
              (joined
                (portRef (member debug_rd_pntr_w 4))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_5))
                (portRef I1 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_2_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_2_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_2_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_2_and00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_4_ "normgen.flblk/clkmod/cx.rdx/PNTR_B<4>")
              (joined
                (portRef (member debug_rd_pntr_w 5))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_4))
                (portRef I3 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_1_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_1_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_1_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_1_and00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_3_ "normgen.flblk/clkmod/cx.rdx/PNTR_B<3>")
              (joined
                (portRef (member debug_rd_pntr_w 6))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_3))
                (portRef I1 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_1_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_1_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_1_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_1_and00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_2_ "normgen.flblk/clkmod/cx.rdx/PNTR_B<2>")
              (joined
                (portRef (member debug_rd_pntr_w 7))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_2))
                (portRef I3 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_0_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_0_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_0_and00001))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_0_and00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_1_ "normgen.flblk/clkmod/cx.rdx/PNTR_B<1>")
              (joined
                (portRef (member debug_rd_pntr_w 8))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_1))
                (portRef I1 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_0_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_0_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_0_and00001))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_0_and00001))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<8>")
              (joined
                (portRef (member debug_wr_pntr_plus1_w 0))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef I0 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_4_not00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt_renamed_62))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<7>")
              (joined
                (portRef (member debug_wr_pntr_plus1_w 1))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef I2 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_3_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_49))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<6>")
              (joined
                (portRef (member debug_wr_pntr_plus1_w 2))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef I0 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_3_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_48))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<5>")
              (joined
                (portRef (member debug_wr_pntr_plus1_w 3))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef I2 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_2_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_47))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<4>")
              (joined
                (portRef (member debug_wr_pntr_plus1_w 4))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef I0 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_2_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_46))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<3>")
              (joined
                (portRef (member debug_wr_pntr_plus1_w 5))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef I2 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_1_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_45))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<2>")
              (joined
                (portRef (member debug_wr_pntr_plus1_w 6))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef I0 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_1_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_44))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<1>")
              (joined
                (portRef (member debug_wr_pntr_plus1_w 7))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef I2 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_0_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_43))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<0>")
              (joined
                (portRef (member debug_wr_pntr_plus1_w 8))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef I0 (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_0_and00001))
                (portRef I
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<8>")
              (joined
                (portRef (member debug_wr_pntr_plus2_w 0))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef I0 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_4_not00001))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_4_not00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt_renamed_61))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<7>")
              (joined
                (portRef (member debug_wr_pntr_plus2_w 1))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef I2 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_3_and00001))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_3_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_42))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<6>")
              (joined
                (portRef (member debug_wr_pntr_plus2_w 2))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef I0 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_3_and00001))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_3_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_41))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<5>")
              (joined
                (portRef (member debug_wr_pntr_plus2_w 3))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef I2 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_2_and00001))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_2_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_40))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<4>")
              (joined
                (portRef (member debug_wr_pntr_plus2_w 4))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef I0 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_2_and00001))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_2_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_39))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<3>")
              (joined
                (portRef (member debug_wr_pntr_plus2_w 5))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef I2 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_1_and00001))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_1_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_38))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<2>")
              (joined
                (portRef (member debug_wr_pntr_plus2_w 6))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef I0 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_1_and00001))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_1_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_37))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<1>")
              (joined
                (portRef (member debug_wr_pntr_plus2_w 7))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef I2 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_0_and00001))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_0_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_36))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<0>")
              (joined
                (portRef (member debug_wr_pntr_plus2_w 8))
                (portRef Q (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef I0 (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_0_and00001))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_0_and00001))
                (portRef I
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0))
              )
            )
            (net (rename DOUT_15_ "DOUT<15>")
              (joined
                (portRef (member DOUT 0))
                (portRef (member DOA 0) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DOUT_14_ "DOUT<14>")
              (joined
                (portRef (member DOUT 1))
                (portRef (member DOA 1) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DOUT_13_ "DOUT<13>")
              (joined
                (portRef (member DOUT 2))
                (portRef (member DOA 2) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DOUT_12_ "DOUT<12>")
              (joined
                (portRef (member DOUT 3))
                (portRef (member DOA 3) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DOUT_11_ "DOUT<11>")
              (joined
                (portRef (member DOUT 4))
                (portRef (member DOA 4) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DOUT_10_ "DOUT<10>")
              (joined
                (portRef (member DOUT 5))
                (portRef (member DOA 5) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DOUT_9_ "DOUT<9>")
              (joined
                (portRef (member DOUT 6))
                (portRef (member DOA 6) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DOUT_8_ "DOUT<8>")
              (joined
                (portRef (member DOUT 7))
                (portRef (member DOA 7) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DOUT_7_ "DOUT<7>")
              (joined
                (portRef (member DOUT 8))
                (portRef (member DOA 8) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DOUT_6_ "DOUT<6>")
              (joined
                (portRef (member DOUT 9))
                (portRef (member DOA 9) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DOUT_5_ "DOUT<5>")
              (joined
                (portRef (member DOUT 10))
                (portRef (member DOA 10) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DOUT_4_ "DOUT<4>")
              (joined
                (portRef (member DOUT 11))
                (portRef (member DOA 11) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DOUT_3_ "DOUT<3>")
              (joined
                (portRef (member DOUT 12))
                (portRef (member DOA 12) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DOUT_2_ "DOUT<2>")
              (joined
                (portRef (member DOUT 13))
                (portRef (member DOA 13) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DOUT_1_ "DOUT<1>")
              (joined
                (portRef (member DOUT 14))
                (portRef (member DOA 14) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DOUT_0_ "DOUT<0>")
              (joined
                (portRef (member DOUT 15))
                (portRef (member DOA 15) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_31_ "DIN<31>")
              (joined
                (portRef (member DIN 0))
                (portRef (member DIB 16) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_30_ "DIN<30>")
              (joined
                (portRef (member DIN 1))
                (portRef (member DIB 17) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_29_ "DIN<29>")
              (joined
                (portRef (member DIN 2))
                (portRef (member DIB 18) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_28_ "DIN<28>")
              (joined
                (portRef (member DIN 3))
                (portRef (member DIB 19) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_27_ "DIN<27>")
              (joined
                (portRef (member DIN 4))
                (portRef (member DIB 20) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_26_ "DIN<26>")
              (joined
                (portRef (member DIN 5))
                (portRef (member DIB 21) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_25_ "DIN<25>")
              (joined
                (portRef (member DIN 6))
                (portRef (member DIB 22) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_24_ "DIN<24>")
              (joined
                (portRef (member DIN 7))
                (portRef (member DIB 23) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_23_ "DIN<23>")
              (joined
                (portRef (member DIN 8))
                (portRef (member DIB 24) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_22_ "DIN<22>")
              (joined
                (portRef (member DIN 9))
                (portRef (member DIB 25) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_21_ "DIN<21>")
              (joined
                (portRef (member DIN 10))
                (portRef (member DIB 26) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_20_ "DIN<20>")
              (joined
                (portRef (member DIN 11))
                (portRef (member DIB 27) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_19_ "DIN<19>")
              (joined
                (portRef (member DIN 12))
                (portRef (member DIB 28) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_18_ "DIN<18>")
              (joined
                (portRef (member DIN 13))
                (portRef (member DIB 29) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_17_ "DIN<17>")
              (joined
                (portRef (member DIN 14))
                (portRef (member DIB 30) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_16_ "DIN<16>")
              (joined
                (portRef (member DIN 15))
                (portRef (member DIB 31) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_15_ "DIN<15>")
              (joined
                (portRef (member DIN 16))
                (portRef (member DIB 0) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_14_ "DIN<14>")
              (joined
                (portRef (member DIN 17))
                (portRef (member DIB 1) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_13_ "DIN<13>")
              (joined
                (portRef (member DIN 18))
                (portRef (member DIB 2) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_12_ "DIN<12>")
              (joined
                (portRef (member DIN 19))
                (portRef (member DIB 3) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_11_ "DIN<11>")
              (joined
                (portRef (member DIN 20))
                (portRef (member DIB 4) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_10_ "DIN<10>")
              (joined
                (portRef (member DIN 21))
                (portRef (member DIB 5) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_9_ "DIN<9>")
              (joined
                (portRef (member DIN 22))
                (portRef (member DIB 6) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_8_ "DIN<8>")
              (joined
                (portRef (member DIN 23))
                (portRef (member DIB 7) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_7_ "DIN<7>")
              (joined
                (portRef (member DIN 24))
                (portRef (member DIB 8) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_6_ "DIN<6>")
              (joined
                (portRef (member DIN 25))
                (portRef (member DIB 9) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_5_ "DIN<5>")
              (joined
                (portRef (member DIN 26))
                (portRef (member DIB 10) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_4_ "DIN<4>")
              (joined
                (portRef (member DIN 27))
                (portRef (member DIB 11) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_3_ "DIN<3>")
              (joined
                (portRef (member DIN 28))
                (portRef (member DIB 12) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_2_ "DIN<2>")
              (joined
                (portRef (member DIN 29))
                (portRef (member DIB 13) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_1_ "DIN<1>")
              (joined
                (portRef (member DIN 30))
                (portRef (member DIB 14) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename DIN_0_ "DIN<0>")
              (joined
                (portRef (member DIN 31))
                (portRef (member DIB 15) (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net N1
              (joined
                (portRef P (instanceRef XST_VCC))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef DI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef CI (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_0__fst_mfirst))
                (portRef CI (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_0__fst_mfirst))
                (portRef CI (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_0__fst_mfirst))
                (portRef CI (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_0__fst_mfirst))
                (portRef CI (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_0__fst_mfirst))
                (portRef CI (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_0__fst_mfirst))
                (portRef CI (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_0__fst_mfirst))
                (portRef CI (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_0__fst_mfirst))
                (portRef ENB (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename normgen_inblk_rd_rst_reg "normgen.inblk/rd_rst_reg")
              (joined
                (portRef D (instanceRef normgen_inblk_rd_rst_int_0))
                (portRef Q (instanceRef normgen_inblk_rd_rst_reg_renamed_2))
              )
            )
            (net (rename normgen_inblk_rd_rst_fb "normgen.inblk/rd_rst_fb")
              (joined
                (portRef Q (instanceRef normgen_inblk_rd_rst_int_0))
                (portRef CE (instanceRef normgen_inblk_rd_rst_reg_renamed_2))
                (portRef PRE
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef PRE (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9))
                (portRef PRE (instanceRef normgen_flblk_thrmod_elogic_RAM_EMPTY_i))
                (portRef PRE (instanceRef normgen_flblk_thrmod_aelogic_almost_empty_i_renamed_3))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_8))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_7))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_6))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_5))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_4))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_3))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_2))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_1))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_0))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_0))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_0))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_9))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_8))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_7))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_6))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_5))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_4))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_3))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_2))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_1))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_0))
                (portRef I2 (instanceRef normgen_memblk_tmp_ram_rd_en1))
                (portRef SSRA (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename normgen_inblk_wr_rst_fb "normgen.inblk/wr_rst_fb")
              (joined
                (portRef CE (instanceRef normgen_inblk_wr_rst_reg_renamed_0))
                (portRef Q (instanceRef normgen_inblk_wr_rst_fb_renamed_1))
                (portRef PRE
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef PRE
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef CLR
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef PRE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef PRE (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef CLR (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef PRE (instanceRef normgen_flblk_thrmod_flogic_RAM_FULL_i))
                (portRef PRE (instanceRef normgen_flblk_thrmod_aflogic_almost_full_i_renamed_4))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_8))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_7))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_6))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_5))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_4))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_3))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_2))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_1))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_0))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_9))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_8))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_7))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_6))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_5))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_4))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_3))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_2))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_1))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1))
                (portRef CLR (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_0))
                (portRef SSRB (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
            (net (rename normgen_inblk_wr_rst_reg "normgen.inblk/wr_rst_reg")
              (joined
                (portRef Q (instanceRef normgen_inblk_wr_rst_reg_renamed_0))
                (portRef D (instanceRef normgen_inblk_wr_rst_fb_renamed_1))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_1_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<1>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<1>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_0_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_5))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_0_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<0>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<0>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_0_and00001))
                (portRef I
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_4_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<4>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<4>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_2_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_8))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_2_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<2>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<2>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_1_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_6))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_3_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<3>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<3>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_1_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_7))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_7_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<7>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<7>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_3_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_11))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_5_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<5>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<5>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_2_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_9))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_6_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<6>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<6>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_3_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_10))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_8_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<8>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<8>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_4_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__rt_renamed_12))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_9_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<9>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<9>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_4_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__rt_renamed_57))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_lut<0>")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<0>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_5))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_6))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_7))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_8))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_9))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_10))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_11))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<8>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__rt_renamed_12))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<8>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus2.bld_rd_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<9>_rt")
              (joined
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__rt_renamed_57))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_1_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<1>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_0_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<0>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_4_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<4>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_2_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<2>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_3_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<3>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_7_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<7>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_5_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<5>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_6_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<6>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_8_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<8>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_9_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<9>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_lut<0>")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<0>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_13))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_14))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_15))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_16))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_17))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_18))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_19))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<8>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__rt_renamed_20))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_ "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<8>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__rt "normgen.cntblk/gen_cntr.gen_rd_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<9>_rt")
              (joined
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__rt_renamed_58))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_0_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<0>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_1_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<1>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_2_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<2>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_3_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<3>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_4_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<4>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_5_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<5>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_6_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<6>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_7_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<7>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_8_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<8>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_9_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<9>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_lut<0>")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<0>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_21))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_22))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_23))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_24))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_25))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_26))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_27))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__rt "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<8>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__rt_renamed_28))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_ "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<8>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__rt "normgen.cntblk/gen_cntr.gen_rd_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<9>_rt")
              (joined
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_9__rt_renamed_59))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_1_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<1>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<1>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_0_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_29))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_0_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<0>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<0>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_0_and00001))
                (portRef I
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_2_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<2>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<2>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_1_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_30))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_3_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<3>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<3>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_1_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_31))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_6_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<6>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<6>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_3_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_34))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_4_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<4>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<4>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_2_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_32))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_5_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<5>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<5>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_2_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_33))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_7_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<7>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<7>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_3_and00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_35))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_8_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<8>")
              (joined
                (portRef D
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/count<8>")
              (joined
                (portRef Q
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_4_not00001))
                (portRef I0
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt_renamed_60))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_lut<0>")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<0>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_29))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_30))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_31))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_32))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_33))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_34))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_35))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus3.bld_wr_cntr_plus3/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<8>_rt")
              (joined
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt_renamed_60))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_1_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<1>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_0_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<0>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_2_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<2>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_3_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<3>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_6_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<6>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_4_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<4>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_5_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<5>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_7_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<7>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_8_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<8>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_lut<0>")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<0>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_36))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_37))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_38))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_39))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_40))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_41))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_42))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus2/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<8>_rt")
              (joined
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt_renamed_61))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_1_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<1>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_0_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<0>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_2_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<2>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_3_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<3>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_6_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<6>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_4_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<4>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_5_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<5>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_7_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<7>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_8_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<8>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_lut<0>")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<0>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_43))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_44))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_45))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_46))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_47))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_48))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_49))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7_ "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt "normgen.cntblk/gen_cntr.gen_wr_cntr_plus1/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<8>_rt")
              (joined
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt_renamed_62))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_0_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<0>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_1_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<1>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_2_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<2>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_3_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<3>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_4_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<4>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_5_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<5>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_6_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<6>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_7_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<7>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result_8_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Result<8>")
              (joined
                (portRef D (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_lut<0>")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_0__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0__INV_0))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<0>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_1__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__rt_renamed_50))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<1>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_2__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__rt_renamed_51))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<2>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_3__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__rt_renamed_52))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<3>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_4__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__rt_renamed_53))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<4>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_5__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__rt_renamed_54))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<5>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_6__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__rt_renamed_55))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<6>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>_rt")
              (joined
                (portRef S
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_7__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__rt_renamed_56))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7_ "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_cy<7>")
              (joined
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_7__))
                (portRef CI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
              )
            )
            (net (rename normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt "normgen.cntblk/gen_cntr.gen_wr_cntr/gen_bin_cnt_top.bin_cnt_top/gen_bsc_bin_cnt.bld_bin_cnt/Mcount_count_xor<8>_rt")
              (joined
                (portRef LI
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__))
                (portRef O
 (instanceRef normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_xor_8__rt_renamed_63))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c1_v1_0_ "normgen.flblk/thrmod/elogic/c1/v1<0>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_0__fst_mfirst))
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c1_v1_0_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c1_carrynet_0_ "normgen.flblk/thrmod/elogic/c1/carrynet<0>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_0__fst_mfirst))
                (portRef CI (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_1__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c1_v1_1_ "normgen.flblk/thrmod/elogic/c1/v1<1>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_1__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c1_v1_1_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c1_carrynet_1_ "normgen.flblk/thrmod/elogic/c1/carrynet<1>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_1__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_2__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c1_v1_2_ "normgen.flblk/thrmod/elogic/c1/v1<2>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_2__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c1_v1_2_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c1_carrynet_2_ "normgen.flblk/thrmod/elogic/c1/carrynet<2>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_2__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_3__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c1_v1_3_ "normgen.flblk/thrmod/elogic/c1/v1<3>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_3__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c1_v1_3_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c1_carrynet_3_ "normgen.flblk/thrmod/elogic/c1/carrynet<3>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_3__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_4__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c1_v1_4_ "normgen.flblk/thrmod/elogic/c1/v1<4>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_4__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c1_v1_4_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_comp1out "normgen.flblk/thrmod/elogic/comp1out")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c1_eqcase_big_mlp_4__mid_mcy))
                (portRef I1 (instanceRef normgen_flblk_thrmod_elogic_EMPTY_NONREG_i1))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c2_v1_0_ "normgen.flblk/thrmod/elogic/c2/v1<0>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_0__fst_mfirst))
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c2_v1_0_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c2_carrynet_0_ "normgen.flblk/thrmod/elogic/c2/carrynet<0>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_0__fst_mfirst))
                (portRef CI (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_1__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c2_v1_1_ "normgen.flblk/thrmod/elogic/c2/v1<1>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_1__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c2_v1_1_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c2_carrynet_1_ "normgen.flblk/thrmod/elogic/c2/carrynet<1>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_1__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_2__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c2_v1_2_ "normgen.flblk/thrmod/elogic/c2/v1<2>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_2__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c2_v1_2_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c2_carrynet_2_ "normgen.flblk/thrmod/elogic/c2/carrynet<2>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_2__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_3__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c2_v1_3_ "normgen.flblk/thrmod/elogic/c2/v1<3>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_3__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c2_v1_3_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c2_carrynet_3_ "normgen.flblk/thrmod/elogic/c2/carrynet<3>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_3__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_4__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_c2_v1_4_ "normgen.flblk/thrmod/elogic/c2/v1<4>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_4__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c2_v1_4_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_comp2out "normgen.flblk/thrmod/elogic/comp2out")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_c2_eqcase_big_mlp_4__mid_mcy))
                (portRef I0 (instanceRef normgen_flblk_thrmod_elogic_EMPTY_NONREG_i1))
              )
            )
            (net (rename normgen_flblk_thrmod_elogic_EMPTY_NONREG "normgen.flblk/thrmod/elogic/EMPTY_NONREG")
              (joined
                (portRef D (instanceRef normgen_flblk_thrmod_elogic_RAM_EMPTY_i))
                (portRef O (instanceRef normgen_flblk_thrmod_elogic_EMPTY_NONREG_i1))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp1_v1_0_ "normgen.flblk/thrmod/flogic/comp1/v1<0>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_0__fst_mfirst))
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_0_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp1_carrynet_0_ "normgen.flblk/thrmod/flogic/comp1/carrynet<0>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_0__fst_mfirst))
                (portRef CI (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_1__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp1_v1_1_ "normgen.flblk/thrmod/flogic/comp1/v1<1>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_1__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_1_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp1_carrynet_1_ "normgen.flblk/thrmod/flogic/comp1/carrynet<1>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_1__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_2__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp1_v1_2_ "normgen.flblk/thrmod/flogic/comp1/v1<2>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_2__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_2_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp1_carrynet_2_ "normgen.flblk/thrmod/flogic/comp1/carrynet<2>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_2__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_3__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp1_v1_3_ "normgen.flblk/thrmod/flogic/comp1/v1<3>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_3__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_3_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp1_carrynet_3_ "normgen.flblk/thrmod/flogic/comp1/carrynet<3>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_3__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_4__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp1_v1_4_ "normgen.flblk/thrmod/flogic/comp1/v1<4>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_4__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp1_v1_4_not00001))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp_full1 "normgen.flblk/thrmod/flogic/comp_full1")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp1_eqcase_big_mlp_4__mid_mcy))
                (portRef I2 (instanceRef normgen_flblk_thrmod_flogic_FULL_NONREG_i1))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp2_v1_0_ "normgen.flblk/thrmod/flogic/comp2/v1<0>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_0__fst_mfirst))
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_0_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp2_carrynet_0_ "normgen.flblk/thrmod/flogic/comp2/carrynet<0>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_0__fst_mfirst))
                (portRef CI (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_1__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp2_v1_1_ "normgen.flblk/thrmod/flogic/comp2/v1<1>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_1__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_1_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp2_carrynet_1_ "normgen.flblk/thrmod/flogic/comp2/carrynet<1>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_1__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_2__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp2_v1_2_ "normgen.flblk/thrmod/flogic/comp2/v1<2>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_2__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_2_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp2_carrynet_2_ "normgen.flblk/thrmod/flogic/comp2/carrynet<2>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_2__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_3__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp2_v1_3_ "normgen.flblk/thrmod/flogic/comp2/v1<3>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_3__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_3_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp2_carrynet_3_ "normgen.flblk/thrmod/flogic/comp2/carrynet<3>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_3__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_4__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp2_v1_4_ "normgen.flblk/thrmod/flogic/comp2/v1<4>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_4__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp2_v1_4_not00001))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_comp_full2 "normgen.flblk/thrmod/flogic/comp_full2")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_comp2_eqcase_big_mlp_4__mid_mcy))
                (portRef I3 (instanceRef normgen_flblk_thrmod_flogic_FULL_NONREG_i1))
              )
            )
            (net (rename normgen_flblk_thrmod_flogic_FULL_NONREG "normgen.flblk/thrmod/flogic/FULL_NONREG")
              (joined
                (portRef D (instanceRef normgen_flblk_thrmod_flogic_RAM_FULL_i))
                (portRef O (instanceRef normgen_flblk_thrmod_flogic_FULL_NONREG_i1))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae1_v1_0_ "normgen.flblk/thrmod/aelogic/cae1/v1<0>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_0__fst_mfirst))
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_0_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae1_carrynet_0_ "normgen.flblk/thrmod/aelogic/cae1/carrynet<0>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_0__fst_mfirst))
                (portRef CI (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_1__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae1_v1_1_ "normgen.flblk/thrmod/aelogic/cae1/v1<1>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_1__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_1_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae1_carrynet_1_ "normgen.flblk/thrmod/aelogic/cae1/carrynet<1>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_1__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_2__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae1_v1_2_ "normgen.flblk/thrmod/aelogic/cae1/v1<2>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_2__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_2_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae1_carrynet_2_ "normgen.flblk/thrmod/aelogic/cae1/carrynet<2>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_2__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_3__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae1_v1_3_ "normgen.flblk/thrmod/aelogic/cae1/v1<3>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_3__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_3_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae1_carrynet_3_ "normgen.flblk/thrmod/aelogic/cae1/carrynet<3>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_3__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_4__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae1_v1_4_ "normgen.flblk/thrmod/aelogic/cae1/v1<4>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_4__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae1_v1_4_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_comp_ae1 "normgen.flblk/thrmod/aelogic/comp_ae1")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae1_eqcase_big_mlp_4__mid_mcy))
                (portRef I1 (instanceRef normgen_flblk_thrmod_aelogic_almost_empty_i_or00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae2_v1_0_ "normgen.flblk/thrmod/aelogic/cae2/v1<0>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_0__fst_mfirst))
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_0_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae2_carrynet_0_ "normgen.flblk/thrmod/aelogic/cae2/carrynet<0>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_0__fst_mfirst))
                (portRef CI (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_1__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae2_v1_1_ "normgen.flblk/thrmod/aelogic/cae2/v1<1>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_1__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_1_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae2_carrynet_1_ "normgen.flblk/thrmod/aelogic/cae2/carrynet<1>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_1__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_2__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae2_v1_2_ "normgen.flblk/thrmod/aelogic/cae2/v1<2>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_2__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_2_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae2_carrynet_2_ "normgen.flblk/thrmod/aelogic/cae2/carrynet<2>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_2__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_3__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae2_v1_3_ "normgen.flblk/thrmod/aelogic/cae2/v1<3>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_3__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_3_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae2_carrynet_3_ "normgen.flblk/thrmod/aelogic/cae2/carrynet<3>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_3__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_4__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_cae2_v1_4_ "normgen.flblk/thrmod/aelogic/cae2/v1<4>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_4__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae2_v1_4_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_comp_ae2 "normgen.flblk/thrmod/aelogic/comp_ae2")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_cae2_eqcase_big_mlp_4__mid_mcy))
                (portRef I0 (instanceRef normgen_flblk_thrmod_aelogic_almost_empty_i_or00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_EMPTY_inv "normgen.flblk/thrmod/aelogic/EMPTY_inv")
              (joined
                (portRef CE (instanceRef normgen_flblk_thrmod_aelogic_almost_empty_i_renamed_3))
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_EMPTY_inv1_INV_0))
              )
            )
            (net (rename normgen_flblk_thrmod_aelogic_almost_empty_i_or0000 "normgen.flblk/thrmod/aelogic/almost_empty_i_or0000")
              (joined
                (portRef D (instanceRef normgen_flblk_thrmod_aelogic_almost_empty_i_renamed_3))
                (portRef O (instanceRef normgen_flblk_thrmod_aelogic_almost_empty_i_or00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf1_v1_0_ "normgen.flblk/thrmod/aflogic/caf1/v1<0>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_0__fst_mfirst))
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_0_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf1_carrynet_0_ "normgen.flblk/thrmod/aflogic/caf1/carrynet<0>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_0__fst_mfirst))
                (portRef CI (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_1__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf1_v1_1_ "normgen.flblk/thrmod/aflogic/caf1/v1<1>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_1__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_1_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf1_carrynet_1_ "normgen.flblk/thrmod/aflogic/caf1/carrynet<1>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_1__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_2__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf1_v1_2_ "normgen.flblk/thrmod/aflogic/caf1/v1<2>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_2__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_2_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf1_carrynet_2_ "normgen.flblk/thrmod/aflogic/caf1/carrynet<2>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_2__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_3__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf1_v1_3_ "normgen.flblk/thrmod/aflogic/caf1/v1<3>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_3__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_3_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf1_carrynet_3_ "normgen.flblk/thrmod/aflogic/caf1/carrynet<3>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_3__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_4__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf1_v1_4_ "normgen.flblk/thrmod/aflogic/caf1/v1<4>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_4__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf1_v1_4_not00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_comp_af1 "normgen.flblk/thrmod/aflogic/comp_af1")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf1_eqcase_big_mlp_4__mid_mcy))
                (portRef I3 (instanceRef normgen_flblk_thrmod_aflogic_almost_full_i_or00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf2_v1_0_ "normgen.flblk/thrmod/aflogic/caf2/v1<0>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_0__fst_mfirst))
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_0_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf2_carrynet_0_ "normgen.flblk/thrmod/aflogic/caf2/carrynet<0>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_0__fst_mfirst))
                (portRef CI (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_1__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf2_v1_1_ "normgen.flblk/thrmod/aflogic/caf2/v1<1>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_1__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_1_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf2_carrynet_1_ "normgen.flblk/thrmod/aflogic/caf2/carrynet<1>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_1__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_2__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf2_v1_2_ "normgen.flblk/thrmod/aflogic/caf2/v1<2>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_2__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_2_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf2_carrynet_2_ "normgen.flblk/thrmod/aflogic/caf2/carrynet<2>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_2__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_3__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf2_v1_3_ "normgen.flblk/thrmod/aflogic/caf2/v1<3>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_3__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_3_and00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf2_carrynet_3_ "normgen.flblk/thrmod/aflogic/caf2/carrynet<3>")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_3__mid_mcy))
                (portRef CI (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_4__mid_mcy))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_caf2_v1_4_ "normgen.flblk/thrmod/aflogic/caf2/v1<4>")
              (joined
                (portRef S (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_4__mid_mcy))
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf2_v1_4_not00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_comp_af2 "normgen.flblk/thrmod/aflogic/comp_af2")
              (joined
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_caf2_eqcase_big_mlp_4__mid_mcy))
                (portRef I2 (instanceRef normgen_flblk_thrmod_aflogic_almost_full_i_or00001))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_FULL_inv "normgen.flblk/thrmod/aflogic/FULL_inv")
              (joined
                (portRef CE (instanceRef normgen_flblk_thrmod_aflogic_almost_full_i_renamed_4))
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_FULL_inv1_INV_0))
              )
            )
            (net (rename normgen_flblk_thrmod_aflogic_almost_full_i_or0000 "normgen.flblk/thrmod/aflogic/almost_full_i_or0000")
              (joined
                (portRef D (instanceRef normgen_flblk_thrmod_aflogic_almost_full_i_renamed_4))
                (portRef O (instanceRef normgen_flblk_thrmod_aflogic_almost_full_i_or00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2<8>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_8))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00001))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00011))
                (portRef I3 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00021))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0000 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor0000")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_7))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0001 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor0001")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_6))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00011))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor0002")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_5))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00021))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00032))
                (portRef I2 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00041))
                (portRef I3 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00051))
                (portRef I3 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00062))
                (portRef I3 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00071))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0003 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor0003")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_4))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00032))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0004 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor0004")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_3))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00041))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0005 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor0005")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_2))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00051))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0006 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor0006")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_1))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00062))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0007 "normgen.flblk/clkmod/cx.wrx/PNTR_B_xor0007")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_0))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00071))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x<8>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x<7>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2<7>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00001))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00011))
                (portRef I2 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00021))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x<6>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2<6>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6))
                (portRef I2 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00011))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00021))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x<5>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2<5>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00021))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x<4>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2<4>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00032))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00041))
                (portRef I2 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00051))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00062))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00071))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x<3>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2<3>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00041))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00051))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00062))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00071))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x<2>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2<2>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00051))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW0))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x<1>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2<1>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW0))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x_0_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x<0>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_0))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_0))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_0_ "normgen.flblk/clkmod/cx.wrx/pntr_gc_x2<0>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_0))
                (portRef I2 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_8_ "normgen.flblk/clkmod/cx.wrx/pntr_gc<8>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_8))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_7_ "normgen.flblk/clkmod/cx.wrx/pntr_gc<7>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_7))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_6_ "normgen.flblk/clkmod/cx.wrx/pntr_gc<6>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_6))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_5_ "normgen.flblk/clkmod/cx.wrx/pntr_gc<5>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_5))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_4_ "normgen.flblk/clkmod/cx.wrx/pntr_gc<4>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_4))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_3_ "normgen.flblk/clkmod/cx.wrx/pntr_gc<3>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_3))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_2_ "normgen.flblk/clkmod/cx.wrx/pntr_gc<2>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_2))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_1_ "normgen.flblk/clkmod/cx.wrx/pntr_gc<1>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_0_ "normgen.flblk/clkmod/cx.wrx/pntr_gc<0>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_x_0))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_0))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0000 "normgen.flblk/clkmod/cx.wrx/pntr_gc_xor0000")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_7))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0000_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0001 "normgen.flblk/clkmod/cx.wrx/pntr_gc_xor0001")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_6))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0001_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0002 "normgen.flblk/clkmod/cx.wrx/pntr_gc_xor0002")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_5))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0002_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0003 "normgen.flblk/clkmod/cx.wrx/pntr_gc_xor0003")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_4))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0003_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0004 "normgen.flblk/clkmod/cx.wrx/pntr_gc_xor0004")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_3))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0004_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0005 "normgen.flblk/clkmod/cx.wrx/pntr_gc_xor0005")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_2))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0005_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0006 "normgen.flblk/clkmod/cx.wrx/pntr_gc_xor0006")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_1))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0006_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0007 "normgen.flblk/clkmod/cx.wrx/pntr_gc_xor0007")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_wrx_pntr_gc_0))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0007_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2<9>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_9))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00001))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00011))
                (portRef I3 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00021))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0000 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor0000")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_8))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00001))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0001 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor0001")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_7))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00011))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor0002")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_6))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00021))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00032))
                (portRef I2 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00041))
                (portRef I3 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00051))
                (portRef I3 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00062))
                (portRef I3 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00071))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0003 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor0003")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_5))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00032))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0004 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor0004")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_4))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00041))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0005 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor0005")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_3))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00051))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0006 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor0006")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_2))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00062))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0007 "normgen.flblk/clkmod/cx.rdx/PNTR_B_xor0007")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_1))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00071))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x<9>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x<8>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2<8>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00001))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00011))
                (portRef I2 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00021))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x<7>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2<7>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7))
                (portRef I2 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00011))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00021))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x<6>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2<6>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00021))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x<5>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2<5>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00032))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00041))
                (portRef I2 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00051))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00062))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00071))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x<4>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2<4>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00041))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00051))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00062))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00071))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x<3>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2<3>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00051))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW0))
                (portRef I0 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x<2>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2<2>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW0))
                (portRef I1 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x<1>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x2<1>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1))
                (portRef I2 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_9_ "normgen.flblk/clkmod/cx.rdx/pntr_gc<9>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_9))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_8_ "normgen.flblk/clkmod/cx.rdx/pntr_gc<8>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_8))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_7_ "normgen.flblk/clkmod/cx.rdx/pntr_gc<7>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_7))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_6_ "normgen.flblk/clkmod/cx.rdx/pntr_gc<6>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_6))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_5_ "normgen.flblk/clkmod/cx.rdx/pntr_gc<5>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_5))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_4_ "normgen.flblk/clkmod/cx.rdx/pntr_gc<4>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_4))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_3_ "normgen.flblk/clkmod/cx.rdx/pntr_gc<3>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_3))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_2_ "normgen.flblk/clkmod/cx.rdx/pntr_gc<2>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_2))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_1_ "normgen.flblk/clkmod/cx.rdx/pntr_gc<1>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_0_ "normgen.flblk/clkmod/cx.rdx/pntr_gc<0>")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_0))
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_0))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_x_0_ "normgen.flblk/clkmod/cx.rdx/pntr_gc_x<0>")
              (joined
                (portRef Q (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_x_0))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0000 "normgen.flblk/clkmod/cx.rdx/pntr_gc_xor0000")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_8))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0000_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0001 "normgen.flblk/clkmod/cx.rdx/pntr_gc_xor0001")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_7))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0001_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0002 "normgen.flblk/clkmod/cx.rdx/pntr_gc_xor0002")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_6))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0002_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0003 "normgen.flblk/clkmod/cx.rdx/pntr_gc_xor0003")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_5))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0003_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0004 "normgen.flblk/clkmod/cx.rdx/pntr_gc_xor0004")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_4))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0004_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0005 "normgen.flblk/clkmod/cx.rdx/pntr_gc_xor0005")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_3))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0005_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0006 "normgen.flblk/clkmod/cx.rdx/pntr_gc_xor0006")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_2))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0006_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0007 "normgen.flblk/clkmod/cx.rdx/pntr_gc_xor0007")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_1))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0007_Result1))
              )
            )
            (net (rename normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0008 "normgen.flblk/clkmod/cx.rdx/pntr_gc_xor0008")
              (joined
                (portRef D (instanceRef normgen_flblk_clkmod_cx_rdx_pntr_gc_0))
                (portRef O (instanceRef normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0008_Result1))
              )
            )
            (net N0
              (joined
                (portRef I2 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00062))
                (portRef LO (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW0))
              )
            )
            (net N2
              (joined
                (portRef I2 (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00071))
                (portRef LO (instanceRef normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1))
              )
            )
            (net N4
              (joined
                (portRef I2 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00062))
                (portRef LO (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW0))
              )
            )
            (net N6
              (joined
                (portRef I2 (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00071))
                (portRef LO (instanceRef normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1))
              )
            )
            (net (rename normgen_memblk_tmp_ram_rd_en "normgen.memblk/tmp_ram_rd_en")
              (joined
                (portRef O (instanceRef normgen_memblk_tmp_ram_rd_en1))
                (portRef ENA (instanceRef normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0__ram_r_v2_ram_dp36x18_ram))
              )
            )
          )
      )
    )
    (cell (rename coregenerator_fifo_send_fifo_generator_v3_3_xst_1_BU2 "coregenerator_fifo_send_fifo_generator_v3_3_xst_1")
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port rd_rst
              (direction INPUT)
            )
            (port prog_full
              (direction OUTPUT)
            )
            (port srst
              (direction INPUT)
            )
            (port almost_empty
              (direction OUTPUT)
            )
            (port valid
              (direction OUTPUT)
            )
            (port backup_marker
              (direction INPUT)
            )
            (port rd_en
              (direction INPUT)
            )
            (port overflow
              (direction OUTPUT)
            )
            (port wr_en
              (direction INPUT)
            )
            (port full
              (direction OUTPUT)
            )
            (port empty
              (direction OUTPUT)
            )
            (port wr_clk
              (direction INPUT)
            )
            (port clk
              (direction INPUT)
            )
            (port wr_rst
              (direction INPUT)
            )
            (port sbiterr
              (direction OUTPUT)
            )
            (port wr_ack
              (direction OUTPUT)
            )
            (port almost_full
              (direction OUTPUT)
            )
            (port underflow
              (direction OUTPUT)
            )
            (port rst
              (direction INPUT)
            )
            (port backup
              (direction INPUT)
            )
            (port prog_empty
              (direction OUTPUT)
            )
            (port dbiterr
              (direction OUTPUT)
            )
            (port rd_clk
              (direction INPUT)
            )
            (port (array (rename prog_empty_thresh_assert "prog_empty_thresh_assert<9:0>") 10)
              (direction INPUT))
            (port (array (rename wr_data_count "wr_data_count<8:0>") 9)
              (direction OUTPUT))
            (port (array (rename rd_data_count "rd_data_count<8:0>") 9)
              (direction OUTPUT))
            (port (array (rename prog_full_thresh_negate "prog_full_thresh_negate<8:0>") 9)
              (direction INPUT))
            (port (array (rename data_count "data_count<8:0>") 9)
              (direction OUTPUT))
            (port (array (rename prog_full_thresh "prog_full_thresh<8:0>") 9)
              (direction INPUT))
            (port (array (rename dout "dout<15:0>") 16)
              (direction OUTPUT))
            (port (array (rename prog_empty_thresh "prog_empty_thresh<9:0>") 10)
              (direction INPUT))
            (port (array (rename din "din<31:0>") 32)
              (direction INPUT))
            (port (array (rename prog_full_thresh_assert "prog_full_thresh_assert<8:0>") 9)
              (direction INPUT))
            (port (array (rename prog_empty_thresh_negate "prog_empty_thresh_negate<9:0>") 10)
              (direction INPUT))
            (property BUS_INFO (string "10:INPUT:prog_empty_thresh_assert<9:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:OUTPUT:wr_data_count<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:OUTPUT:rd_data_count<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:INPUT:prog_full_thresh_negate<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:OUTPUT:data_count<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:INPUT:prog_full_thresh<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "16:OUTPUT:dout<15:0>") (owner "Xilinx"))
            (property BUS_INFO (string "10:INPUT:prog_empty_thresh<9:0>") (owner "Xilinx"))
            (property BUS_INFO (string "32:INPUT:din<31:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:INPUT:prog_full_thresh_assert<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "10:INPUT:prog_empty_thresh_negate<9:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:OUTPUT:data_count<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:OUTPUT:wr_data_count<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "16:OUTPUT:dout<15:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:OUTPUT:rd_data_count<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "10:INPUT:prog_empty_thresh_assert<9:0>") (owner "Xilinx"))
            (property BUS_INFO (string "32:INPUT:din<31:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:INPUT:prog_full_thresh_negate<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:INPUT:prog_full_thresh_assert<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "9:INPUT:prog_full_thresh<8:0>") (owner "Xilinx"))
            (property BUS_INFO (string "10:INPUT:prog_empty_thresh_negate<9:0>") (owner "Xilinx"))
            (property BUS_INFO (string "10:INPUT:prog_empty_thresh<9:0>") (owner "Xilinx"))
            (property TYPE (string "coregenerator_fifo_send_fifo_generator_v3_3_xst_1") (owner "Xilinx"))
            (property IOB (string "False") (owner "Xilinx"))
            (property CHECK_LICENSE_TYPE (string "coregenerator_fifo_send,fifo_generator_v3_3,NONE,NONE") (owner "Xilinx"))
            (property CORE_GENERATION_INFO (string "coregenerator_fifo_send,fifo_generator_v3_3,{c_has_srst=0,c_rd_freq=100,c_has_rd_data_count=0,c_din_width=32,c_has_wr_data_count=0,c_implementation_type=2,c_wr_freq=100,c_underflow_low=0,c_has_overflow=0,c_preload_latency=1,c_dout_width=16,c_rd_depth=1024,c_has_underflow=0,c_has_almost_full=1,c_has_rst=1,c_data_count_width=9,c_has_wr_ack=0,c_use_ecc=0,c_common_clock=0,c_wr_ack_low=0,c_rd_pntr_width=10,c_has_almost_empty=1,c_rd_data_count_width=9,c_overflow_low=0,c_wr_pntr_width=9,c_prog_empty_type=0,c_wr_data_count_width=9,c_preload_regs=0,c_dout_rst_val=0,c_has_data_count=0,c_prog_full_thresh_negate_val=509,c_wr_depth=512,c_prog_empty_thresh_negate_val=4,c_prog_empty_thresh_assert_val=3,c_has_valid=0,c_prog_full_thresh_assert_val=510,component_name=coregenerator_fifo_send,c_valid_low=0,c_prim_fifo_type=512x36,c_prog_full_type=0,c_memory_type=1,}") (owner "Xilinx"))
            (property NB_BUSPIN_PROPS (string "OK") (owner "Xilinx"))
            (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
            (property NLW_MACRO_TAG (integer 1) (owner "Xilinx"))
            (property NLW_MACRO_ALIAS (string "coregenerator_fifo_send_fifo_generator_v3_3_xst_1_BU2") (owner "Xilinx"))
          )
          (contents
            (instance XST_GND
              (viewRef view_1 (cellRef GND (libraryRef UNISIMS)))
              (property XSTLIB (boolean (true)) (owner "Xilinx"))
            )
            (instance (rename U0_gen_as_fgas "U0/gen_as.fgas")
              (viewRef view_1 (cellRef fifo_generator_v3_3_as_U0_gen_as_fgas (libraryRef coregenerator_fifo_send_lib)))
              (property BUS_INFO (string "9:OUTPUT:debug_wr_pntr_r<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:OUTPUT:debug_wr_pntr_w<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "10:OUTPUT:debug_rd_pntr_plus1_r<9:0>") (owner "Xilinx"))
              (property BUS_INFO (string "10:OUTPUT:debug_rd_pntr_r<9:0>") (owner "Xilinx"))
              (property BUS_INFO (string "10:OUTPUT:debug_rd_pntr_w<9:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:OUTPUT:DEBUG_WR_PNTR<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:OUTPUT:WR_DATA_COUNT<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:OUTPUT:debug_wr_pntr_plus1_w<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "10:OUTPUT:DEBUG_RD_PNTR<9:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:OUTPUT:debug_wr_pntr_plus2_w<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "16:OUTPUT:DOUT<15:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:OUTPUT:RD_DATA_COUNT<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "10:INPUT:PROG_EMPTY_THRESH_ASSERT<9:0>") (owner "Xilinx"))
              (property BUS_INFO (string "32:INPUT:DIN<31:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:INPUT:PROG_FULL_THRESH_NEGATE<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:INPUT:PROG_FULL_THRESH_ASSERT<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:INPUT:PROG_FULL_THRESH<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "10:INPUT:PROG_EMPTY_THRESH_NEGATE<9:0>") (owner "Xilinx"))
              (property BUS_INFO (string "10:INPUT:PROG_EMPTY_THRESH<9:0>") (owner "Xilinx"))
              (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
              (property NLW_MACRO_TAG (integer 2) (owner "Xilinx"))
              (property NLW_MACRO_ALIAS (string "fifo_generator_v3_3_as_U0/gen_as.fgas") (owner "Xilinx"))
            )
            (net rd_en
              (joined
                (portRef rd_en)
                (portRef RD_EN (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename NlwRenamedSignal_data_count_0_ "NlwRenamedSignal_data_count<0>")
              (joined
                (portRef dbiterr)
                (portRef sbiterr)
                (portRef (member data_count 0))
                (portRef (member data_count 1))
                (portRef (member data_count 2))
                (portRef (member data_count 3))
                (portRef (member data_count 4))
                (portRef (member data_count 5))
                (portRef (member data_count 6))
                (portRef (member data_count 7))
                (portRef (member data_count 8))
                (portRef G (instanceRef XST_GND))
              )
            )
            (net almost_full
              (joined
                (portRef almost_full)
                (portRef ALMOST_FULL (instanceRef U0_gen_as_fgas))
              )
            )
            (net rst
              (joined
                (portRef rst)
                (portRef RST (instanceRef U0_gen_as_fgas))
              )
            )
            (net wr_ack
              (joined
                (portRef wr_ack)
                (portRef WR_ACK (instanceRef U0_gen_as_fgas))
              )
            )
            (net empty
              (joined
                (portRef empty)
                (portRef EMPTY (instanceRef U0_gen_as_fgas))
              )
            )
            (net wr_en
              (joined
                (portRef wr_en)
                (portRef WR_EN (instanceRef U0_gen_as_fgas))
              )
            )
            (net underflow
              (joined
                (portRef underflow)
                (portRef UNDERFLOW (instanceRef U0_gen_as_fgas))
              )
            )
            (net almost_empty
              (joined
                (portRef almost_empty)
                (portRef ALMOST_EMPTY (instanceRef U0_gen_as_fgas))
              )
            )
            (net rd_clk
              (joined
                (portRef rd_clk)
                (portRef RD_CLK (instanceRef U0_gen_as_fgas))
              )
            )
            (net overflow
              (joined
                (portRef overflow)
                (portRef OVERFLOW (instanceRef U0_gen_as_fgas))
              )
            )
            (net valid
              (joined
                (portRef valid)
                (portRef VALID (instanceRef U0_gen_as_fgas))
              )
            )
            (net full
              (joined
                (portRef full)
                (portRef FULL (instanceRef U0_gen_as_fgas))
              )
            )
            (net prog_empty
              (joined
                (portRef prog_empty)
                (portRef PROG_EMPTY (instanceRef U0_gen_as_fgas))
              )
            )
            (net wr_clk
              (joined
                (portRef wr_clk)
                (portRef WR_CLK (instanceRef U0_gen_as_fgas))
              )
            )
            (net prog_full
              (joined
                (portRef prog_full)
                (portRef PROG_FULL (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename wr_data_count_renamed_64_8_ "wr_data_count<8>")
              (joined
                (portRef (member wr_data_count 0))
                (portRef (member WR_DATA_COUNT 0) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename wr_data_count_renamed_64_7_ "wr_data_count<7>")
              (joined
                (portRef (member wr_data_count 1))
                (portRef (member WR_DATA_COUNT 1) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename wr_data_count_renamed_64_6_ "wr_data_count<6>")
              (joined
                (portRef (member wr_data_count 2))
                (portRef (member WR_DATA_COUNT 2) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename wr_data_count_renamed_64_5_ "wr_data_count<5>")
              (joined
                (portRef (member wr_data_count 3))
                (portRef (member WR_DATA_COUNT 3) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename wr_data_count_renamed_64_4_ "wr_data_count<4>")
              (joined
                (portRef (member wr_data_count 4))
                (portRef (member WR_DATA_COUNT 4) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename wr_data_count_renamed_64_3_ "wr_data_count<3>")
              (joined
                (portRef (member wr_data_count 5))
                (portRef (member WR_DATA_COUNT 5) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename wr_data_count_renamed_64_2_ "wr_data_count<2>")
              (joined
                (portRef (member wr_data_count 6))
                (portRef (member WR_DATA_COUNT 6) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename wr_data_count_renamed_64_1_ "wr_data_count<1>")
              (joined
                (portRef (member wr_data_count 7))
                (portRef (member WR_DATA_COUNT 7) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename wr_data_count_renamed_64_0_ "wr_data_count<0>")
              (joined
                (portRef (member wr_data_count 8))
                (portRef (member WR_DATA_COUNT 8) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_15_ "dout<15>")
              (joined
                (portRef (member dout 0))
                (portRef (member DOUT 0) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_14_ "dout<14>")
              (joined
                (portRef (member dout 1))
                (portRef (member DOUT 1) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_13_ "dout<13>")
              (joined
                (portRef (member dout 2))
                (portRef (member DOUT 2) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_12_ "dout<12>")
              (joined
                (portRef (member dout 3))
                (portRef (member DOUT 3) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_11_ "dout<11>")
              (joined
                (portRef (member dout 4))
                (portRef (member DOUT 4) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_10_ "dout<10>")
              (joined
                (portRef (member dout 5))
                (portRef (member DOUT 5) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_9_ "dout<9>")
              (joined
                (portRef (member dout 6))
                (portRef (member DOUT 6) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_8_ "dout<8>")
              (joined
                (portRef (member dout 7))
                (portRef (member DOUT 7) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_7_ "dout<7>")
              (joined
                (portRef (member dout 8))
                (portRef (member DOUT 8) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_6_ "dout<6>")
              (joined
                (portRef (member dout 9))
                (portRef (member DOUT 9) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_5_ "dout<5>")
              (joined
                (portRef (member dout 10))
                (portRef (member DOUT 10) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_4_ "dout<4>")
              (joined
                (portRef (member dout 11))
                (portRef (member DOUT 11) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_3_ "dout<3>")
              (joined
                (portRef (member dout 12))
                (portRef (member DOUT 12) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_2_ "dout<2>")
              (joined
                (portRef (member dout 13))
                (portRef (member DOUT 13) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_1_ "dout<1>")
              (joined
                (portRef (member dout 14))
                (portRef (member DOUT 14) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename dout_renamed_65_0_ "dout<0>")
              (joined
                (portRef (member dout 15))
                (portRef (member DOUT 15) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename rd_data_count_renamed_66_8_ "rd_data_count<8>")
              (joined
                (portRef (member rd_data_count 0))
                (portRef (member RD_DATA_COUNT 0) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename rd_data_count_renamed_66_7_ "rd_data_count<7>")
              (joined
                (portRef (member rd_data_count 1))
                (portRef (member RD_DATA_COUNT 1) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename rd_data_count_renamed_66_6_ "rd_data_count<6>")
              (joined
                (portRef (member rd_data_count 2))
                (portRef (member RD_DATA_COUNT 2) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename rd_data_count_renamed_66_5_ "rd_data_count<5>")
              (joined
                (portRef (member rd_data_count 3))
                (portRef (member RD_DATA_COUNT 3) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename rd_data_count_renamed_66_4_ "rd_data_count<4>")
              (joined
                (portRef (member rd_data_count 4))
                (portRef (member RD_DATA_COUNT 4) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename rd_data_count_renamed_66_3_ "rd_data_count<3>")
              (joined
                (portRef (member rd_data_count 5))
                (portRef (member RD_DATA_COUNT 5) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename rd_data_count_renamed_66_2_ "rd_data_count<2>")
              (joined
                (portRef (member rd_data_count 6))
                (portRef (member RD_DATA_COUNT 6) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename rd_data_count_renamed_66_1_ "rd_data_count<1>")
              (joined
                (portRef (member rd_data_count 7))
                (portRef (member RD_DATA_COUNT 7) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename rd_data_count_renamed_66_0_ "rd_data_count<0>")
              (joined
                (portRef (member rd_data_count 8))
                (portRef (member RD_DATA_COUNT 8) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_assert_renamed_67_9_ "prog_empty_thresh_assert<9>")
              (joined
                (portRef (member prog_empty_thresh_assert 0))
                (portRef (member PROG_EMPTY_THRESH_ASSERT 0) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_assert_renamed_67_8_ "prog_empty_thresh_assert<8>")
              (joined
                (portRef (member prog_empty_thresh_assert 1))
                (portRef (member PROG_EMPTY_THRESH_ASSERT 1) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_assert_renamed_67_7_ "prog_empty_thresh_assert<7>")
              (joined
                (portRef (member prog_empty_thresh_assert 2))
                (portRef (member PROG_EMPTY_THRESH_ASSERT 2) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_assert_renamed_67_6_ "prog_empty_thresh_assert<6>")
              (joined
                (portRef (member prog_empty_thresh_assert 3))
                (portRef (member PROG_EMPTY_THRESH_ASSERT 3) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_assert_renamed_67_5_ "prog_empty_thresh_assert<5>")
              (joined
                (portRef (member prog_empty_thresh_assert 4))
                (portRef (member PROG_EMPTY_THRESH_ASSERT 4) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_assert_renamed_67_4_ "prog_empty_thresh_assert<4>")
              (joined
                (portRef (member prog_empty_thresh_assert 5))
                (portRef (member PROG_EMPTY_THRESH_ASSERT 5) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_assert_renamed_67_3_ "prog_empty_thresh_assert<3>")
              (joined
                (portRef (member prog_empty_thresh_assert 6))
                (portRef (member PROG_EMPTY_THRESH_ASSERT 6) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_assert_renamed_67_2_ "prog_empty_thresh_assert<2>")
              (joined
                (portRef (member prog_empty_thresh_assert 7))
                (portRef (member PROG_EMPTY_THRESH_ASSERT 7) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_assert_renamed_67_1_ "prog_empty_thresh_assert<1>")
              (joined
                (portRef (member prog_empty_thresh_assert 8))
                (portRef (member PROG_EMPTY_THRESH_ASSERT 8) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_assert_renamed_67_0_ "prog_empty_thresh_assert<0>")
              (joined
                (portRef (member prog_empty_thresh_assert 9))
                (portRef (member PROG_EMPTY_THRESH_ASSERT 9) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_31_ "din<31>")
              (joined
                (portRef (member din 0))
                (portRef (member DIN 0) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_30_ "din<30>")
              (joined
                (portRef (member din 1))
                (portRef (member DIN 1) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_29_ "din<29>")
              (joined
                (portRef (member din 2))
                (portRef (member DIN 2) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_28_ "din<28>")
              (joined
                (portRef (member din 3))
                (portRef (member DIN 3) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_27_ "din<27>")
              (joined
                (portRef (member din 4))
                (portRef (member DIN 4) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_26_ "din<26>")
              (joined
                (portRef (member din 5))
                (portRef (member DIN 5) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_25_ "din<25>")
              (joined
                (portRef (member din 6))
                (portRef (member DIN 6) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_24_ "din<24>")
              (joined
                (portRef (member din 7))
                (portRef (member DIN 7) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_23_ "din<23>")
              (joined
                (portRef (member din 8))
                (portRef (member DIN 8) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_22_ "din<22>")
              (joined
                (portRef (member din 9))
                (portRef (member DIN 9) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_21_ "din<21>")
              (joined
                (portRef (member din 10))
                (portRef (member DIN 10) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_20_ "din<20>")
              (joined
                (portRef (member din 11))
                (portRef (member DIN 11) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_19_ "din<19>")
              (joined
                (portRef (member din 12))
                (portRef (member DIN 12) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_18_ "din<18>")
              (joined
                (portRef (member din 13))
                (portRef (member DIN 13) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_17_ "din<17>")
              (joined
                (portRef (member din 14))
                (portRef (member DIN 14) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_16_ "din<16>")
              (joined
                (portRef (member din 15))
                (portRef (member DIN 15) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_15_ "din<15>")
              (joined
                (portRef (member din 16))
                (portRef (member DIN 16) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_14_ "din<14>")
              (joined
                (portRef (member din 17))
                (portRef (member DIN 17) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_13_ "din<13>")
              (joined
                (portRef (member din 18))
                (portRef (member DIN 18) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_12_ "din<12>")
              (joined
                (portRef (member din 19))
                (portRef (member DIN 19) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_11_ "din<11>")
              (joined
                (portRef (member din 20))
                (portRef (member DIN 20) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_10_ "din<10>")
              (joined
                (portRef (member din 21))
                (portRef (member DIN 21) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_9_ "din<9>")
              (joined
                (portRef (member din 22))
                (portRef (member DIN 22) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_8_ "din<8>")
              (joined
                (portRef (member din 23))
                (portRef (member DIN 23) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_7_ "din<7>")
              (joined
                (portRef (member din 24))
                (portRef (member DIN 24) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_6_ "din<6>")
              (joined
                (portRef (member din 25))
                (portRef (member DIN 25) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_5_ "din<5>")
              (joined
                (portRef (member din 26))
                (portRef (member DIN 26) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_4_ "din<4>")
              (joined
                (portRef (member din 27))
                (portRef (member DIN 27) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_3_ "din<3>")
              (joined
                (portRef (member din 28))
                (portRef (member DIN 28) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_2_ "din<2>")
              (joined
                (portRef (member din 29))
                (portRef (member DIN 29) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_1_ "din<1>")
              (joined
                (portRef (member din 30))
                (portRef (member DIN 30) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename din_renamed_68_0_ "din<0>")
              (joined
                (portRef (member din 31))
                (portRef (member DIN 31) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_negate_renamed_69_8_ "prog_full_thresh_negate<8>")
              (joined
                (portRef (member prog_full_thresh_negate 0))
                (portRef (member PROG_FULL_THRESH_NEGATE 0) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_negate_renamed_69_7_ "prog_full_thresh_negate<7>")
              (joined
                (portRef (member prog_full_thresh_negate 1))
                (portRef (member PROG_FULL_THRESH_NEGATE 1) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_negate_renamed_69_6_ "prog_full_thresh_negate<6>")
              (joined
                (portRef (member prog_full_thresh_negate 2))
                (portRef (member PROG_FULL_THRESH_NEGATE 2) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_negate_renamed_69_5_ "prog_full_thresh_negate<5>")
              (joined
                (portRef (member prog_full_thresh_negate 3))
                (portRef (member PROG_FULL_THRESH_NEGATE 3) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_negate_renamed_69_4_ "prog_full_thresh_negate<4>")
              (joined
                (portRef (member prog_full_thresh_negate 4))
                (portRef (member PROG_FULL_THRESH_NEGATE 4) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_negate_renamed_69_3_ "prog_full_thresh_negate<3>")
              (joined
                (portRef (member prog_full_thresh_negate 5))
                (portRef (member PROG_FULL_THRESH_NEGATE 5) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_negate_renamed_69_2_ "prog_full_thresh_negate<2>")
              (joined
                (portRef (member prog_full_thresh_negate 6))
                (portRef (member PROG_FULL_THRESH_NEGATE 6) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_negate_renamed_69_1_ "prog_full_thresh_negate<1>")
              (joined
                (portRef (member prog_full_thresh_negate 7))
                (portRef (member PROG_FULL_THRESH_NEGATE 7) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_negate_renamed_69_0_ "prog_full_thresh_negate<0>")
              (joined
                (portRef (member prog_full_thresh_negate 8))
                (portRef (member PROG_FULL_THRESH_NEGATE 8) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_assert_renamed_70_8_ "prog_full_thresh_assert<8>")
              (joined
                (portRef (member prog_full_thresh_assert 0))
                (portRef (member PROG_FULL_THRESH_ASSERT 0) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_assert_renamed_70_7_ "prog_full_thresh_assert<7>")
              (joined
                (portRef (member prog_full_thresh_assert 1))
                (portRef (member PROG_FULL_THRESH_ASSERT 1) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_assert_renamed_70_6_ "prog_full_thresh_assert<6>")
              (joined
                (portRef (member prog_full_thresh_assert 2))
                (portRef (member PROG_FULL_THRESH_ASSERT 2) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_assert_renamed_70_5_ "prog_full_thresh_assert<5>")
              (joined
                (portRef (member prog_full_thresh_assert 3))
                (portRef (member PROG_FULL_THRESH_ASSERT 3) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_assert_renamed_70_4_ "prog_full_thresh_assert<4>")
              (joined
                (portRef (member prog_full_thresh_assert 4))
                (portRef (member PROG_FULL_THRESH_ASSERT 4) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_assert_renamed_70_3_ "prog_full_thresh_assert<3>")
              (joined
                (portRef (member prog_full_thresh_assert 5))
                (portRef (member PROG_FULL_THRESH_ASSERT 5) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_assert_renamed_70_2_ "prog_full_thresh_assert<2>")
              (joined
                (portRef (member prog_full_thresh_assert 6))
                (portRef (member PROG_FULL_THRESH_ASSERT 6) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_assert_renamed_70_1_ "prog_full_thresh_assert<1>")
              (joined
                (portRef (member prog_full_thresh_assert 7))
                (portRef (member PROG_FULL_THRESH_ASSERT 7) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_assert_renamed_70_0_ "prog_full_thresh_assert<0>")
              (joined
                (portRef (member prog_full_thresh_assert 8))
                (portRef (member PROG_FULL_THRESH_ASSERT 8) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_renamed_71_8_ "prog_full_thresh<8>")
              (joined
                (portRef (member prog_full_thresh 0))
                (portRef (member PROG_FULL_THRESH 0) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_renamed_71_7_ "prog_full_thresh<7>")
              (joined
                (portRef (member prog_full_thresh 1))
                (portRef (member PROG_FULL_THRESH 1) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_renamed_71_6_ "prog_full_thresh<6>")
              (joined
                (portRef (member prog_full_thresh 2))
                (portRef (member PROG_FULL_THRESH 2) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_renamed_71_5_ "prog_full_thresh<5>")
              (joined
                (portRef (member prog_full_thresh 3))
                (portRef (member PROG_FULL_THRESH 3) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_renamed_71_4_ "prog_full_thresh<4>")
              (joined
                (portRef (member prog_full_thresh 4))
                (portRef (member PROG_FULL_THRESH 4) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_renamed_71_3_ "prog_full_thresh<3>")
              (joined
                (portRef (member prog_full_thresh 5))
                (portRef (member PROG_FULL_THRESH 5) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_renamed_71_2_ "prog_full_thresh<2>")
              (joined
                (portRef (member prog_full_thresh 6))
                (portRef (member PROG_FULL_THRESH 6) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_renamed_71_1_ "prog_full_thresh<1>")
              (joined
                (portRef (member prog_full_thresh 7))
                (portRef (member PROG_FULL_THRESH 7) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_full_thresh_renamed_71_0_ "prog_full_thresh<0>")
              (joined
                (portRef (member prog_full_thresh 8))
                (portRef (member PROG_FULL_THRESH 8) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_negate_renamed_72_9_ "prog_empty_thresh_negate<9>")
              (joined
                (portRef (member prog_empty_thresh_negate 0))
                (portRef (member PROG_EMPTY_THRESH_NEGATE 0) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_negate_renamed_72_8_ "prog_empty_thresh_negate<8>")
              (joined
                (portRef (member prog_empty_thresh_negate 1))
                (portRef (member PROG_EMPTY_THRESH_NEGATE 1) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_negate_renamed_72_7_ "prog_empty_thresh_negate<7>")
              (joined
                (portRef (member prog_empty_thresh_negate 2))
                (portRef (member PROG_EMPTY_THRESH_NEGATE 2) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_negate_renamed_72_6_ "prog_empty_thresh_negate<6>")
              (joined
                (portRef (member prog_empty_thresh_negate 3))
                (portRef (member PROG_EMPTY_THRESH_NEGATE 3) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_negate_renamed_72_5_ "prog_empty_thresh_negate<5>")
              (joined
                (portRef (member prog_empty_thresh_negate 4))
                (portRef (member PROG_EMPTY_THRESH_NEGATE 4) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_negate_renamed_72_4_ "prog_empty_thresh_negate<4>")
              (joined
                (portRef (member prog_empty_thresh_negate 5))
                (portRef (member PROG_EMPTY_THRESH_NEGATE 5) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_negate_renamed_72_3_ "prog_empty_thresh_negate<3>")
              (joined
                (portRef (member prog_empty_thresh_negate 6))
                (portRef (member PROG_EMPTY_THRESH_NEGATE 6) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_negate_renamed_72_2_ "prog_empty_thresh_negate<2>")
              (joined
                (portRef (member prog_empty_thresh_negate 7))
                (portRef (member PROG_EMPTY_THRESH_NEGATE 7) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_negate_renamed_72_1_ "prog_empty_thresh_negate<1>")
              (joined
                (portRef (member prog_empty_thresh_negate 8))
                (portRef (member PROG_EMPTY_THRESH_NEGATE 8) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_negate_renamed_72_0_ "prog_empty_thresh_negate<0>")
              (joined
                (portRef (member prog_empty_thresh_negate 9))
                (portRef (member PROG_EMPTY_THRESH_NEGATE 9) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_renamed_73_9_ "prog_empty_thresh<9>")
              (joined
                (portRef (member prog_empty_thresh 0))
                (portRef (member PROG_EMPTY_THRESH 0) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_renamed_73_8_ "prog_empty_thresh<8>")
              (joined
                (portRef (member prog_empty_thresh 1))
                (portRef (member PROG_EMPTY_THRESH 1) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_renamed_73_7_ "prog_empty_thresh<7>")
              (joined
                (portRef (member prog_empty_thresh 2))
                (portRef (member PROG_EMPTY_THRESH 2) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_renamed_73_6_ "prog_empty_thresh<6>")
              (joined
                (portRef (member prog_empty_thresh 3))
                (portRef (member PROG_EMPTY_THRESH 3) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_renamed_73_5_ "prog_empty_thresh<5>")
              (joined
                (portRef (member prog_empty_thresh 4))
                (portRef (member PROG_EMPTY_THRESH 4) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_renamed_73_4_ "prog_empty_thresh<4>")
              (joined
                (portRef (member prog_empty_thresh 5))
                (portRef (member PROG_EMPTY_THRESH 5) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_renamed_73_3_ "prog_empty_thresh<3>")
              (joined
                (portRef (member prog_empty_thresh 6))
                (portRef (member PROG_EMPTY_THRESH 6) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_renamed_73_2_ "prog_empty_thresh<2>")
              (joined
                (portRef (member prog_empty_thresh 7))
                (portRef (member PROG_EMPTY_THRESH 7) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_renamed_73_1_ "prog_empty_thresh<1>")
              (joined
                (portRef (member prog_empty_thresh 8))
                (portRef (member PROG_EMPTY_THRESH 8) (instanceRef U0_gen_as_fgas))
              )
            )
            (net (rename prog_empty_thresh_renamed_73_0_ "prog_empty_thresh<0>")
              (joined
                (portRef (member prog_empty_thresh 9))
                (portRef (member PROG_EMPTY_THRESH 9) (instanceRef U0_gen_as_fgas))
              )
            )
          )
      )
    )
    (cell coregenerator_fifo_send
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port almost_empty
              (direction OUTPUT)
            )
            (port rd_en
              (direction INPUT)
            )
            (port wr_en
              (direction INPUT)
            )
            (port full
              (direction OUTPUT)
            )
            (port empty
              (direction OUTPUT)
            )
            (port wr_clk
              (direction INPUT)
            )
            (port almost_full
              (direction OUTPUT)
            )
            (port rst
              (direction INPUT)
            )
            (port rd_clk
              (direction INPUT)
            )
            (port (array (rename dout "dout<15:0>") 16)
              (direction OUTPUT))
            (port (array (rename din "din<31:0>") 32)
              (direction INPUT))
            (designator "3s1500fg676-4")
            (property BUS_INFO (string "16:OUTPUT:dout<15:0>") (owner "Xilinx"))
            (property BUS_INFO (string "32:INPUT:din<31:0>") (owner "Xilinx"))
            (property TYPE (string "coregenerator_fifo_send") (owner "Xilinx"))
            (property X_CORE_INFO (string "fifo_generator_v3_3, Xilinx CORE Generator 11.1") (owner "Xilinx"))
            (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
            (property NLW_MACRO_TAG (integer 0) (owner "Xilinx"))
            (property NLW_MACRO_ALIAS (string "coregenerator_fifo_send_coregenerator_fifo_send") (owner "Xilinx"))
          )
          (contents
            (instance (rename VCC_76 "VCC")
              (viewRef view_1 (cellRef VCC (libraryRef UNISIMS)))
            )
            (instance (rename GND_77 "GND")
              (viewRef view_1 (cellRef GND (libraryRef UNISIMS)))
            )
            (instance BU2
              (viewRef view_1 (cellRef coregenerator_fifo_send_fifo_generator_v3_3_xst_1_BU2 (libraryRef coregenerator_fifo_send_lib)))
              (property BUS_INFO (string "10:INPUT:prog_empty_thresh_assert<9:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:OUTPUT:wr_data_count<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:OUTPUT:rd_data_count<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:INPUT:prog_full_thresh_negate<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:OUTPUT:data_count<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:INPUT:prog_full_thresh<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "16:OUTPUT:dout<15:0>") (owner "Xilinx"))
              (property BUS_INFO (string "10:INPUT:prog_empty_thresh<9:0>") (owner "Xilinx"))
              (property BUS_INFO (string "32:INPUT:din<31:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:INPUT:prog_full_thresh_assert<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "10:INPUT:prog_empty_thresh_negate<9:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:OUTPUT:data_count<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:OUTPUT:wr_data_count<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "16:OUTPUT:dout<15:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:OUTPUT:rd_data_count<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "10:INPUT:prog_empty_thresh_assert<9:0>") (owner "Xilinx"))
              (property BUS_INFO (string "32:INPUT:din<31:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:INPUT:prog_full_thresh_negate<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:INPUT:prog_full_thresh_assert<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "9:INPUT:prog_full_thresh<8:0>") (owner "Xilinx"))
              (property BUS_INFO (string "10:INPUT:prog_empty_thresh_negate<9:0>") (owner "Xilinx"))
              (property BUS_INFO (string "10:INPUT:prog_empty_thresh<9:0>") (owner "Xilinx"))
              (property IOB (string "False") (owner "Xilinx"))
              (property CHECK_LICENSE_TYPE (string "coregenerator_fifo_send,fifo_generator_v3_3,NONE,NONE") (owner "Xilinx"))
              (property CORE_GENERATION_INFO (string "coregenerator_fifo_send,fifo_generator_v3_3,{c_has_srst=0,c_rd_freq=100,c_has_rd_data_count=0,c_din_width=32,c_has_wr_data_count=0,c_implementation_type=2,c_wr_freq=100,c_underflow_low=0,c_has_overflow=0,c_preload_latency=1,c_dout_width=16,c_rd_depth=1024,c_has_underflow=0,c_has_almost_full=1,c_has_rst=1,c_data_count_width=9,c_has_wr_ack=0,c_use_ecc=0,c_common_clock=0,c_wr_ack_low=0,c_rd_pntr_width=10,c_has_almost_empty=1,c_rd_data_count_width=9,c_overflow_low=0,c_wr_pntr_width=9,c_prog_empty_type=0,c_wr_data_count_width=9,c_preload_regs=0,c_dout_rst_val=0,c_has_data_count=0,c_prog_full_thresh_negate_val=509,c_wr_depth=512,c_prog_empty_thresh_negate_val=4,c_prog_empty_thresh_assert_val=3,c_has_valid=0,c_prog_full_thresh_assert_val=510,component_name=coregenerator_fifo_send,c_valid_low=0,c_prim_fifo_type=512x36,c_prog_full_type=0,c_memory_type=1,}") (owner "Xilinx"))
              (property NB_BUSPIN_PROPS (string "OK") (owner "Xilinx"))
              (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
              (property NLW_MACRO_TAG (integer 1) (owner "Xilinx"))
              (property NLW_MACRO_ALIAS (string "coregenerator_fifo_send_fifo_generator_v3_3_xst_1_BU2") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_31_ "din<31>")
              (joined
                (portRef (member din 0))
                (portRef (member din 0) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N5") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_30_ "din<30>")
              (joined
                (portRef (member din 1))
                (portRef (member din 1) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N6") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_29_ "din<29>")
              (joined
                (portRef (member din 2))
                (portRef (member din 2) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N7") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_28_ "din<28>")
              (joined
                (portRef (member din 3))
                (portRef (member din 3) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N8") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_27_ "din<27>")
              (joined
                (portRef (member din 4))
                (portRef (member din 4) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N9") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_26_ "din<26>")
              (joined
                (portRef (member din 5))
                (portRef (member din 5) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N10") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_25_ "din<25>")
              (joined
                (portRef (member din 6))
                (portRef (member din 6) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N11") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_24_ "din<24>")
              (joined
                (portRef (member din 7))
                (portRef (member din 7) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N12") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_23_ "din<23>")
              (joined
                (portRef (member din 8))
                (portRef (member din 8) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N13") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_22_ "din<22>")
              (joined
                (portRef (member din 9))
                (portRef (member din 9) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N14") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_21_ "din<21>")
              (joined
                (portRef (member din 10))
                (portRef (member din 10) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N15") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_20_ "din<20>")
              (joined
                (portRef (member din 11))
                (portRef (member din 11) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N16") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_19_ "din<19>")
              (joined
                (portRef (member din 12))
                (portRef (member din 12) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N17") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_18_ "din<18>")
              (joined
                (portRef (member din 13))
                (portRef (member din 13) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N18") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_17_ "din<17>")
              (joined
                (portRef (member din 14))
                (portRef (member din 14) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N19") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_16_ "din<16>")
              (joined
                (portRef (member din 15))
                (portRef (member din 15) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N20") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_15_ "din<15>")
              (joined
                (portRef (member din 16))
                (portRef (member din 16) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N21") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_14_ "din<14>")
              (joined
                (portRef (member din 17))
                (portRef (member din 17) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N22") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_13_ "din<13>")
              (joined
                (portRef (member din 18))
                (portRef (member din 18) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N23") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_12_ "din<12>")
              (joined
                (portRef (member din 19))
                (portRef (member din 19) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N24") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_11_ "din<11>")
              (joined
                (portRef (member din 20))
                (portRef (member din 20) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N25") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_10_ "din<10>")
              (joined
                (portRef (member din 21))
                (portRef (member din 21) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N26") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_9_ "din<9>")
              (joined
                (portRef (member din 22))
                (portRef (member din 22) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N27") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_8_ "din<8>")
              (joined
                (portRef (member din 23))
                (portRef (member din 23) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N28") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_7_ "din<7>")
              (joined
                (portRef (member din 24))
                (portRef (member din 24) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N29") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_6_ "din<6>")
              (joined
                (portRef (member din 25))
                (portRef (member din 25) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N30") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_5_ "din<5>")
              (joined
                (portRef (member din 26))
                (portRef (member din 26) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N31") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_4_ "din<4>")
              (joined
                (portRef (member din 27))
                (portRef (member din 27) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N32") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_3_ "din<3>")
              (joined
                (portRef (member din 28))
                (portRef (member din 28) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N33") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_2_ "din<2>")
              (joined
                (portRef (member din 29))
                (portRef (member din 29) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N34") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_1_ "din<1>")
              (joined
                (portRef (member din 30))
                (portRef (member din 30) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N35") (owner "Xilinx"))
            )
            (net (rename din_renamed_74_0_ "din<0>")
              (joined
                (portRef (member din 31))
                (portRef (member din 31) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N36") (owner "Xilinx"))
            )
            (net rd_clk
              (joined
                (portRef rd_clk)
                (portRef rd_clk (instanceRef BU2))
              )
              (property USER_ALIAS (string "N94") (owner "Xilinx"))
            )
            (net rd_en
              (joined
                (portRef rd_en)
                (portRef rd_en (instanceRef BU2))
              )
              (property USER_ALIAS (string "N95") (owner "Xilinx"))
            )
            (net rst
              (joined
                (portRef rst)
                (portRef rst (instanceRef BU2))
              )
              (property USER_ALIAS (string "N97") (owner "Xilinx"))
            )
            (net wr_clk
              (joined
                (portRef wr_clk)
                (portRef wr_clk (instanceRef BU2))
              )
              (property USER_ALIAS (string "N99") (owner "Xilinx"))
            )
            (net wr_en
              (joined
                (portRef wr_en)
                (portRef wr_en (instanceRef BU2))
              )
              (property USER_ALIAS (string "N100") (owner "Xilinx"))
            )
            (net almost_empty
              (joined
                (portRef almost_empty)
                (portRef almost_empty (instanceRef BU2))
              )
              (property USER_ALIAS (string "N102") (owner "Xilinx"))
            )
            (net almost_full
              (joined
                (portRef almost_full)
                (portRef almost_full (instanceRef BU2))
              )
              (property USER_ALIAS (string "N103") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_15_ "dout<15>")
              (joined
                (portRef (member dout 0))
                (portRef (member dout 0) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N113") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_14_ "dout<14>")
              (joined
                (portRef (member dout 1))
                (portRef (member dout 1) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N114") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_13_ "dout<13>")
              (joined
                (portRef (member dout 2))
                (portRef (member dout 2) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N115") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_12_ "dout<12>")
              (joined
                (portRef (member dout 3))
                (portRef (member dout 3) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N116") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_11_ "dout<11>")
              (joined
                (portRef (member dout 4))
                (portRef (member dout 4) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N117") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_10_ "dout<10>")
              (joined
                (portRef (member dout 5))
                (portRef (member dout 5) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N118") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_9_ "dout<9>")
              (joined
                (portRef (member dout 6))
                (portRef (member dout 6) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N119") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_8_ "dout<8>")
              (joined
                (portRef (member dout 7))
                (portRef (member dout 7) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N120") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_7_ "dout<7>")
              (joined
                (portRef (member dout 8))
                (portRef (member dout 8) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N121") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_6_ "dout<6>")
              (joined
                (portRef (member dout 9))
                (portRef (member dout 9) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N122") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_5_ "dout<5>")
              (joined
                (portRef (member dout 10))
                (portRef (member dout 10) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N123") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_4_ "dout<4>")
              (joined
                (portRef (member dout 11))
                (portRef (member dout 11) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N124") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_3_ "dout<3>")
              (joined
                (portRef (member dout 12))
                (portRef (member dout 12) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N125") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_2_ "dout<2>")
              (joined
                (portRef (member dout 13))
                (portRef (member dout 13) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N126") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_1_ "dout<1>")
              (joined
                (portRef (member dout 14))
                (portRef (member dout 14) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N127") (owner "Xilinx"))
            )
            (net (rename dout_renamed_75_0_ "dout<0>")
              (joined
                (portRef (member dout 15))
                (portRef (member dout 15) (instanceRef BU2))
              )
              (property USER_ALIAS (string "N128") (owner "Xilinx"))
            )
            (net empty
              (joined
                (portRef empty)
                (portRef empty (instanceRef BU2))
              )
              (property USER_ALIAS (string "N129") (owner "Xilinx"))
            )
            (net full
              (joined
                (portRef full)
                (portRef full (instanceRef BU2))
              )
              (property USER_ALIAS (string "N130") (owner "Xilinx"))
            )
          )
      )
    )
  )

  (design coregenerator_fifo_send
    (cellRef coregenerator_fifo_send
      (libraryRef coregenerator_fifo_send_lib)
    )
  )
)