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COPYRIGHT (c) 2006, 2007 XILINX, INC.
ALL RIGHTS RESERVED

Core name            : FIFO Generator 
Version              : v3.3 rev 1
Release Date         : April 2, 2007
File                 : fifo_generator_release_notes.txt

Revision History
Date     By            Version   Change Description
========================================================================
09/2006  Xilinx, Inc.  3.2       Initial creation.
02/2007  Xilinx, Inc.  3.3       Revised for v3.3.
02/2007  Xilinx, Inc.  3.3       Revised for v3.3 rev 1.
========================================================================

INTRODUCTION
RELEASE NOTES
  1. General Core Design
    1.1 Enhancements
    1.2 Resolved Issues
    1.3 Outstanding Issues
  2. General Simulation
    2.1 Enhancements
    2.2 Resolved Issues
    2.3 Outstanding Issues
  3. Documentation
    3.1 Enhancements
    3.2 Resolved Issues
    3.3 Outstanding Issues
OTHER GENERAL INFORMATION
TECHNICAL SUPPORT

========================================================================

INTRODUCTION
============
Thank you using the FIFO Generator core from Xilinx!  
In order to obtain the latest core updates and documentation, 
please visit the Intellectual Property page located at:
http://www.xilinx.com/ipcenter/index.htm
This document contains the release notes for FIFO Generator v3.3
which includes enhancements, resolved issues and outstanding known
issues.  For release notes and known issues for CORE Generator 9.1i IP
Update 1 and FIFO Generator v3.3 please see Answer Record 234307.

RELEASE NOTES
=============
This section lists any enhancements, resolved issues and outstanding
known issues.


1. General Core Design
  1.1 Enhancements
    1.1.1 Spartan(TM)-3A DSP support

    1.1.2 Added Support for Error Correction Checking (ECC) feature for 
          Virtex-5 Built-In FIFO configuration.

  1.2 Resolved Issues
    1.2.1 Coregen GUI - For Block RAM and Distributed RAM FIFOs, if the 
          reset pin is not chosen, the reset type text in page 6 of the 
          GUI (summary) is displayed as "Asynchronous" instead of 
          "Not Selected".
          Change request: 423076

    1.2.2 Programmable full threshold assert range is incorrect for 
          independent clock Block RAM configurations.
          Change request: 422495

    
    1.2.3 "ERROR:LIT:250 - Pins WEA0, WEA1, WEA2, WEA3 of RAMB16 symbol
          .. , these pins should be connected to the same signal" occur
          during MAP when targeting Virtex-4 and Virtex-5.
          Change request: 419562, 430838

  1.3 Outstanding Issues
    1.3.1 "WARNING:Ngdbuild:452 - logical net 
          'u1/BU2/prog_*_thresh_assert<*>' has no driver" occur during 
          NgdBuild although programmable empty or full is not selected.          
          Warnings can be safely ignored.
          Change request: 431975

2. General Simulation
  2.1 Enhancements
      None at this time.

  2.2 Resolved Issues
      None at this time.

  2.3 Outstanding Issues
    2.3.1 Ncelab warnings during Verilog structural and timing simulations 
          in ncsim for Virtex5 Block RAM FIFOs. 
          The simulations will be successful, but there will be warnings 
          similar to the following in the log file: "memory index out of 
          declared bounds" in simprims_ver_virtex5_source.v or 
          unisims_ver_virtex5_source.v.  Cadence does not want to fix this 
          issue. These warning messages can safely be ignored.
          Change request: 423374, 423375

3. Documentation
  3.1 Enhancements
    3.1.1 Added clarification on the WR_DATA_COUNT and RD_DATA_COUNT description.
          Change request: 4328061

  3.2 Resolved Issues
      None at this time.
      
  3.3 Outstanding Issues
      None at this time.


TECHNICAL SUPPORT
=================
The fastest method for obtaining specific technical support for the 
FIFO Generator core is through the http://support.xilinx.com/
website. Questions are routed to a team of engineers with specific
expertise in using the Block Memory Generator core.  Xilinx will provide
technical support for use of this product as described in the Block
Memory Generator Datasheet. Xilinx cannot guarantee timing,
functionality, or support of this product for designs that do not
follow these guidelines.