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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [netgen/] [par/] [USB_TMC_IP_timesim.vhd] - Rev 26
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-------------------------------------------------------------------------------- -- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: J.33 -- \ \ Application: netgen -- / / Filename: USB_TMC_IP_timesim.vhd -- /___/ /\ Timestamp: Mon Jun 15 19:04:35 2009 -- \ \ / \ -- \___\/\___\ -- -- Command : -intstyle ise -s 4 -pcf USB_TMC_IP.pcf -rpw 100 -tpw 0 -ar Structure -tm USB_TMC_IP -insert_pp_buffers false -w -dir netgen/par -ofmt vhdl -sim USB_TMC_IP.ncd USB_TMC_IP_timesim.vhd -- Device : 3s1500fg676-4 (PRODUCTION 1.39 2006-10-19) -- Input file : USB_TMC_IP.ncd -- Output file : /home/habea2/Geccko3com/gecko3com_v04/netgen/par/USB_TMC_IP_timesim.vhd -- # of Entities : 1 -- Design Name : USB_TMC_IP -- Xilinx : /opt/xilinx/ise_91i -- -- Purpose: -- This VHDL netlist is a verification model and uses simulation -- primitives which may not represent the true implementation of the -- device, however the netlist is functionally correct and should not -- be modified. This file cannot be synthesized and should only be used -- with supported simulation tools. -- -- Reference: -- Development System Reference Guide, Chapter 23 -- Synthesis and Simulation Design Guide, Chapter 6 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library SIMPRIM; use SIMPRIM.VCOMPONENTS.ALL; use SIMPRIM.VPACKAGE.ALL; entity USB_TMC_IP is port ( i_nReset : in STD_LOGIC := 'X'; o_LEDrx : out STD_LOGIC; o_LEDtx : out STD_LOGIC; o_WRX : out STD_LOGIC; i_RDYU : in STD_LOGIC := 'X'; o_RDYX : out STD_LOGIC; i_WRU : in STD_LOGIC := 'X'; i_SYSCLK : in STD_LOGIC := 'X'; i_IFCLK : in STD_LOGIC := 'X'; o_LEDrun : out STD_LOGIC; b_dbus : inout STD_LOGIC_VECTOR ( 15 downto 0 ) ); end USB_TMC_IP; architecture Structure of USB_TMC_IP is signal GLOBAL_LOGIC1 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2 : STD_LOGIC; signal GLOBAL_LOGIC0 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0 : STD_LOGIC; signal i_SYSCLK_BUFGP : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0 : STD_LOGIC; signal i_IFCLK_BUFGP : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q : STD_LOGIC; signal F_IN_full : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb : STD_LOGIC; signal i_WRU_IBUF_2 : STD_LOGIC; signal i_RDYU_IBUF_3 : STD_LOGIC; signal FSM_GPIF_s_bus_trans_dir_inv_0 : STD_LOGIC; signal i_nReset_IBUF_4 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en_0 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en_0 : STD_LOGIC; signal s_X2U_EMPTY : STD_LOGIC; signal FSM_GPIF_pr_state_FFd1_5 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd4_6 : STD_LOGIC; signal s_X2U_RD_EN : STD_LOGIC; signal FSM_GPIF_pr_state_FFd3_7 : STD_LOGIC; signal s_U2X_AM_FULL : STD_LOGIC; signal FSM_GPIF_pr_state_FFd4_In_map18 : STD_LOGIC; signal s_X2U_AM_FULL : STD_LOGIC; signal Loopback_pr_stateLoop_FFd3_8 : STD_LOGIC; signal Loopback_pr_stateLoop_FFd2_9 : STD_LOGIC; signal s_U2X_EMPTY : STD_LOGIC; signal s_U2X_AM_EMPTY : STD_LOGIC; signal FSM_GPIF_o_RDYX_map9_0 : STD_LOGIC; signal FSM_GPIF_o_RDYX_map19_0 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd2_10 : STD_LOGIC; signal N4 : STD_LOGIC; signal N124_0 : STD_LOGIC; signal FSM_GPIF_v_setup_not0001_0 : STD_LOGIC; signal FSM_GPIF_pr_state_not0001_0 : STD_LOGIC; signal N350_0 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd3_In98_SW0_O : STD_LOGIC; signal FSM_GPIF_pr_state_FFd3_In_map22_0 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd3_In_map18_0 : STD_LOGIC; signal FSM_GPIF_Mcount_v_setup_eqn_332_O : STD_LOGIC; signal FSM_GPIF_Mcount_v_setup_eqn_3_map16_0 : STD_LOGIC; signal N23 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd4_In13_O : STD_LOGIC; signal FSM_GPIF_pr_state_FFd4_In_map30_0 : STD_LOGIC; signal FSM_GPIF_o_RDYX_map2_0 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1_O : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1_O : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002 : STD_LOGIC; signal FSM_GPIF_Mcount_v_setup_eqn_3_map0 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1_O : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1_O : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd2_In5_O : STD_LOGIC; signal FSM_GPIF_pr_state_FFd2_In_map8_0 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_N86_0 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_N86_0 : STD_LOGIC; signal F_OUT_full : STD_LOGIC; signal s_X2U_WR_EN : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_N90_0 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_N90_0 : STD_LOGIC; signal N120_0 : STD_LOGIC; signal s_U2X_RD_EN : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd4_In_map29 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_11 : STD_LOGIC; signal s_FIFOrst_0 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_12 : STD_LOGIC; signal N90_0 : STD_LOGIC; signal N89 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_13 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_14 : STD_LOGIC; signal N30_0 : STD_LOGIC; signal N31 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYINIT_15 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELF_16 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYMUXG_17 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_LOGIC_ZERO_18 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELG_19 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELF_20 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXFAST_21 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYAND_22 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_FASTCARRY_23 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXG2_24 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXF2_25 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_LOGIC_ZERO_26 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELG_27 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_LOGIC_ZERO_28 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYINIT_29 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYSELF_30 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYINIT_31 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELF_32 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYMUXG_33 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_LOGIC_ZERO_34 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELG_35 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELF_36 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXFAST_37 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYAND_38 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_FASTCARRY_39 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXG2_40 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXF2_41 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_LOGIC_ZERO_42 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELG_43 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_LOGIC_ZERO_44 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYINIT_45 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYSELF_46 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYINIT_47 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELF_48 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYMUXG_49 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_LOGIC_ZERO_50 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELG_51 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELF_52 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXFAST_53 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYAND_54 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_FASTCARRY_55 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXG2_56 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXF2_57 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_LOGIC_ZERO_58 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELG_59 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_LOGIC_ZERO_60 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYINIT_61 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYSELF_62 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYINIT_63 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELF_64 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYMUXG_65 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_LOGIC_ZERO_66 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELG_67 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELF_68 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXFAST_69 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYAND_70 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_FASTCARRY_71 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXG2_72 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXF2_73 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_LOGIC_ZERO_74 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELG_75 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_LOGIC_ZERO_76 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYINIT_77 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYSELF_78 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYINIT_79 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELF_80 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYMUXG_81 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_LOGIC_ZERO_82 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELG_83 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELF_84 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXFAST_85 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYAND_86 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_FASTCARRY_87 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXG2_88 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXF2_89 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_LOGIC_ZERO_90 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELG_91 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_LOGIC_ZERO_92 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYINIT_93 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYSELF_94 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYINIT_95 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELF_96 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYMUXG_97 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_LOGIC_ZERO_98 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELG_99 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELF_100 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXFAST_101 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYAND_102 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_FASTCARRY_103 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXG2_104 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXF2_105 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_LOGIC_ZERO_106 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELG_107 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_LOGIC_ZERO_108 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYINIT_109 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYSELF_110 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYINIT_111 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYSELF_112 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYMUXG_113 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_LOGIC_ZERO_114 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYSELG_115 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYSELF_116 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYMUXFAST_117 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYAND_118 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_FASTCARRY_119 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYMUXG2_120 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYMUXF2_121 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_LOGIC_ZERO_122 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYSELG_123 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2_LOGIC_ZERO_124 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2_CYINIT_125 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2_CYSELF_126 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYINIT_127 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYSELF_128 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYMUXG_129 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_LOGIC_ZERO_130 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYSELG_131 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYSELF_132 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYMUXFAST_133 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYAND_134 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_FASTCARRY_135 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYMUXG2_136 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYMUXF2_137 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_LOGIC_ZERO_138 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYSELG_139 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1_LOGIC_ZERO_140 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1_CYINIT_141 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1_CYSELF_142 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYINIT_143 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELF_144 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYMUXG_145 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_LOGIC_ZERO_146 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELG_147 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELF_148 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXFAST_149 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYAND_150 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_FASTCARRY_151 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXG2_152 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXF2_153 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_LOGIC_ZERO_154 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELG_155 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_LOGIC_ZERO_156 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYINIT_157 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYSELF_158 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYINIT_159 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELF_160 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYMUXG_161 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_LOGIC_ZERO_162 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELG_163 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELF_164 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXFAST_165 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYAND_166 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_FASTCARRY_167 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXG2_168 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXF2_169 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_LOGIC_ZERO_170 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELG_171 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_LOGIC_ZERO_172 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYINIT_173 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYSELF_174 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYINIT_175 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELF_176 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYMUXG_177 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_LOGIC_ZERO_178 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELG_179 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELF_180 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXFAST_181 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYAND_182 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_FASTCARRY_183 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXG2_184 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXF2_185 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_LOGIC_ZERO_186 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELG_187 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_LOGIC_ZERO_188 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYINIT_189 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYSELF_190 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYINIT_191 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELF_192 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYMUXG_193 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_LOGIC_ZERO_194 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELG_195 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELF_196 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXFAST_197 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYAND_198 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_FASTCARRY_199 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXG2_200 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXF2_201 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_LOGIC_ZERO_202 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELG_203 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_LOGIC_ZERO_204 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYINIT_205 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYSELF_206 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYINIT_207 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELF_208 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYMUXG_209 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_LOGIC_ZERO_210 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELG_211 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELF_212 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXFAST_213 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYAND_214 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_FASTCARRY_215 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXG2_216 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXF2_217 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_LOGIC_ZERO_218 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELG_219 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_LOGIC_ZERO_220 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYINIT_221 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYSELF_222 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYINIT_223 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELF_224 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYMUXG_225 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_LOGIC_ZERO_226 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELG_227 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELF_228 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXFAST_229 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYAND_230 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_FASTCARRY_231 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXG2_232 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXF2_233 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_LOGIC_ZERO_234 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELG_235 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_LOGIC_ZERO_236 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYINIT_237 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYSELF_238 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DXMUX_239 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ONE_240 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYINIT_241 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELF_242 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DYMUX_243 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_XORG_244 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYMUXG_245 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ZERO_246 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELG_247 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_SRINV_248 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CLKINV_249 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CEINV_250 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DXMUX_251 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORF_252 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYINIT_253 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DYMUX_254 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORG_255 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELF_256 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXFAST_257 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYAND_258 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_FASTCARRY_259 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXG2_260 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXF2_261 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_LOGIC_ZERO_262 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELG_263 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_SRINV_264 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CLKINV_265 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CEINV_266 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DXMUX_267 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORF_268 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYINIT_269 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DYMUX_270 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORG_271 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELF_272 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXFAST_273 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYAND_274 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_FASTCARRY_275 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXG2_276 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXF2_277 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_LOGIC_ZERO_278 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELG_279 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_SRINV_280 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CLKINV_281 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CEINV_282 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DXMUX_283 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORF_284 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYINIT_285 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DYMUX_286 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORG_287 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELF_288 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXFAST_289 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYAND_290 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_FASTCARRY_291 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXG2_292 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXF2_293 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_LOGIC_ZERO_294 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELG_295 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_SRINV_296 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CLKINV_297 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CEINV_298 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_DXMUX_299 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_XORF_300 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CYINIT_301 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_rt_302 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CLKINV_303 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CEINV_304 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DXMUX_305 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ONE_306 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYINIT_307 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELF_308 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DYMUX_309 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_XORG_310 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYMUXG_311 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ZERO_312 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELG_313 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_SRINV_314 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CLKINV_315 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CEINV_316 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DXMUX_317 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORF_318 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYINIT_319 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DYMUX_320 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORG_321 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELF_322 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXFAST_323 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYAND_324 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_FASTCARRY_325 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXG2_326 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXF2_327 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_LOGIC_ZERO_328 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELG_329 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_SRINV_330 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CLKINV_331 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CEINV_332 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DXMUX_333 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORF_334 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYINIT_335 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DYMUX_336 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORG_337 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELF_338 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXFAST_339 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYAND_340 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_FASTCARRY_341 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXG2_342 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXF2_343 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_LOGIC_ZERO_344 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELG_345 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_SRINV_346 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CLKINV_347 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CEINV_348 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DXMUX_349 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORF_350 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYINIT_351 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DYMUX_352 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORG_353 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELF_354 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXFAST_355 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYAND_356 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_FASTCARRY_357 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXG2_358 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXF2_359 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_LOGIC_ZERO_360 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELG_361 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_SRINV_362 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CLKINV_363 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CEINV_364 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_DXMUX_365 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_XORF_366 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CYINIT_367 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_rt_368 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CLKINV_369 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CEINV_370 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DXMUX_371 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ONE_372 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYINIT_373 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELF_374 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DYMUX_375 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_XORG_376 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYMUXG_377 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ZERO_378 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELG_379 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_SRINV_380 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CLKINV_381 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CEINV_382 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DXMUX_383 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORF_384 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYINIT_385 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DYMUX_386 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORG_387 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELF_388 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXFAST_389 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYAND_390 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_FASTCARRY_391 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXG2_392 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXF2_393 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_LOGIC_ZERO_394 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELG_395 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_SRINV_396 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CLKINV_397 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CEINV_398 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DXMUX_399 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORF_400 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYINIT_401 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DYMUX_402 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORG_403 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELF_404 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXFAST_405 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYAND_406 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_FASTCARRY_407 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXG2_408 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXF2_409 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_LOGIC_ZERO_410 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELG_411 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_SRINV_412 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CLKINV_413 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CEINV_414 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DXMUX_415 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORF_416 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYINIT_417 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DYMUX_418 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORG_419 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELF_420 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXFAST_421 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYAND_422 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_FASTCARRY_423 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXG2_424 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXF2_425 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_LOGIC_ZERO_426 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELG_427 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_SRINV_428 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CLKINV_429 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CEINV_430 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_DXMUX_431 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_XORF_432 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CYINIT_433 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_rt_434 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CLKINV_435 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CEINV_436 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DXMUX_437 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ONE_438 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYINIT_439 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELF_440 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DYMUX_441 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_XORG_442 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYMUXG_443 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ZERO_444 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELG_445 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_SRINV_446 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CLKINV_447 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CEINV_448 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DXMUX_449 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORF_450 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYINIT_451 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DYMUX_452 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORG_453 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF_454 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXFAST_455 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYAND_456 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_FASTCARRY_457 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXG2_458 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXF2_459 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_460 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELG_461 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_SRINV_462 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CLKINV_463 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CEINV_464 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DXMUX_465 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORF_466 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYINIT_467 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DYMUX_468 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORG_469 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF_470 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXFAST_471 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYAND_472 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_FASTCARRY_473 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXG2_474 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXF2_475 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_476 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELG_477 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_SRINV_478 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CLKINV_479 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CEINV_480 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DXMUX_481 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORF_482 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYINIT_483 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DYMUX_484 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORG_485 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF_486 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXFAST_487 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYAND_488 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_FASTCARRY_489 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXG2_490 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXF2_491 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_492 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELG_493 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_SRINV_494 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CLKINV_495 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CEINV_496 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DXMUX_497 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORF_498 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYINIT_499 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_rt_500 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CLKINV_501 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CEINV_502 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DXMUX_503 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ONE_504 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYINIT_505 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELF_506 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DYMUX_507 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_XORG_508 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYMUXG_509 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ZERO_510 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELG_511 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_SRINV_512 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CLKINV_513 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CEINV_514 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DXMUX_515 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORF_516 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYINIT_517 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DYMUX_518 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORG_519 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELF_520 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXFAST_521 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYAND_522 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_FASTCARRY_523 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXG2_524 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXF2_525 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_LOGIC_ZERO_526 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELG_527 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_SRINV_528 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CLKINV_529 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CEINV_530 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DXMUX_531 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORF_532 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYINIT_533 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DYMUX_534 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORG_535 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELF_536 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXFAST_537 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYAND_538 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_FASTCARRY_539 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXG2_540 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXF2_541 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_LOGIC_ZERO_542 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELG_543 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_SRINV_544 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CLKINV_545 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CEINV_546 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DXMUX_547 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORF_548 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYINIT_549 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DYMUX_550 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORG_551 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELF_552 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXFAST_553 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYAND_554 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_FASTCARRY_555 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXG2_556 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXF2_557 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_LOGIC_ZERO_558 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELG_559 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_SRINV_560 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CLKINV_561 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CEINV_562 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_DXMUX_563 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_XORF_564 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_LOGIC_ZERO_565 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CYINIT_566 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CYSELF_567 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_DYMUX_568 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_XORG_569 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_9_rt_570 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_SRINV_571 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CLKINV_572 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CEINV_573 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DXMUX_574 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ONE_575 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYINIT_576 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELF_577 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DYMUX_578 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_XORG_579 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYMUXG_580 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ZERO_581 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELG_582 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_SRINV_583 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CLKINV_584 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CEINV_585 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DXMUX_586 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORF_587 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYINIT_588 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DYMUX_589 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORG_590 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELF_591 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXFAST_592 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYAND_593 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_FASTCARRY_594 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXG2_595 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXF2_596 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_LOGIC_ZERO_597 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELG_598 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_SRINV_599 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CLKINV_600 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CEINV_601 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DXMUX_602 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORF_603 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYINIT_604 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DYMUX_605 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORG_606 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELF_607 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXFAST_608 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYAND_609 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_FASTCARRY_610 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXG2_611 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXF2_612 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_LOGIC_ZERO_613 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELG_614 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_SRINV_615 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CLKINV_616 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CEINV_617 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DXMUX_618 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORF_619 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYINIT_620 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DYMUX_621 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORG_622 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELF_623 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXFAST_624 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYAND_625 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_FASTCARRY_626 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXG2_627 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXF2_628 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_LOGIC_ZERO_629 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELG_630 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_G : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_SRINV_631 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CLKINV_632 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CEINV_633 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_DXMUX_634 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_XORF_635 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_LOGIC_ZERO_636 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CYINIT_637 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CYSELF_638 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_F : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_DYMUX_639 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_XORG_640 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_9_rt_641 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_SRINV_642 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CLKINV_643 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CEINV_644 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DXMUX_645 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ONE_646 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYINIT_647 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELF_648 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DYMUX_649 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_XORG_650 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYMUXG_651 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ZERO_652 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELG_653 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_SRINV_654 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CLKINV_655 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DXMUX_656 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORF_657 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYINIT_658 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DYMUX_659 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORG_660 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELF_661 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXFAST_662 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYAND_663 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_FASTCARRY_664 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXG2_665 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXF2_666 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_LOGIC_ZERO_667 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELG_668 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_SRINV_669 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CLKINV_670 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DXMUX_671 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORF_672 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYINIT_673 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DYMUX_674 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORG_675 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELF_676 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXFAST_677 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYAND_678 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_FASTCARRY_679 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXG2_680 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXF2_681 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_LOGIC_ZERO_682 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELG_683 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_SRINV_684 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CLKINV_685 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DXMUX_686 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORF_687 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYINIT_688 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DYMUX_689 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORG_690 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELF_691 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXFAST_692 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYAND_693 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_FASTCARRY_694 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXG2_695 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXF2_696 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_LOGIC_ZERO_697 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELG_698 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_SRINV_699 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CLKINV_700 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_DXMUX_701 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_XORF_702 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_LOGIC_ZERO_703 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CYINIT_704 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CYSELF_705 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_DYMUX_706 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_XORG_707 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_9_rt_708 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_SRINV_709 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CLKINV_710 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DXMUX_711 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ONE_712 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYINIT_713 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELF_714 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DYMUX_715 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_XORG_716 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYMUXG_717 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ZERO_718 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELG_719 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_SRINV_720 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CLKINV_721 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DXMUX_722 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORF_723 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYINIT_724 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DYMUX_725 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORG_726 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELF_727 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXFAST_728 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYAND_729 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_FASTCARRY_730 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXG2_731 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXF2_732 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_LOGIC_ZERO_733 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELG_734 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_SRINV_735 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CLKINV_736 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DXMUX_737 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORF_738 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYINIT_739 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DYMUX_740 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORG_741 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELF_742 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXFAST_743 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYAND_744 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_FASTCARRY_745 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXG2_746 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXF2_747 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_LOGIC_ZERO_748 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELG_749 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_SRINV_750 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CLKINV_751 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DXMUX_752 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORF_753 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYINIT_754 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DYMUX_755 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORG_756 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELF_757 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXFAST_758 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYAND_759 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_FASTCARRY_760 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXG2_761 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXF2_762 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_LOGIC_ZERO_763 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELG_764 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_SRINV_765 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CLKINV_766 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_DXMUX_767 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_XORF_768 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_LOGIC_ZERO_769 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CYINIT_770 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CYSELF_771 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_DYMUX_772 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_XORG_773 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_9_rt_774 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_SRINV_775 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CLKINV_776 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DXMUX_777 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ONE_778 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYINIT_779 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELF_780 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DYMUX_781 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_XORG_782 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYMUXG_783 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ZERO_784 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELG_785 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_SRINV_786 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CLKINV_787 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DXMUX_788 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORF_789 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYINIT_790 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DYMUX_791 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORG_792 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELF_793 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXFAST_794 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYAND_795 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_FASTCARRY_796 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXG2_797 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXF2_798 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_LOGIC_ZERO_799 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELG_800 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_SRINV_801 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CLKINV_802 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DXMUX_803 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORF_804 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYINIT_805 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DYMUX_806 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORG_807 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELF_808 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXFAST_809 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYAND_810 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_FASTCARRY_811 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXG2_812 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXF2_813 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_LOGIC_ZERO_814 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELG_815 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_SRINV_816 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CLKINV_817 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DXMUX_818 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORF_819 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYINIT_820 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DYMUX_821 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORG_822 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELF_823 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXFAST_824 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYAND_825 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_FASTCARRY_826 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXG2_827 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXF2_828 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_LOGIC_ZERO_829 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELG_830 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_SRINV_831 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CLKINV_832 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_DXMUX_833 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_XORF_834 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_LOGIC_ZERO_835 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CYINIT_836 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CYSELF_837 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_DYMUX_838 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_XORG_839 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_9_rt_840 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_SRINV_841 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CLKINV_842 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DXMUX_843 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ONE_844 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYINIT_845 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELF_846 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DYMUX_847 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_XORG_848 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYMUXG_849 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ZERO_850 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELG_851 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_SRINV_852 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CLKINV_853 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DXMUX_854 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORF_855 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYINIT_856 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DYMUX_857 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORG_858 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF_859 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXFAST_860 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYAND_861 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_FASTCARRY_862 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXG2_863 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXF2_864 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_865 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELG_866 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_SRINV_867 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CLKINV_868 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DXMUX_869 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORF_870 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYINIT_871 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DYMUX_872 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORG_873 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF_874 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXFAST_875 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYAND_876 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_FASTCARRY_877 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXG2_878 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXF2_879 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_880 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELG_881 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_SRINV_882 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CLKINV_883 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DXMUX_884 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORF_885 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYINIT_886 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DYMUX_887 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORG_888 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF_889 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXFAST_890 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYAND_891 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_FASTCARRY_892 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXG2_893 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXF2_894 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_895 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELG_896 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_SRINV_897 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CLKINV_898 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DXMUX_899 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORF_900 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_LOGIC_ZERO_901 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYINIT_902 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYSELF_903 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DYMUX_904 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORG_905 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9_rt_906 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_SRINV_907 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CLKINV_908 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DXMUX_909 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ONE_910 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYINIT_911 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELF_912 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DYMUX_913 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_XORG_914 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYMUXG_915 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ZERO_916 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELG_917 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_SRINV_918 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CLKINV_919 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CEINV_920 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DXMUX_921 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORF_922 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYINIT_923 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DYMUX_924 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORG_925 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELF_926 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXFAST_927 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYAND_928 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_FASTCARRY_929 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXG2_930 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXF2_931 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_LOGIC_ZERO_932 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELG_933 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_SRINV_934 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CLKINV_935 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CEINV_936 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DXMUX_937 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORF_938 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYINIT_939 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DYMUX_940 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORG_941 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELF_942 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXFAST_943 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYAND_944 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_FASTCARRY_945 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXG2_946 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXF2_947 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_LOGIC_ZERO_948 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELG_949 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_SRINV_950 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CLKINV_951 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CEINV_952 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DXMUX_953 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORF_954 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYINIT_955 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DYMUX_956 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORG_957 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELF_958 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXFAST_959 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYAND_960 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_FASTCARRY_961 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXG2_962 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXF2_963 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_LOGIC_ZERO_964 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELG_965 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_SRINV_966 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CLKINV_967 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CEINV_968 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_DXMUX_969 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_XORF_970 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CYINIT_971 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_rt_972 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CLKINV_973 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CEINV_974 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DXMUX_975 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ONE_976 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYINIT_977 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELF_978 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DYMUX_979 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_XORG_980 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYMUXG_981 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ZERO_982 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELG_983 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_SRINV_984 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CLKINV_985 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CEINV_986 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DXMUX_987 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORF_988 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYINIT_989 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DYMUX_990 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORG_991 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELF_992 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXFAST_993 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYAND_994 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_FASTCARRY_995 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXG2_996 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXF2_997 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_LOGIC_ZERO_998 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELG_999 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_SRINV_1000 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CLKINV_1001 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CEINV_1002 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DXMUX_1003 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORF_1004 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYINIT_1005 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DYMUX_1006 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORG_1007 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELF_1008 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXFAST_1009 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYAND_1010 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_FASTCARRY_1011 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXG2_1012 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXF2_1013 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_LOGIC_ZERO_1014 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELG_1015 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_SRINV_1016 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CLKINV_1017 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CEINV_1018 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DXMUX_1019 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORF_1020 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYINIT_1021 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DYMUX_1022 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORG_1023 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELF_1024 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXFAST_1025 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYAND_1026 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_FASTCARRY_1027 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXG2_1028 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXF2_1029 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_LOGIC_ZERO_1030 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELG_1031 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_SRINV_1032 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CLKINV_1033 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CEINV_1034 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_DXMUX_1035 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_XORF_1036 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CYINIT_1037 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_rt_1038 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CLKINV_1039 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CEINV_1040 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DXMUX_1041 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ONE_1042 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYINIT_1043 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELF_1044 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DYMUX_1045 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_XORG_1046 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYMUXG_1047 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ZERO_1048 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELG_1049 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_SRINV_1050 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CLKINV_1051 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CEINV_1052 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DXMUX_1053 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORF_1054 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYINIT_1055 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DYMUX_1056 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORG_1057 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF_1058 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXFAST_1059 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYAND_1060 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_FASTCARRY_1061 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXG2_1062 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXF2_1063 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_1064 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELG_1065 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_SRINV_1066 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CLKINV_1067 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CEINV_1068 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DXMUX_1069 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORF_1070 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYINIT_1071 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DYMUX_1072 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORG_1073 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF_1074 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXFAST_1075 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYAND_1076 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_FASTCARRY_1077 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXG2_1078 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXF2_1079 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_1080 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELG_1081 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_SRINV_1082 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CLKINV_1083 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CEINV_1084 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DXMUX_1085 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORF_1086 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYINIT_1087 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_F : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DYMUX_1088 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORG_1089 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF_1090 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXFAST_1091 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYAND_1092 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_FASTCARRY_1093 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXG2_1094 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXF2_1095 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_1096 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELG_1097 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_G : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_SRINV_1098 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CLKINV_1099 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CEINV_1100 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DXMUX_1101 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORF_1102 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYINIT_1103 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_rt_1104 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CLKINV_1105 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CEINV_1106 : STD_LOGIC; signal i_WRU_INBUF : STD_LOGIC; signal i_RDYU_INBUF : STD_LOGIC; signal b_dbus_10_O : STD_LOGIC; signal b_dbus_10_T : STD_LOGIC; signal b_dbus_10_INBUF : STD_LOGIC; signal b_dbus_11_O : STD_LOGIC; signal b_dbus_11_T : STD_LOGIC; signal b_dbus_11_INBUF : STD_LOGIC; signal b_dbus_12_O : STD_LOGIC; signal b_dbus_12_T : STD_LOGIC; signal b_dbus_12_INBUF : STD_LOGIC; signal b_dbus_13_O : STD_LOGIC; signal b_dbus_13_T : STD_LOGIC; signal b_dbus_13_INBUF : STD_LOGIC; signal b_dbus_14_O : STD_LOGIC; signal b_dbus_14_T : STD_LOGIC; signal b_dbus_14_INBUF : STD_LOGIC; signal b_dbus_15_O : STD_LOGIC; signal b_dbus_15_T : STD_LOGIC; signal b_dbus_15_INBUF : STD_LOGIC; signal o_WRX_O : STD_LOGIC; signal o_RDYX_O : STD_LOGIC; signal o_LEDrx_O : STD_LOGIC; signal o_LEDtx_O : STD_LOGIC; signal b_dbus_0_O : STD_LOGIC; signal b_dbus_0_T : STD_LOGIC; signal b_dbus_0_INBUF : STD_LOGIC; signal b_dbus_1_O : STD_LOGIC; signal b_dbus_1_T : STD_LOGIC; signal b_dbus_1_INBUF : STD_LOGIC; signal b_dbus_2_O : STD_LOGIC; signal b_dbus_2_T : STD_LOGIC; signal b_dbus_2_INBUF : STD_LOGIC; signal b_dbus_3_O : STD_LOGIC; signal b_dbus_3_T : STD_LOGIC; signal b_dbus_3_INBUF : STD_LOGIC; signal b_dbus_4_O : STD_LOGIC; signal b_dbus_4_T : STD_LOGIC; signal b_dbus_4_INBUF : STD_LOGIC; signal i_SYSCLK_INBUF : STD_LOGIC; signal b_dbus_5_O : STD_LOGIC; signal b_dbus_5_T : STD_LOGIC; signal b_dbus_5_INBUF : STD_LOGIC; signal b_dbus_6_O : STD_LOGIC; signal b_dbus_6_T : STD_LOGIC; signal b_dbus_6_INBUF : STD_LOGIC; signal b_dbus_7_O : STD_LOGIC; signal b_dbus_7_T : STD_LOGIC; signal b_dbus_7_INBUF : STD_LOGIC; signal b_dbus_8_O : STD_LOGIC; signal b_dbus_8_T : STD_LOGIC; signal b_dbus_8_INBUF : STD_LOGIC; signal b_dbus_9_O : STD_LOGIC; signal b_dbus_9_T : STD_LOGIC; signal b_dbus_9_INBUF : STD_LOGIC; signal i_nReset_INBUF : STD_LOGIC; signal i_IFCLK_INBUF : STD_LOGIC; signal o_LEDrun_O : STD_LOGIC; signal i_SYSCLK_BUFGP_BUFG_S_INVNOT : STD_LOGIC; signal i_SYSCLK_BUFGP_BUFG_I0_INV : STD_LOGIC; signal i_IFCLK_BUFGP_BUFG_S_INVNOT : STD_LOGIC; signal i_IFCLK_BUFGP_BUFG_I0_INV : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOPB3 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOPB2 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOPB1 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOPB0 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOPA1 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOPA0 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA15 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA14 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA13 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA12 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA11 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA10 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA9 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA8 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA7 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA6 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA5 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA4 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA3 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA2 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA1 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA0 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIPB3 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIPB2 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIPB1 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIPB0 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB31 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB30 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB29 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB28 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB27 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB26 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB25 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB24 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB23 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB22 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB21 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB20 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB19 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB18 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB17 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB16 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB15 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB14 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB13 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB12 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB11 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB10 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB9 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB8 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB7 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB6 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB5 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB4 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB3 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB2 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB1 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB0 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_WEA_INTNOT : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOPB3 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOPB2 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOPB1 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOPB0 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB31 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB30 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB29 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB28 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB27 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB26 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB25 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB24 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB23 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB22 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB21 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB20 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB19 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB18 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB17 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB16 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB15 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB14 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB13 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB12 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB11 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB10 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB9 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB8 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB7 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB6 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB5 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB4 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB3 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB2 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB1 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB0 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOPA1 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOPA0 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIPA1 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIPA0 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA15 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA14 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA13 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA12 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA11 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA10 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA9 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA8 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA7 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA6 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA5 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA4 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA3 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA2 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA1 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA0 : STD_LOGIC; signal s_X2U_RD_EN_F5MUX_1107 : STD_LOGIC; signal N360 : STD_LOGIC; signal s_X2U_RD_EN_BXINV_1108 : STD_LOGIC; signal N361 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd4_In_map18_F5MUX_1109 : STD_LOGIC; signal N362 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd4_In_map18_BXINV_1110 : STD_LOGIC; signal N363 : STD_LOGIC; signal Loopback_pr_stateLoop_FFd2_DXMUX_1111 : STD_LOGIC; signal Loopback_pr_stateLoop_FFd2_F5MUX_1112 : STD_LOGIC; signal N357 : STD_LOGIC; signal Loopback_pr_stateLoop_FFd2_BXINV_1113 : STD_LOGIC; signal N358 : STD_LOGIC; signal Loopback_pr_stateLoop_FFd2_CLKINV_1114 : STD_LOGIC; signal o_RDYX_OBUF_F5MUX_1115 : STD_LOGIC; signal N355 : STD_LOGIC; signal o_RDYX_OBUF_BXINV_1116 : STD_LOGIC; signal N354 : STD_LOGIC; signal FSM_GPIF_v_setup_not0001_1117 : STD_LOGIC; signal N4_pack_1 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd3_DXMUX_1118 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd3_In : STD_LOGIC; signal FSM_GPIF_pr_state_FFd3_In98_SW0_O_pack_1 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd3_CLKINV_1119 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd3_CEINV_1120 : STD_LOGIC; signal FSM_GPIF_v_setup_3_DXMUX_1121 : STD_LOGIC; signal FSM_GPIF_Mcount_v_setup_eqn_3 : STD_LOGIC; signal FSM_GPIF_Mcount_v_setup_eqn_332_O_pack_1 : STD_LOGIC; signal FSM_GPIF_v_setup_3_CLKINV_1122 : STD_LOGIC; signal FSM_GPIF_v_setup_3_CEINV_1123 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd4_DXMUX_1124 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd4_In : STD_LOGIC; signal FSM_GPIF_pr_state_FFd4_In13_O_pack_1 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd4_CLKINV_1125 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd4_CEINV_1126 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_DXMUX_1127 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0007 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1_O_pack_1 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_CLKINV_1128 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_0_DXMUX_1129 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0007 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1_O_pack_1 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_0_CLKINV_1130 : STD_LOGIC; signal FSM_GPIF_v_setup_0_DXMUX_1131 : STD_LOGIC; signal FSM_GPIF_Mcount_v_setup_eqn_0_1132 : STD_LOGIC; signal FSM_GPIF_Mcount_v_setup_eqn_3_map0_pack_1 : STD_LOGIC; signal FSM_GPIF_v_setup_0_CLKINV_1133 : STD_LOGIC; signal FSM_GPIF_v_setup_0_CEINV_1134 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_0_DXMUX_1135 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0007 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1_O_pack_1 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_0_CLKINV_1136 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_DXMUX_1137 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0007 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1_O_pack_1 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_CLKINV_1138 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd2_DXMUX_1139 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd2_In : STD_LOGIC; signal FSM_GPIF_pr_state_FFd2_In5_O_pack_1 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd2_CLKINV_1140 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd2_CEINV_1141 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_DYMUX_1142 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0006 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_CLKINV_1143 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_2_DYMUX_1144 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0006 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_2_CLKINV_1145 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_DXMUX_1146 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0004 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_DYMUX_1147 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0005 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_SRINV_1148 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_CLKINV_1149 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DXMUX_1150 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0004 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DYMUX_1151 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0005 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_SRINV_1152 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_CLKINV_1153 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DXMUX_1154 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0003 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DYMUX_1155 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_GYMUX_1156 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002_pack_1 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_SRINV_1157 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_CLKINV_1158 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_DXMUX_1159 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0003 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_DYMUX_1160 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_GYMUX_1161 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002_pack_1 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_SRINV_1162 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_CLKINV_1163 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_DXMUX_1164 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0000 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_DYMUX_1165 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0001 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_SRINV_1166 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_CLKINV_1167 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_DXMUX_1168 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0000 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_DYMUX_1169 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0001 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_SRINV_1170 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_CLKINV_1171 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_DXMUX_1172 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0006 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_DYMUX_1173 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0007 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_SRINV_1174 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_CLKINV_1175 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_DXMUX_1176 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0006 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_DYMUX_1177 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0007 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_SRINV_1178 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_CLKINV_1179 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_DXMUX_1180 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0004 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_DYMUX_1181 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0005 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_SRINV_1182 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_CLKINV_1183 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_DXMUX_1184 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0004 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_DYMUX_1185 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0005 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_SRINV_1186 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_CLKINV_1187 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_DXMUX_1188 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0002 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_DYMUX_1189 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0003 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_SRINV_1190 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_CLKINV_1191 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_DXMUX_1192 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0002 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_DYMUX_1193 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0003 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_SRINV_1194 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_CLKINV_1195 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_DXMUX_1196 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0000 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_DYMUX_1197 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0001 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_SRINV_1198 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_CLKINV_1199 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_DXMUX_1200 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0000 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_DYMUX_1201 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0001 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_SRINV_1202 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_CLKINV_1203 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN : STD_LOGIC; signal s_X2U_AM_FULL_DYMUX_1204 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_almost_full_i_or0000 : STD_LOGIC; signal s_X2U_AM_FULL_CLKINV_1205 : STD_LOGIC; signal s_X2U_AM_FULL_CEINVNOT : STD_LOGIC; signal s_U2X_AM_FULL_DYMUX_1206 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_almost_full_i_or0000 : STD_LOGIC; signal s_U2X_AM_FULL_CLKINV_1207 : STD_LOGIC; signal s_U2X_AM_FULL_CEINVNOT : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_DYMUX_1208 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0006 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_CLKINV_1209 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_DXMUX_1210 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0004 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_DYMUX_1211 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0005 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_SRINV_1212 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_CLKINV_1213 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_2_DYMUX_1214 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0006 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_2_CLKINV_1215 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DXMUX_1216 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0004 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DYMUX_1217 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0005 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_SRINV_1218 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_CLKINV_1219 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DXMUX_1220 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0003 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DYMUX_1221 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_GYMUX_1222 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002_pack_1 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_SRINV_1223 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_CLKINV_1224 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_DXMUX_1225 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0000 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_DYMUX_1226 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0001 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_SRINV_1227 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_CLKINV_1228 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_DXMUX_1229 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0003 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_DYMUX_1230 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_GYMUX_1231 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002_pack_1 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_SRINV_1232 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_CLKINV_1233 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_DXMUX_1234 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0000 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_DYMUX_1235 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0001 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_SRINV_1236 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_CLKINV_1237 : STD_LOGIC; signal N120 : STD_LOGIC; signal FSM_GPIF_v_setup_1_DYMUX_1238 : STD_LOGIC; signal FSM_GPIF_Mcount_v_setup_eqn_1_1239 : STD_LOGIC; signal FSM_GPIF_v_setup_1_CLKINV_1240 : STD_LOGIC; signal FSM_GPIF_v_setup_1_CEINV_1241 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en : STD_LOGIC; signal s_U2X_AM_EMPTY_DYMUX_1242 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_almost_empty_i_or0000 : STD_LOGIC; signal s_U2X_AM_EMPTY_CLKINV_1243 : STD_LOGIC; signal s_U2X_AM_EMPTY_CEINVNOT : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_DXMUX_1244 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0006 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_DYMUX_1245 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0007 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_SRINV_1246 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_CLKINV_1247 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_DXMUX_1248 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0006 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_DYMUX_1249 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0007 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_SRINV_1250 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_CLKINV_1251 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_DXMUX_1252 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0004 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_DYMUX_1253 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0005 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_SRINV_1254 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_CLKINV_1255 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_DXMUX_1256 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0004 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_DYMUX_1257 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0005 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_SRINV_1258 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_CLKINV_1259 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_DXMUX_1260 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0002 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_DYMUX_1261 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0003 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_SRINV_1262 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_CLKINV_1263 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_DXMUX_1264 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0002 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_DYMUX_1265 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0003 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_SRINV_1266 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_CLKINV_1267 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_DXMUX_1268 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0000 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_DYMUX_1269 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0001 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_SRINV_1270 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_CLKINV_1271 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_DXMUX_1272 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0000 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_DYMUX_1273 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0001 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_SRINV_1274 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_CLKINV_1275 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN : STD_LOGIC; signal s_X2U_EMPTY_DYMUX_1276 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_EMPTY_NONREG : STD_LOGIC; signal s_X2U_EMPTY_CLKINV_1277 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN : STD_LOGIC; signal Loopback_pr_stateLoop_FFd3_DYMUX_1278 : STD_LOGIC; signal N333 : STD_LOGIC; signal Loopback_pr_stateLoop_FFd3_CLKINV_1279 : STD_LOGIC; signal Loopback_pr_stateLoop_FFd3_CEINV_1280 : STD_LOGIC; signal F_IN_full_DYMUX_1281 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG : STD_LOGIC; signal F_IN_full_CLKINV_1282 : STD_LOGIC; signal o_LEDrx_OBUF_1283 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd3_In_map22 : STD_LOGIC; signal FSM_GPIF_o_RDYX_map9 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd3_In_map18 : STD_LOGIC; signal Loopback_o_X2U_DATA_1_DXMUX_1284 : STD_LOGIC; signal Loopback_o_X2U_DATA_1_DYMUX_1285 : STD_LOGIC; signal Loopback_o_X2U_DATA_1_CLKINV_1286 : STD_LOGIC; signal Loopback_o_X2U_DATA_3_DXMUX_1287 : STD_LOGIC; signal Loopback_o_X2U_DATA_3_DYMUX_1288 : STD_LOGIC; signal Loopback_o_X2U_DATA_3_CLKINV_1289 : STD_LOGIC; signal Loopback_o_X2U_DATA_5_DXMUX_1290 : STD_LOGIC; signal Loopback_o_X2U_DATA_5_DYMUX_1291 : STD_LOGIC; signal Loopback_o_X2U_DATA_5_CLKINV_1292 : STD_LOGIC; signal Loopback_o_X2U_DATA_7_DXMUX_1293 : STD_LOGIC; signal Loopback_o_X2U_DATA_7_DYMUX_1294 : STD_LOGIC; signal Loopback_o_X2U_DATA_7_CLKINV_1295 : STD_LOGIC; signal Loopback_o_X2U_DATA_9_DXMUX_1296 : STD_LOGIC; signal Loopback_o_X2U_DATA_9_DYMUX_1297 : STD_LOGIC; signal Loopback_o_X2U_DATA_9_CLKINV_1298 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd4_In_map30 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd4_In_map29_pack_1 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_DYMUX_1299 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_CLKINV_1300 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_DYMUX_1301 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_CLKINV_1302 : STD_LOGIC; signal N124 : STD_LOGIC; signal FSM_GPIF_Mcount_v_setup_eqn_3_map16 : STD_LOGIC; signal N350 : STD_LOGIC; signal s_FIFOrst : STD_LOGIC; signal FSM_GPIF_pr_state_FFd2_In_map8 : STD_LOGIC; signal o_LEDtx_OBUF_1303 : STD_LOGIC; signal FSM_GPIF_o_RDYX_map19 : STD_LOGIC; signal o_LEDrun_OBUF_1304 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd1_DXMUX_1305 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd1_In_1306 : STD_LOGIC; signal N89_pack_1 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd1_CLKINV_1307 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd1_CEINV_1308 : STD_LOGIC; signal FSM_GPIF_s_bus_trans_dir_inv : STD_LOGIC; signal N90 : STD_LOGIC; signal Loopback_o_X2U_DATA_11_DXMUX_1309 : STD_LOGIC; signal Loopback_o_X2U_DATA_11_DYMUX_1310 : STD_LOGIC; signal Loopback_o_X2U_DATA_11_CLKINV_1311 : STD_LOGIC; signal Loopback_o_X2U_DATA_13_DXMUX_1312 : STD_LOGIC; signal Loopback_o_X2U_DATA_13_DYMUX_1313 : STD_LOGIC; signal Loopback_o_X2U_DATA_13_CLKINV_1314 : STD_LOGIC; signal Loopback_o_X2U_DATA_21_DXMUX_1315 : STD_LOGIC; signal Loopback_o_X2U_DATA_21_DYMUX_1316 : STD_LOGIC; signal Loopback_o_X2U_DATA_21_CLKINV_1317 : STD_LOGIC; signal Loopback_o_X2U_DATA_15_DXMUX_1318 : STD_LOGIC; signal Loopback_o_X2U_DATA_15_DYMUX_1319 : STD_LOGIC; signal Loopback_o_X2U_DATA_15_CLKINV_1320 : STD_LOGIC; signal Loopback_o_X2U_DATA_23_DXMUX_1321 : STD_LOGIC; signal Loopback_o_X2U_DATA_23_DYMUX_1322 : STD_LOGIC; signal Loopback_o_X2U_DATA_23_CLKINV_1323 : STD_LOGIC; signal Loopback_o_X2U_DATA_31_DXMUX_1324 : STD_LOGIC; signal Loopback_o_X2U_DATA_31_DYMUX_1325 : STD_LOGIC; signal Loopback_o_X2U_DATA_31_CLKINV_1326 : STD_LOGIC; signal Loopback_o_X2U_DATA_17_DXMUX_1327 : STD_LOGIC; signal Loopback_o_X2U_DATA_17_DYMUX_1328 : STD_LOGIC; signal Loopback_o_X2U_DATA_17_CLKINV_1329 : STD_LOGIC; signal Loopback_o_X2U_DATA_25_DXMUX_1330 : STD_LOGIC; signal Loopback_o_X2U_DATA_25_DYMUX_1331 : STD_LOGIC; signal Loopback_o_X2U_DATA_25_CLKINV_1332 : STD_LOGIC; signal Loopback_o_X2U_DATA_19_DXMUX_1333 : STD_LOGIC; signal Loopback_o_X2U_DATA_19_DYMUX_1334 : STD_LOGIC; signal Loopback_o_X2U_DATA_19_CLKINV_1335 : STD_LOGIC; signal Loopback_o_X2U_DATA_27_DXMUX_1336 : STD_LOGIC; signal Loopback_o_X2U_DATA_27_DYMUX_1337 : STD_LOGIC; signal Loopback_o_X2U_DATA_27_CLKINV_1338 : STD_LOGIC; signal Loopback_o_X2U_DATA_29_DXMUX_1339 : STD_LOGIC; signal Loopback_o_X2U_DATA_29_DYMUX_1340 : STD_LOGIC; signal Loopback_o_X2U_DATA_29_CLKINV_1341 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_DYMUX_1342 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_CLKINV_1343 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_9_DYMUX_1344 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_9_CLKINV_1345 : STD_LOGIC; signal F_OUT_full_DXMUX_1346 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG : STD_LOGIC; signal s_X2U_WR_EN_pack_1 : STD_LOGIC; signal F_OUT_full_CLKINV_1347 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_DYMUX_1348 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CLKINV_1349 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CEINV_1350 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_DYMUX_1351 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CLKINV_1352 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CEINV_1353 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_DXMUX_1354 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_DYMUX_1355 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_SRINV_1356 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_CLKINV_1357 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_DXMUX_1358 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_DYMUX_1359 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_SRINV_1360 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_CLKINV_1361 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_DXMUX_1362 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_DYMUX_1363 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_SRINV_1364 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_CLKINV_1365 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_DXMUX_1366 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_DYMUX_1367 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_SRINV_1368 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_CLKINV_1369 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_DXMUX_1370 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_DYMUX_1371 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_SRINV_1372 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_CLKINV_1373 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_DXMUX_1374 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_DYMUX_1375 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_SRINV_1376 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_CLKINV_1377 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_DXMUX_1378 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_DYMUX_1379 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_SRINV_1380 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_CLKINV_1381 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_DXMUX_1382 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_DYMUX_1383 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_SRINV_1384 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_CLKINV_1385 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_DYMUX_1386 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_CLKINV_1387 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_9_DYMUX_1388 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_9_CLKINV_1389 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_DYMUX_1390 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CLKINV_1391 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CEINV_1392 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_DYMUX_1393 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CLKINV_1394 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CEINV_1395 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_N86 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_N86 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_DYMUX_1396 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_CLKINV_1397 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_9_DYMUX_1398 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_9_CLKINV_1399 : STD_LOGIC; signal N30 : STD_LOGIC; signal FSM_GPIF_o_RDYX_map2 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_DXMUX_1400 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_DYMUX_1401 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_SRINV_1402 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_CLKINV_1403 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_DXMUX_1404 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_DYMUX_1405 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_SRINV_1406 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_CLKINV_1407 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_DYMUX_1408 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_CLKINV_1409 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_DXMUX_1410 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_DYMUX_1411 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_SRINV_1412 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_CLKINV_1413 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_DYMUX_1414 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_CLKINV_1415 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_DXMUX_1416 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_DYMUX_1417 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_SRINV_1418 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_CLKINV_1419 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_DXMUX_1420 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_DYMUX_1421 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_SRINV_1422 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_CLKINV_1423 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_DXMUX_1424 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_DYMUX_1425 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_SRINV_1426 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_CLKINV_1427 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_DXMUX_1428 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_DYMUX_1429 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_SRINV_1430 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_CLKINV_1431 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_DXMUX_1432 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_DYMUX_1433 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_SRINV_1434 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_CLKINV_1435 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_DYMUX_1436 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_CLKINV_1437 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9_DYMUX_1438 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9_CLKINV_1439 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_DYMUX_1440 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_CLKINV_1441 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_DYMUX_1442 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_CLKINV_1443 : STD_LOGIC; signal FSM_GPIF_pr_state_not0001 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_DXMUX_1444 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_DYMUX_1445 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_SRINV_1446 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_CLKINV_1447 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_DXMUX_1448 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_DYMUX_1449 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_SRINV_1450 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_CLKINV_1451 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_DXMUX_1452 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_DYMUX_1453 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_SRINV_1454 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_CLKINV_1455 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_DXMUX_1456 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_DYMUX_1457 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_SRINV_1458 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_CLKINV_1459 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_DXMUX_1460 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_DYMUX_1461 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_SRINV_1462 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_CLKINV_1463 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_DXMUX_1464 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_DYMUX_1465 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_SRINV_1466 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_CLKINV_1467 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_DXMUX_1468 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_DYMUX_1469 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_SRINV_1470 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_CLKINV_1471 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_DXMUX_1472 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_DYMUX_1473 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_SRINV_1474 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_CLKINV_1475 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_DYMUX_1476 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_CLKINV_1477 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_9_DYMUX_1478 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_9_CLKINV_1479 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_DYMUX_1480 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_CLKINV_1481 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_9_DYMUX_1482 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_9_CLKINV_1483 : STD_LOGIC; signal s_U2X_EMPTY_DXMUX_1484 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_EMPTY_NONREG : STD_LOGIC; signal s_U2X_RD_EN_pack_1 : STD_LOGIC; signal s_U2X_EMPTY_CLKINV_1485 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_DYMUX_1486 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_CLKINV_1487 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_9_DYMUX_1488 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_9_CLKINV_1489 : STD_LOGIC; signal o_WRX_OBUF_1490 : STD_LOGIC; signal N31_pack_1 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_DXMUX_1491 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_DYMUX_1492 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_SRINV_1493 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_CLKINV_1494 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_DXMUX_1495 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_DYMUX_1496 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_SRINV_1497 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_CLKINV_1498 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_DXMUX_1499 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_DYMUX_1500 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_SRINV_1501 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_CLKINV_1502 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_DXMUX_1503 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_DYMUX_1504 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_SRINV_1505 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_CLKINV_1506 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_DXMUX_1507 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_DYMUX_1508 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_SRINV_1509 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_CLKINV_1510 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_N90 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_DXMUX_1511 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_DYMUX_1512 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_SRINV_1513 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_CLKINV_1514 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_N90 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_DXMUX_1515 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_DYMUX_1516 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_SRINV_1517 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_CLKINV_1518 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_DXMUX_1519 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_DYMUX_1520 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_SRINV_1521 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_CLKINV_1522 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_DYMUX_1523 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_CLKINV_1524 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9_DYMUX_1525 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9_CLKINV_1526 : STD_LOGIC; signal FSM_GPIF_v_setup_2_DXMUX_1527 : STD_LOGIC; signal FSM_GPIF_Mcount_v_setup_eqn_2_1528 : STD_LOGIC; signal N23_pack_1 : STD_LOGIC; signal FSM_GPIF_v_setup_2_CLKINV_1529 : STD_LOGIC; signal FSM_GPIF_v_setup_2_CEINV_1530 : STD_LOGIC; signal b_dbus_10_IFF_ICLK1INV_1531 : STD_LOGIC; signal b_dbus_10_IFF_ICEINV_1532 : STD_LOGIC; signal b_dbus_10_IFF_IFFDMUX_1533 : STD_LOGIC; signal b_dbus_11_IFF_ICLK1INV_1534 : STD_LOGIC; signal b_dbus_11_IFF_ICEINV_1535 : STD_LOGIC; signal b_dbus_11_IFF_IFFDMUX_1536 : STD_LOGIC; signal b_dbus_12_IFF_ICLK1INV_1537 : STD_LOGIC; signal b_dbus_12_IFF_ICEINV_1538 : STD_LOGIC; signal b_dbus_12_IFF_IFFDMUX_1539 : STD_LOGIC; signal b_dbus_13_IFF_ICLK1INV_1540 : STD_LOGIC; signal b_dbus_13_IFF_ICEINV_1541 : STD_LOGIC; signal b_dbus_13_IFF_IFFDMUX_1542 : STD_LOGIC; signal b_dbus_14_IFF_ICLK1INV_1543 : STD_LOGIC; signal b_dbus_14_IFF_ICEINV_1544 : STD_LOGIC; signal b_dbus_14_IFF_IFFDMUX_1545 : STD_LOGIC; signal b_dbus_15_IFF_ICLK1INV_1546 : STD_LOGIC; signal b_dbus_15_IFF_ICEINV_1547 : STD_LOGIC; signal b_dbus_15_IFF_IFFDMUX_1548 : STD_LOGIC; signal b_dbus_0_IFF_ICLK1INV_1549 : STD_LOGIC; signal b_dbus_0_IFF_ICEINV_1550 : STD_LOGIC; signal b_dbus_0_IFF_IFFDMUX_1551 : STD_LOGIC; signal b_dbus_1_IFF_ICLK1INV_1552 : STD_LOGIC; signal b_dbus_1_IFF_ICEINV_1553 : STD_LOGIC; signal b_dbus_1_IFF_IFFDMUX_1554 : STD_LOGIC; signal b_dbus_2_IFF_ICLK1INV_1555 : STD_LOGIC; signal b_dbus_2_IFF_ICEINV_1556 : STD_LOGIC; signal b_dbus_2_IFF_IFFDMUX_1557 : STD_LOGIC; signal b_dbus_3_IFF_ICLK1INV_1558 : STD_LOGIC; signal b_dbus_3_IFF_ICEINV_1559 : STD_LOGIC; signal b_dbus_3_IFF_IFFDMUX_1560 : STD_LOGIC; signal b_dbus_4_IFF_ICLK1INV_1561 : STD_LOGIC; signal b_dbus_4_IFF_ICEINV_1562 : STD_LOGIC; signal b_dbus_4_IFF_IFFDMUX_1563 : STD_LOGIC; signal b_dbus_5_IFF_ICLK1INV_1564 : STD_LOGIC; signal b_dbus_5_IFF_ICEINV_1565 : STD_LOGIC; signal b_dbus_5_IFF_IFFDMUX_1566 : STD_LOGIC; signal b_dbus_6_IFF_ICLK1INV_1567 : STD_LOGIC; signal b_dbus_6_IFF_ICEINV_1568 : STD_LOGIC; signal b_dbus_6_IFF_IFFDMUX_1569 : STD_LOGIC; signal b_dbus_7_IFF_ICLK1INV_1570 : STD_LOGIC; signal b_dbus_7_IFF_ICEINV_1571 : STD_LOGIC; signal b_dbus_7_IFF_IFFDMUX_1572 : STD_LOGIC; signal b_dbus_8_IFF_ICLK1INV_1573 : STD_LOGIC; signal b_dbus_8_IFF_ICEINV_1574 : STD_LOGIC; signal b_dbus_8_IFF_IFFDMUX_1575 : STD_LOGIC; signal b_dbus_9_IFF_ICLK1INV_1576 : STD_LOGIC; signal b_dbus_9_IFF_ICEINV_1577 : STD_LOGIC; signal b_dbus_9_IFF_IFFDMUX_1578 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_FFX_RSTAND_1579 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_FFX_RSTAND_1580 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_FFX_RSTAND_1581 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_FFX_RSTAND_1582 : STD_LOGIC; signal s_X2U_EMPTY_FFY_SET : STD_LOGIC; signal Loopback_pr_stateLoop_FFd3_FFY_RSTAND_1583 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_FFX_RSTAND_1584 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_FFX_RSTAND_1585 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_FFX_RSTAND_1586 : STD_LOGIC; signal Loopback_pr_stateLoop_FFd2_FFX_RSTAND_1587 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd3_FFX_RSTAND_1588 : STD_LOGIC; signal FSM_GPIF_v_setup_3_FFX_RSTAND_1589 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_FFY_SET : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_FFY_SET : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_FFX_RSTAND_1590 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd2_FFX_RSTAND_1591 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_FFY_RSTAND_1592 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_2_FFY_RSTAND_1593 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd4_FFX_RSTAND_1594 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_FFX_RSTAND_1595 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_0_FFX_RSTAND_1596 : STD_LOGIC; signal FSM_GPIF_v_setup_0_FFX_RSTAND_1597 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_0_FFX_RSTAND_1598 : STD_LOGIC; signal s_X2U_AM_FULL_FFY_SET : STD_LOGIC; signal s_U2X_AM_FULL_FFY_SET : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_FFY_RSTAND_1599 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_2_FFY_RSTAND_1600 : STD_LOGIC; signal FSM_GPIF_v_setup_1_FFY_RSTAND_1601 : STD_LOGIC; signal s_U2X_AM_EMPTY_FFY_SET : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_FFY_RSTAND_1602 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_9_FFY_RSTAND_1603 : STD_LOGIC; signal FSM_GPIF_pr_state_FFd1_FFX_RSTAND_1604 : STD_LOGIC; signal F_IN_full_FFY_SET : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_FFY_SET : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_FFY_SET : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_FFY_RSTAND_1605 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_9_FFY_RSTAND_1606 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_FFY_RSTAND_1607 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_9_FFY_RSTAND_1608 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_FFY_SET : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_FFY_SET : STD_LOGIC; signal F_OUT_full_FFX_SET : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_FFY_SET : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_FFY_SET : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_FFY_RSTAND_1609 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9_FFY_RSTAND_1610 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_FFY_SET : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_FFY_SET : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_FFY_RSTAND_1611 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_9_FFY_RSTAND_1612 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_FFY_RSTAND_1613 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_9_FFY_RSTAND_1614 : STD_LOGIC; signal s_U2X_EMPTY_FFX_SET : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_FFY_RSTAND_1615 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_9_FFY_RSTAND_1616 : STD_LOGIC; signal FSM_GPIF_v_setup_2_FFX_RSTAND_1617 : STD_LOGIC; signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_FFY_RSTAND_1618 : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9_FFY_RSTAND_1619 : STD_LOGIC; signal VCC : STD_LOGIC; signal GND : STD_LOGIC; signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count : STD_LOGIC_VECTOR ( 8 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w : STD_LOGIC_VECTOR ( 9 downto 1 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count : STD_LOGIC_VECTOR ( 9 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w : STD_LOGIC_VECTOR ( 8 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r : STD_LOGIC_VECTOR ( 9 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r : STD_LOGIC_VECTOR ( 8 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r : STD_LOGIC_VECTOR ( 9 downto 1 ); signal F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r : STD_LOGIC_VECTOR ( 8 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w : STD_LOGIC_VECTOR ( 8 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w : STD_LOGIC_VECTOR ( 9 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count : STD_LOGIC_VECTOR ( 8 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w : STD_LOGIC_VECTOR ( 8 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w : STD_LOGIC_VECTOR ( 9 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR : STD_LOGIC_VECTOR ( 9 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR : STD_LOGIC_VECTOR ( 8 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR : STD_LOGIC_VECTOR ( 8 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR : STD_LOGIC_VECTOR ( 9 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); signal s_dbus_out : STD_LOGIC_VECTOR ( 15 downto 0 ); signal FSM_GPIF_o_dbus : STD_LOGIC_VECTOR ( 15 downto 0 ); signal s_opb_in : STD_LOGIC_VECTOR ( 31 downto 0 ); signal Loopback_o_X2U_DATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal FSM_GPIF_v_setup : STD_LOGIC_VECTOR ( 3 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2 : STD_LOGIC_VECTOR ( 9 downto 1 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2 : STD_LOGIC_VECTOR ( 8 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2 : STD_LOGIC_VECTOR ( 8 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2 : STD_LOGIC_VECTOR ( 9 downto 1 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc : STD_LOGIC_VECTOR ( 8 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 1 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc : STD_LOGIC_VECTOR ( 8 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 1 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x : STD_LOGIC_VECTOR ( 8 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x : STD_LOGIC_VECTOR ( 9 downto 1 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x : STD_LOGIC_VECTOR ( 8 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x : STD_LOGIC_VECTOR ( 9 downto 1 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 0 downto 0 ); signal F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 0 downto 0 ); begin F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X42Y4" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_LOGIC_ZERO_18 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X42Y4" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_LOGIC_ZERO_18, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYINIT_15, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELF_16, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYINIT : X_BUF generic map( LOC => "SLICE_X42Y4", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYINIT_15 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELF : X_BUF generic map( LOC => "SLICE_X42Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(0), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELF_16 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X42Y4" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_LOGIC_ZERO_18, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet(0), SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELG_19, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYMUXG_17 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELG : X_BUF generic map( LOC => "SLICE_X42Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(1), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELG_19 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X42Y5" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_LOGIC_ZERO_26 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X42Y5" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_LOGIC_ZERO_26, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_LOGIC_ZERO_26, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELF_20, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXF2_25 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELF : X_BUF generic map( LOC => "SLICE_X42Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(2), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELF_20 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_FASTCARRY : X_BUF generic map( LOC => "SLICE_X42Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYMUXG_17, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_FASTCARRY_23 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYAND : X_AND2 generic map( LOC => "SLICE_X42Y5" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELG_27, I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELF_20, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYAND_22 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X42Y5" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXG2_24, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_FASTCARRY_23, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYAND_22, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXFAST_21 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X42Y5" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_LOGIC_ZERO_26, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXF2_25, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELG_27, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXG2_24 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELG : X_BUF generic map( LOC => "SLICE_X42Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELG_27 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X42Y6" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_LOGIC_ZERO_28 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X42Y6" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_LOGIC_ZERO_28, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYINIT_29, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYSELF_30, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYINIT : X_BUF generic map( LOC => "SLICE_X42Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXFAST_21, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYINIT_29 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYSELF : X_BUF generic map( LOC => "SLICE_X42Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYSELF_30 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1_4_not00001 : X_LUT4 generic map( INIT => X"C3C3", LOC => "SLICE_X42Y6" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(9), ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(8), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X30Y12" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_LOGIC_ZERO_34 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X30Y12" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_LOGIC_ZERO_34, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYINIT_31, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELF_32, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYINIT : X_BUF generic map( LOC => "SLICE_X30Y12", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYINIT_31 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELF : X_BUF generic map( LOC => "SLICE_X30Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELF_32 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X30Y12" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_LOGIC_ZERO_34, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet(0), SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELG_35, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYMUXG_33 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELG : X_BUF generic map( LOC => "SLICE_X30Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYSELG_35 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X30Y13" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_LOGIC_ZERO_42 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X30Y13" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_LOGIC_ZERO_42, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_LOGIC_ZERO_42, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELF_36, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXF2_41 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELF : X_BUF generic map( LOC => "SLICE_X30Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELF_36 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_FASTCARRY : X_BUF generic map( LOC => "SLICE_X30Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_1_CYMUXG_33, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_FASTCARRY_39 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYAND : X_AND2 generic map( LOC => "SLICE_X30Y13" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELG_43, I1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELF_36, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYAND_38 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X30Y13" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXG2_40, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_FASTCARRY_39, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYAND_38, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXFAST_37 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X30Y13" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_LOGIC_ZERO_42, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXF2_41, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELG_43, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXG2_40 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELG : X_BUF generic map( LOC => "SLICE_X30Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYSELG_43 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X30Y14" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_LOGIC_ZERO_44 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X30Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_LOGIC_ZERO_44, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYINIT_45, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYSELF_46, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYINIT : X_BUF generic map( LOC => "SLICE_X30Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_carrynet_3_CYMUXFAST_37, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYINIT_45 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYSELF : X_BUF generic map( LOC => "SLICE_X30Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2_CYSELF_46 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1_4_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X30Y14" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(7), ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(8), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(8), ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(9), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X36Y6" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_LOGIC_ZERO_50 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X36Y6" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_LOGIC_ZERO_50, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYINIT_47, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELF_48, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYINIT : X_BUF generic map( LOC => "SLICE_X36Y6", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYINIT_47 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELF : X_BUF generic map( LOC => "SLICE_X36Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(0), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELF_48 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X36Y6" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_LOGIC_ZERO_50, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet(0), SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELG_51, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYMUXG_49 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELG : X_BUF generic map( LOC => "SLICE_X36Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(1), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELG_51 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X36Y7" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_LOGIC_ZERO_58 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X36Y7" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_LOGIC_ZERO_58, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_LOGIC_ZERO_58, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELF_52, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXF2_57 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELF : X_BUF generic map( LOC => "SLICE_X36Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(2), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELF_52 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_FASTCARRY : X_BUF generic map( LOC => "SLICE_X36Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYMUXG_49, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_FASTCARRY_55 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYAND : X_AND2 generic map( LOC => "SLICE_X36Y7" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELG_59, I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELF_52, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYAND_54 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X36Y7" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXG2_56, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_FASTCARRY_55, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYAND_54, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXFAST_53 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X36Y7" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_LOGIC_ZERO_58, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXF2_57, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELG_59, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXG2_56 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELG : X_BUF generic map( LOC => "SLICE_X36Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELG_59 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X36Y8" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_LOGIC_ZERO_60 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X36Y8" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_LOGIC_ZERO_60, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYINIT_61, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYSELF_62, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYINIT : X_BUF generic map( LOC => "SLICE_X36Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXFAST_53, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYINIT_61 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYSELF : X_BUF generic map( LOC => "SLICE_X36Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYSELF_62 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1_4_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X36Y8" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(9), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(7), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(8), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(8), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X26Y4" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_LOGIC_ZERO_66 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X26Y4" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_LOGIC_ZERO_66, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYINIT_63, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELF_64, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYINIT : X_BUF generic map( LOC => "SLICE_X26Y4", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYINIT_63 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELF : X_BUF generic map( LOC => "SLICE_X26Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELF_64 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X26Y4" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_LOGIC_ZERO_66, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet(0), SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELG_67, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYMUXG_65 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELG : X_BUF generic map( LOC => "SLICE_X26Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYSELG_67 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X26Y5" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_LOGIC_ZERO_74 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X26Y5" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_LOGIC_ZERO_74, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_LOGIC_ZERO_74, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELF_68, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXF2_73 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELF : X_BUF generic map( LOC => "SLICE_X26Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELF_68 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_FASTCARRY : X_BUF generic map( LOC => "SLICE_X26Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_1_CYMUXG_65, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_FASTCARRY_71 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYAND : X_AND2 generic map( LOC => "SLICE_X26Y5" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELG_75, I1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELF_68, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYAND_70 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X26Y5" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXG2_72, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_FASTCARRY_71, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYAND_70, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXFAST_69 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X26Y5" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_LOGIC_ZERO_74, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXF2_73, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELG_75, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXG2_72 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELG : X_BUF generic map( LOC => "SLICE_X26Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYSELG_75 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X26Y6" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_LOGIC_ZERO_76 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X26Y6" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_LOGIC_ZERO_76, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYINIT_77, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYSELF_78, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYINIT : X_BUF generic map( LOC => "SLICE_X26Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_carrynet_3_CYMUXFAST_69, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYINIT_77 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYSELF : X_BUF generic map( LOC => "SLICE_X26Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out_CYSELF_78 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1_4_not00001 : X_LUT4 generic map( INIT => X"F00F", LOC => "SLICE_X26Y6" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(8), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(9), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X45Y2" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_LOGIC_ZERO_82 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X45Y2" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_LOGIC_ZERO_82, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYINIT_79, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELF_80, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYINIT : X_BUF generic map( LOC => "SLICE_X45Y2", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYINIT_79 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELF : X_BUF generic map( LOC => "SLICE_X45Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(0), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELF_80 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X45Y2" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_LOGIC_ZERO_82, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet(0), SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELG_83, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYMUXG_81 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELG : X_BUF generic map( LOC => "SLICE_X45Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(1), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELG_83 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X45Y3" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_LOGIC_ZERO_90 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X45Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_LOGIC_ZERO_90, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_LOGIC_ZERO_90, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELF_84, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXF2_89 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELF : X_BUF generic map( LOC => "SLICE_X45Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(2), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELF_84 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_FASTCARRY : X_BUF generic map( LOC => "SLICE_X45Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYMUXG_81, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_FASTCARRY_87 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYAND : X_AND2 generic map( LOC => "SLICE_X45Y3" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELG_91, I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELF_84, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYAND_86 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X45Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXG2_88, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_FASTCARRY_87, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYAND_86, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXFAST_85 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X45Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_LOGIC_ZERO_90, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXF2_89, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELG_91, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXG2_88 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELG : X_BUF generic map( LOC => "SLICE_X45Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELG_91 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X45Y4" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_LOGIC_ZERO_92 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X45Y4" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_LOGIC_ZERO_92, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYINIT_93, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYSELF_94, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYINIT : X_BUF generic map( LOC => "SLICE_X45Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXFAST_85, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYINIT_93 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYSELF : X_BUF generic map( LOC => "SLICE_X45Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYSELF_94 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1_4_not00001 : X_LUT4 generic map( INIT => X"F00F", LOC => "SLICE_X45Y4" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(8), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(9), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X27Y14" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_LOGIC_ZERO_98 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X27Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_LOGIC_ZERO_98, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYINIT_95, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELF_96, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYINIT : X_BUF generic map( LOC => "SLICE_X27Y14", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYINIT_95 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELF : X_BUF generic map( LOC => "SLICE_X27Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELF_96 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X27Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_LOGIC_ZERO_98, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet(0), SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELG_99, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYMUXG_97 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELG : X_BUF generic map( LOC => "SLICE_X27Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYSELG_99 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X27Y15" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_LOGIC_ZERO_106 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X27Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_LOGIC_ZERO_106, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_LOGIC_ZERO_106, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELF_100, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXF2_105 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELF : X_BUF generic map( LOC => "SLICE_X27Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELF_100 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_FASTCARRY : X_BUF generic map( LOC => "SLICE_X27Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_1_CYMUXG_97, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_FASTCARRY_103 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYAND : X_AND2 generic map( LOC => "SLICE_X27Y15" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELG_107, I1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELF_100, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYAND_102 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X27Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXG2_104, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_FASTCARRY_103, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYAND_102, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXFAST_101 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X27Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_LOGIC_ZERO_106, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXF2_105, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELG_107, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXG2_104 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELG : X_BUF generic map( LOC => "SLICE_X27Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYSELG_107 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X27Y16" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_LOGIC_ZERO_108 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X27Y16" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_LOGIC_ZERO_108, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYINIT_109, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYSELF_110, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYINIT : X_BUF generic map( LOC => "SLICE_X27Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_carrynet_3_CYMUXFAST_101, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYINIT_109 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYSELF : X_BUF generic map( LOC => "SLICE_X27Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1_CYSELF_110 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1_4_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X27Y16" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(7), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(8), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(8), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(9), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X28Y2" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_LOGIC_ZERO_114 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X28Y2" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_LOGIC_ZERO_114, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYINIT_111, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYSELF_112, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYINIT : X_BUF generic map( LOC => "SLICE_X28Y2", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYINIT_111 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYSELF : X_BUF generic map( LOC => "SLICE_X28Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYSELF_112 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X28Y2" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_LOGIC_ZERO_114, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet(0), SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYSELG_115, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYMUXG_113 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYSELG : X_BUF generic map( LOC => "SLICE_X28Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYSELG_115 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X28Y3" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_LOGIC_ZERO_122 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X28Y3" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_LOGIC_ZERO_122, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_LOGIC_ZERO_122, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYSELF_116, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYMUXF2_121 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYSELF : X_BUF generic map( LOC => "SLICE_X28Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYSELF_116 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_FASTCARRY : X_BUF generic map( LOC => "SLICE_X28Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_1_CYMUXG_113, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_FASTCARRY_119 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYAND : X_AND2 generic map( LOC => "SLICE_X28Y3" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYSELG_123, I1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYSELF_116, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYAND_118 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X28Y3" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYMUXG2_120, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_FASTCARRY_119, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYAND_118, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYMUXFAST_117 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X28Y3" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_LOGIC_ZERO_122, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYMUXF2_121, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYSELG_123, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYMUXG2_120 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYSELG : X_BUF generic map( LOC => "SLICE_X28Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYSELG_123 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X28Y4" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2_LOGIC_ZERO_124 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X28Y4" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2_LOGIC_ZERO_124, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2_CYINIT_125, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2_CYSELF_126, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2_CYINIT : X_BUF generic map( LOC => "SLICE_X28Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_carrynet_3_CYMUXFAST_117, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2_CYINIT_125 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2_CYSELF : X_BUF generic map( LOC => "SLICE_X28Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2_CYSELF_126 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1_4_not00001 : X_LUT4 generic map( INIT => X"AA55", LOC => "SLICE_X28Y4" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(9), ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(8), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X24Y2" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_LOGIC_ZERO_130 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X24Y2" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_LOGIC_ZERO_130, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYINIT_127, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYSELF_128, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYINIT : X_BUF generic map( LOC => "SLICE_X24Y2", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYINIT_127 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYSELF : X_BUF generic map( LOC => "SLICE_X24Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYSELF_128 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X24Y2" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_LOGIC_ZERO_130, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet(0), SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYSELG_131, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYMUXG_129 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYSELG : X_BUF generic map( LOC => "SLICE_X24Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYSELG_131 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X24Y3" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_LOGIC_ZERO_138 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X24Y3" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_LOGIC_ZERO_138, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_LOGIC_ZERO_138, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYSELF_132, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYMUXF2_137 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYSELF : X_BUF generic map( LOC => "SLICE_X24Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYSELF_132 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_FASTCARRY : X_BUF generic map( LOC => "SLICE_X24Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_1_CYMUXG_129, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_FASTCARRY_135 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYAND : X_AND2 generic map( LOC => "SLICE_X24Y3" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYSELG_139, I1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYSELF_132, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYAND_134 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X24Y3" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYMUXG2_136, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_FASTCARRY_135, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYAND_134, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYMUXFAST_133 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X24Y3" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_LOGIC_ZERO_138, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYMUXF2_137, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYSELG_139, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYMUXG2_136 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYSELG : X_BUF generic map( LOC => "SLICE_X24Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYSELG_139 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X24Y4" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1_LOGIC_ZERO_140 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X24Y4" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1_LOGIC_ZERO_140, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1_CYINIT_141, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1_CYSELF_142, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1_CYINIT : X_BUF generic map( LOC => "SLICE_X24Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_carrynet_3_CYMUXFAST_133, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1_CYINIT_141 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1_CYSELF : X_BUF generic map( LOC => "SLICE_X24Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1_CYSELF_142 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1_4_not00001 : X_LUT4 generic map( INIT => X"AA55", LOC => "SLICE_X24Y4" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(8), ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(9), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X41Y2" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_LOGIC_ZERO_146 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X41Y2" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_LOGIC_ZERO_146, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYINIT_143, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELF_144, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYINIT : X_BUF generic map( LOC => "SLICE_X41Y2", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYINIT_143 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELF : X_BUF generic map( LOC => "SLICE_X41Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(0), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELF_144 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X41Y2" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_LOGIC_ZERO_146, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet(0), SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELG_147, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYMUXG_145 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELG : X_BUF generic map( LOC => "SLICE_X41Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(1), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELG_147 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X41Y3" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_LOGIC_ZERO_154 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X41Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_LOGIC_ZERO_154, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_LOGIC_ZERO_154, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELF_148, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXF2_153 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELF : X_BUF generic map( LOC => "SLICE_X41Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(2), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELF_148 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_FASTCARRY : X_BUF generic map( LOC => "SLICE_X41Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYMUXG_145, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_FASTCARRY_151 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYAND : X_AND2 generic map( LOC => "SLICE_X41Y3" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELG_155, I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELF_148, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYAND_150 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X41Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXG2_152, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_FASTCARRY_151, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYAND_150, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXFAST_149 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X41Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_LOGIC_ZERO_154, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXF2_153, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELG_155, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXG2_152 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELG : X_BUF generic map( LOC => "SLICE_X41Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELG_155 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X41Y4" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_LOGIC_ZERO_156 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X41Y4" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_LOGIC_ZERO_156, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYINIT_157, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYSELF_158, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYINIT : X_BUF generic map( LOC => "SLICE_X41Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXFAST_149, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYINIT_157 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYSELF : X_BUF generic map( LOC => "SLICE_X41Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYSELF_158 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1_4_not00001 : X_LUT4 generic map( INIT => X"9999", LOC => "SLICE_X41Y4" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(8), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(9), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X28Y14" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_LOGIC_ZERO_162 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X28Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_LOGIC_ZERO_162, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYINIT_159, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELF_160, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYINIT : X_BUF generic map( LOC => "SLICE_X28Y14", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYINIT_159 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELF : X_BUF generic map( LOC => "SLICE_X28Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELF_160 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X28Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_LOGIC_ZERO_162, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet(0), SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELG_163, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYMUXG_161 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELG : X_BUF generic map( LOC => "SLICE_X28Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYSELG_163 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X28Y15" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_LOGIC_ZERO_170 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X28Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_LOGIC_ZERO_170, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_LOGIC_ZERO_170, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELF_164, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXF2_169 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELF : X_BUF generic map( LOC => "SLICE_X28Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELF_164 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_FASTCARRY : X_BUF generic map( LOC => "SLICE_X28Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_1_CYMUXG_161, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_FASTCARRY_167 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYAND : X_AND2 generic map( LOC => "SLICE_X28Y15" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELG_171, I1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELF_164, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYAND_166 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X28Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXG2_168, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_FASTCARRY_167, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYAND_166, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXFAST_165 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X28Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_LOGIC_ZERO_170, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXF2_169, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELG_171, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXG2_168 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELG : X_BUF generic map( LOC => "SLICE_X28Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYSELG_171 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X28Y16" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_LOGIC_ZERO_172 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X28Y16" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_LOGIC_ZERO_172, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYINIT_173, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYSELF_174, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYINIT : X_BUF generic map( LOC => "SLICE_X28Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_carrynet_3_CYMUXFAST_165, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYINIT_173 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYSELF : X_BUF generic map( LOC => "SLICE_X28Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1_CYSELF_174 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1_4_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X28Y16" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(7), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(9), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(8), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(8), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X37Y6" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_LOGIC_ZERO_178 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X37Y6" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_LOGIC_ZERO_178, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYINIT_175, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELF_176, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYINIT : X_BUF generic map( LOC => "SLICE_X37Y6", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYINIT_175 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELF : X_BUF generic map( LOC => "SLICE_X37Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(0), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELF_176 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X37Y6" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_LOGIC_ZERO_178, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet(0), SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELG_179, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYMUXG_177 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELG : X_BUF generic map( LOC => "SLICE_X37Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(1), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELG_179 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X37Y7" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_LOGIC_ZERO_186 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X37Y7" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_LOGIC_ZERO_186, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_LOGIC_ZERO_186, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELF_180, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXF2_185 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELF : X_BUF generic map( LOC => "SLICE_X37Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(2), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELF_180 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_FASTCARRY : X_BUF generic map( LOC => "SLICE_X37Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYMUXG_177, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_FASTCARRY_183 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYAND : X_AND2 generic map( LOC => "SLICE_X37Y7" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELG_187, I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELF_180, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYAND_182 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X37Y7" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXG2_184, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_FASTCARRY_183, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYAND_182, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXFAST_181 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X37Y7" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_LOGIC_ZERO_186, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXF2_185, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELG_187, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXG2_184 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELG : X_BUF generic map( LOC => "SLICE_X37Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELG_187 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X37Y8" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_LOGIC_ZERO_188 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X37Y8" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_LOGIC_ZERO_188, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYINIT_189, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYSELF_190, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYINIT : X_BUF generic map( LOC => "SLICE_X37Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXFAST_181, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYINIT_189 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYSELF : X_BUF generic map( LOC => "SLICE_X37Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYSELF_190 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1_4_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X37Y8" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(8), ADR1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(9), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(7), ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(8), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X27Y4" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_LOGIC_ZERO_194 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X27Y4" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_LOGIC_ZERO_194, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYINIT_191, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELF_192, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYINIT : X_BUF generic map( LOC => "SLICE_X27Y4", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYINIT_191 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELF : X_BUF generic map( LOC => "SLICE_X27Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELF_192 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X27Y4" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_LOGIC_ZERO_194, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet(0), SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELG_195, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYMUXG_193 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELG : X_BUF generic map( LOC => "SLICE_X27Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYSELG_195 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X27Y5" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_LOGIC_ZERO_202 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X27Y5" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_LOGIC_ZERO_202, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_LOGIC_ZERO_202, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELF_196, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXF2_201 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELF : X_BUF generic map( LOC => "SLICE_X27Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELF_196 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_FASTCARRY : X_BUF generic map( LOC => "SLICE_X27Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_1_CYMUXG_193, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_FASTCARRY_199 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYAND : X_AND2 generic map( LOC => "SLICE_X27Y5" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELG_203, I1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELF_196, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYAND_198 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X27Y5" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXG2_200, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_FASTCARRY_199, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYAND_198, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXFAST_197 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X27Y5" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_LOGIC_ZERO_202, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXF2_201, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELG_203, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXG2_200 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELG : X_BUF generic map( LOC => "SLICE_X27Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYSELG_203 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X27Y6" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_LOGIC_ZERO_204 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X27Y6" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_LOGIC_ZERO_204, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYINIT_205, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYSELF_206, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYINIT : X_BUF generic map( LOC => "SLICE_X27Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_carrynet_3_CYMUXFAST_197, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYINIT_205 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYSELF : X_BUF generic map( LOC => "SLICE_X27Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out_CYSELF_206 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1_4_not00001 : X_LUT4 generic map( INIT => X"AA55", LOC => "SLICE_X27Y6" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(9), ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(8), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X43Y2" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_LOGIC_ZERO_210 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X43Y2" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_LOGIC_ZERO_210, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYINIT_207, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELF_208, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYINIT : X_BUF generic map( LOC => "SLICE_X43Y2", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYINIT_207 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELF : X_BUF generic map( LOC => "SLICE_X43Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(0), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELF_208 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X43Y2" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_LOGIC_ZERO_210, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet(0), SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELG_211, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYMUXG_209 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELG : X_BUF generic map( LOC => "SLICE_X43Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(1), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELG_211 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X43Y3" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_LOGIC_ZERO_218 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X43Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_LOGIC_ZERO_218, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_LOGIC_ZERO_218, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELF_212, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXF2_217 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELF : X_BUF generic map( LOC => "SLICE_X43Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(2), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELF_212 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_FASTCARRY : X_BUF generic map( LOC => "SLICE_X43Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYMUXG_209, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_FASTCARRY_215 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYAND : X_AND2 generic map( LOC => "SLICE_X43Y3" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELG_219, I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELF_212, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYAND_214 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X43Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXG2_216, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_FASTCARRY_215, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYAND_214, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXFAST_213 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X43Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_LOGIC_ZERO_218, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXF2_217, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELG_219, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXG2_216 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELG : X_BUF generic map( LOC => "SLICE_X43Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELG_219 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X43Y4" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_LOGIC_ZERO_220 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X43Y4" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_LOGIC_ZERO_220, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYINIT_221, SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYSELF_222, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYINIT : X_BUF generic map( LOC => "SLICE_X43Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXFAST_213, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYINIT_221 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYSELF : X_BUF generic map( LOC => "SLICE_X43Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYSELF_222 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1_4_not00001 : X_LUT4 generic map( INIT => X"AA55", LOC => "SLICE_X43Y4" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(8), ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(9), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X29Y14" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_LOGIC_ZERO_226 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X29Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_LOGIC_ZERO_226, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYINIT_223, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELF_224, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYINIT : X_BUF generic map( LOC => "SLICE_X29Y14", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYINIT_223 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELF : X_BUF generic map( LOC => "SLICE_X29Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELF_224 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X29Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_LOGIC_ZERO_226, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet(0), SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELG_227, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYMUXG_225 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELG : X_BUF generic map( LOC => "SLICE_X29Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYSELG_227 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X29Y15" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_LOGIC_ZERO_234 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X29Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_LOGIC_ZERO_234, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_LOGIC_ZERO_234, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELF_228, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXF2_233 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELF : X_BUF generic map( LOC => "SLICE_X29Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELF_228 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_FASTCARRY : X_BUF generic map( LOC => "SLICE_X29Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_1_CYMUXG_225, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_FASTCARRY_231 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYAND : X_AND2 generic map( LOC => "SLICE_X29Y15" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELG_235, I1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELF_228, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYAND_230 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X29Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXG2_232, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_FASTCARRY_231, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYAND_230, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXFAST_229 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X29Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_LOGIC_ZERO_234, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXF2_233, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELG_235, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXG2_232 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELG : X_BUF generic map( LOC => "SLICE_X29Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYSELG_235 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X29Y16" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_LOGIC_ZERO_236 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X29Y16" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_LOGIC_ZERO_236, IB => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYINIT_237, SEL => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYSELF_238, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYINIT : X_BUF generic map( LOC => "SLICE_X29Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_carrynet_3_CYMUXFAST_229, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYINIT_237 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYSELF : X_BUF generic map( LOC => "SLICE_X29Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2_CYSELF_238 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1_4_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X29Y16" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(7), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(8), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(9), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(8), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(4) ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X53Y10" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ZERO_246 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ONE : X_ONE generic map( LOC => "SLICE_X53Y10" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ONE_240 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DXMUX : X_BUF generic map( LOC => "SLICE_X53Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DXMUX_239 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X53Y10" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ONE_240, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYINIT_241, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELF_242, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0) ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYINIT : X_BUF generic map( LOC => "SLICE_X53Y10", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYINIT_241 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELF : X_BUF generic map( LOC => "SLICE_X53Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELF_242 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DYMUX : X_BUF generic map( LOC => "SLICE_X53Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_XORG_244, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DYMUX_243 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_XORG : X_XOR2 generic map( LOC => "SLICE_X53Y10" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0), I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_XORG_244 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_COUTUSED : X_BUF generic map( LOC => "SLICE_X53Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYMUXG_245, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1) ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X53Y10" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ZERO_246, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0), SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELG_247, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYMUXG_245 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELG : X_BUF generic map( LOC => "SLICE_X53Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELG_247 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_SRINV : X_BUF generic map( LOC => "SLICE_X53Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_SRINV_248 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CLKINV : X_BUF generic map( LOC => "SLICE_X53Y10", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CLKINV_249 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CEINV : X_BUF generic map( LOC => "SLICE_X53Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CEINV_250 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X53Y11" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_LOGIC_ZERO_262 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DXMUX : X_BUF generic map( LOC => "SLICE_X53Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORF_252, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DXMUX_251 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORF : X_XOR2 generic map( LOC => "SLICE_X53Y11" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYINIT_253, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_F, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORF_252 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X53Y11" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_LOGIC_ZERO_262, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYINIT_253, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELF_256, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(2) ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X53Y11" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_LOGIC_ZERO_262, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_LOGIC_ZERO_262, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELF_256, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXF2_261 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYINIT : X_BUF generic map( LOC => "SLICE_X53Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYINIT_253 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELF : X_BUF generic map( LOC => "SLICE_X53Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_F, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELF_256 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DYMUX : X_BUF generic map( LOC => "SLICE_X53Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORG_255, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DYMUX_254 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORG : X_XOR2 generic map( LOC => "SLICE_X53Y11" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(2), I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORG_255 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_COUTUSED : X_BUF generic map( LOC => "SLICE_X53Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXFAST_257, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3) ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_FASTCARRY : X_BUF generic map( LOC => "SLICE_X53Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_FASTCARRY_259 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYAND : X_AND2 generic map( LOC => "SLICE_X53Y11" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELG_263, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELF_256, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYAND_258 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X53Y11" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXG2_260, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_FASTCARRY_259, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYAND_258, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXFAST_257 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X53Y11" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_LOGIC_ZERO_262, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXF2_261, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELG_263, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXG2_260 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELG : X_BUF generic map( LOC => "SLICE_X53Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELG_263 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_SRINV : X_BUF generic map( LOC => "SLICE_X53Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_SRINV_264 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CLKINV : X_BUF generic map( LOC => "SLICE_X53Y11", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CLKINV_265 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CEINV : X_BUF generic map( LOC => "SLICE_X53Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CEINV_266 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X53Y12" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_LOGIC_ZERO_278 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DXMUX : X_BUF generic map( LOC => "SLICE_X53Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORF_268, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DXMUX_267 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORF : X_XOR2 generic map( LOC => "SLICE_X53Y12" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYINIT_269, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_F, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORF_268 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X53Y12" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_LOGIC_ZERO_278, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYINIT_269, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELF_272, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(4) ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X53Y12" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_LOGIC_ZERO_278, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_LOGIC_ZERO_278, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELF_272, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXF2_277 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYINIT : X_BUF generic map( LOC => "SLICE_X53Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYINIT_269 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELF : X_BUF generic map( LOC => "SLICE_X53Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_F, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELF_272 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DYMUX : X_BUF generic map( LOC => "SLICE_X53Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORG_271, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DYMUX_270 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORG : X_XOR2 generic map( LOC => "SLICE_X53Y12" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(4), I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORG_271 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_COUTUSED : X_BUF generic map( LOC => "SLICE_X53Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXFAST_273, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5) ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_FASTCARRY : X_BUF generic map( LOC => "SLICE_X53Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_FASTCARRY_275 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYAND : X_AND2 generic map( LOC => "SLICE_X53Y12" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELG_279, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELF_272, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYAND_274 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X53Y12" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXG2_276, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_FASTCARRY_275, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYAND_274, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXFAST_273 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X53Y12" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_LOGIC_ZERO_278, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXF2_277, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELG_279, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXG2_276 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELG : X_BUF generic map( LOC => "SLICE_X53Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELG_279 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_SRINV : X_BUF generic map( LOC => "SLICE_X53Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_SRINV_280 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CLKINV : X_BUF generic map( LOC => "SLICE_X53Y12", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CLKINV_281 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CEINV : X_BUF generic map( LOC => "SLICE_X53Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CEINV_282 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X53Y13" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_LOGIC_ZERO_294 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DXMUX : X_BUF generic map( LOC => "SLICE_X53Y13", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORF_284, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DXMUX_283 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORF : X_XOR2 generic map( LOC => "SLICE_X53Y13" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYINIT_285, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_F, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORF_284 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X53Y13" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_LOGIC_ZERO_294, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYINIT_285, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELF_288, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(6) ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X53Y13" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_LOGIC_ZERO_294, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_LOGIC_ZERO_294, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELF_288, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXF2_293 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYINIT : X_BUF generic map( LOC => "SLICE_X53Y13", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYINIT_285 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELF : X_BUF generic map( LOC => "SLICE_X53Y13", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_F, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELF_288 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DYMUX : X_BUF generic map( LOC => "SLICE_X53Y13", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORG_287, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DYMUX_286 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORG : X_XOR2 generic map( LOC => "SLICE_X53Y13" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(6), I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORG_287 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_FASTCARRY : X_BUF generic map( LOC => "SLICE_X53Y13", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_FASTCARRY_291 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYAND : X_AND2 generic map( LOC => "SLICE_X53Y13" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELG_295, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELF_288, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYAND_290 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X53Y13" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXG2_292, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_FASTCARRY_291, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYAND_290, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXFAST_289 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X53Y13" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_LOGIC_ZERO_294, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXF2_293, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELG_295, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXG2_292 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELG : X_BUF generic map( LOC => "SLICE_X53Y13", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELG_295 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_SRINV : X_BUF generic map( LOC => "SLICE_X53Y13", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_SRINV_296 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CLKINV : X_BUF generic map( LOC => "SLICE_X53Y13", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CLKINV_297 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CEINV : X_BUF generic map( LOC => "SLICE_X53Y13", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CEINV_298 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_DXMUX : X_BUF generic map( LOC => "SLICE_X53Y14", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_XORF_300, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_DXMUX_299 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_XORF : X_XOR2 generic map( LOC => "SLICE_X53Y14" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CYINIT_301, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_rt_302, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_XORF_300 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CYINIT : X_BUF generic map( LOC => "SLICE_X53Y14", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXFAST_289, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CYINIT_301 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CLKINV : X_BUF generic map( LOC => "SLICE_X53Y14", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CLKINV_303 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CEINV : X_BUF generic map( LOC => "SLICE_X53Y14", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CEINV_304 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X44Y4" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ZERO_312 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ONE : X_ONE generic map( LOC => "SLICE_X44Y4" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ONE_306 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DXMUX : X_BUF generic map( LOC => "SLICE_X44Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DXMUX_305 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X44Y4" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ONE_306, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYINIT_307, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELF_308, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYINIT : X_BUF generic map( LOC => "SLICE_X44Y4", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYINIT_307 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELF : X_BUF generic map( LOC => "SLICE_X44Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELF_308 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DYMUX : X_BUF generic map( LOC => "SLICE_X44Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_XORG_310, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DYMUX_309 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_XORG : X_XOR2 generic map( LOC => "SLICE_X44Y4" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0), I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_XORG_310 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_COUTUSED : X_BUF generic map( LOC => "SLICE_X44Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYMUXG_311, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X44Y4" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ZERO_312, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0), SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELG_313, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYMUXG_311 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELG : X_BUF generic map( LOC => "SLICE_X44Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELG_313 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_SRINV : X_BUF generic map( LOC => "SLICE_X44Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_SRINV_314 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CLKINV : X_BUF generic map( LOC => "SLICE_X44Y4", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CLKINV_315 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CEINV : X_BUF generic map( LOC => "SLICE_X44Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CEINV_316 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X44Y5" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_LOGIC_ZERO_328 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DXMUX : X_BUF generic map( LOC => "SLICE_X44Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORF_318, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DXMUX_317 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORF : X_XOR2 generic map( LOC => "SLICE_X44Y5" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYINIT_319, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORF_318 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X44Y5" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_LOGIC_ZERO_328, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYINIT_319, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELF_322, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(2) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X44Y5" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_LOGIC_ZERO_328, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_LOGIC_ZERO_328, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELF_322, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXF2_327 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYINIT : X_BUF generic map( LOC => "SLICE_X44Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYINIT_319 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELF : X_BUF generic map( LOC => "SLICE_X44Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELF_322 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DYMUX : X_BUF generic map( LOC => "SLICE_X44Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORG_321, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DYMUX_320 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORG : X_XOR2 generic map( LOC => "SLICE_X44Y5" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(2), I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORG_321 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_COUTUSED : X_BUF generic map( LOC => "SLICE_X44Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXFAST_323, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_FASTCARRY : X_BUF generic map( LOC => "SLICE_X44Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_FASTCARRY_325 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYAND : X_AND2 generic map( LOC => "SLICE_X44Y5" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELG_329, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELF_322, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYAND_324 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X44Y5" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXG2_326, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_FASTCARRY_325, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYAND_324, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXFAST_323 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X44Y5" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_LOGIC_ZERO_328, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXF2_327, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELG_329, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXG2_326 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELG : X_BUF generic map( LOC => "SLICE_X44Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELG_329 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_SRINV : X_BUF generic map( LOC => "SLICE_X44Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_SRINV_330 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CLKINV : X_BUF generic map( LOC => "SLICE_X44Y5", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CLKINV_331 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CEINV : X_BUF generic map( LOC => "SLICE_X44Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CEINV_332 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X44Y6" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_LOGIC_ZERO_344 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DXMUX : X_BUF generic map( LOC => "SLICE_X44Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORF_334, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DXMUX_333 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORF : X_XOR2 generic map( LOC => "SLICE_X44Y6" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYINIT_335, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORF_334 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X44Y6" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_LOGIC_ZERO_344, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYINIT_335, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELF_338, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(4) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X44Y6" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_LOGIC_ZERO_344, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_LOGIC_ZERO_344, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELF_338, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXF2_343 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYINIT : X_BUF generic map( LOC => "SLICE_X44Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYINIT_335 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELF : X_BUF generic map( LOC => "SLICE_X44Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELF_338 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DYMUX : X_BUF generic map( LOC => "SLICE_X44Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORG_337, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DYMUX_336 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORG : X_XOR2 generic map( LOC => "SLICE_X44Y6" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(4), I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORG_337 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_COUTUSED : X_BUF generic map( LOC => "SLICE_X44Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXFAST_339, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_FASTCARRY : X_BUF generic map( LOC => "SLICE_X44Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_FASTCARRY_341 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYAND : X_AND2 generic map( LOC => "SLICE_X44Y6" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELG_345, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELF_338, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYAND_340 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X44Y6" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXG2_342, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_FASTCARRY_341, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYAND_340, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXFAST_339 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X44Y6" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_LOGIC_ZERO_344, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXF2_343, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELG_345, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXG2_342 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELG : X_BUF generic map( LOC => "SLICE_X44Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELG_345 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_SRINV : X_BUF generic map( LOC => "SLICE_X44Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_SRINV_346 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CLKINV : X_BUF generic map( LOC => "SLICE_X44Y6", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CLKINV_347 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CEINV : X_BUF generic map( LOC => "SLICE_X44Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CEINV_348 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X44Y7" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_LOGIC_ZERO_360 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DXMUX : X_BUF generic map( LOC => "SLICE_X44Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORF_350, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DXMUX_349 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORF : X_XOR2 generic map( LOC => "SLICE_X44Y7" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYINIT_351, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORF_350 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X44Y7" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_LOGIC_ZERO_360, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYINIT_351, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELF_354, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(6) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X44Y7" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_LOGIC_ZERO_360, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_LOGIC_ZERO_360, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELF_354, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXF2_359 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYINIT : X_BUF generic map( LOC => "SLICE_X44Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYINIT_351 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELF : X_BUF generic map( LOC => "SLICE_X44Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELF_354 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DYMUX : X_BUF generic map( LOC => "SLICE_X44Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORG_353, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DYMUX_352 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORG : X_XOR2 generic map( LOC => "SLICE_X44Y7" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(6), I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORG_353 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_FASTCARRY : X_BUF generic map( LOC => "SLICE_X44Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_FASTCARRY_357 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYAND : X_AND2 generic map( LOC => "SLICE_X44Y7" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELG_361, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELF_354, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYAND_356 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X44Y7" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXG2_358, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_FASTCARRY_357, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYAND_356, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXFAST_355 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X44Y7" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_LOGIC_ZERO_360, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXF2_359, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELG_361, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXG2_358 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELG : X_BUF generic map( LOC => "SLICE_X44Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELG_361 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_SRINV : X_BUF generic map( LOC => "SLICE_X44Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_SRINV_362 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CLKINV : X_BUF generic map( LOC => "SLICE_X44Y7", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CLKINV_363 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CEINV : X_BUF generic map( LOC => "SLICE_X44Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CEINV_364 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_DXMUX : X_BUF generic map( LOC => "SLICE_X44Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_XORF_366, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_DXMUX_365 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_XORF : X_XOR2 generic map( LOC => "SLICE_X44Y8" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CYINIT_367, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_rt_368, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_XORF_366 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CYINIT : X_BUF generic map( LOC => "SLICE_X44Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXFAST_355, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CYINIT_367 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CLKINV : X_BUF generic map( LOC => "SLICE_X44Y8", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CLKINV_369 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CEINV : X_BUF generic map( LOC => "SLICE_X44Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CEINV_370 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X40Y0" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ZERO_378 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ONE : X_ONE generic map( LOC => "SLICE_X40Y0" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ONE_372 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DXMUX : X_BUF generic map( LOC => "SLICE_X40Y0", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DXMUX_371 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X40Y0" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ONE_372, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYINIT_373, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELF_374, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYINIT : X_BUF generic map( LOC => "SLICE_X40Y0", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYINIT_373 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELF : X_BUF generic map( LOC => "SLICE_X40Y0", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELF_374 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DYMUX : X_BUF generic map( LOC => "SLICE_X40Y0", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_XORG_376, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DYMUX_375 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_XORG : X_XOR2 generic map( LOC => "SLICE_X40Y0" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0), I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_XORG_376 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_COUTUSED : X_BUF generic map( LOC => "SLICE_X40Y0", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYMUXG_377, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X40Y0" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ZERO_378, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0), SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELG_379, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYMUXG_377 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELG : X_BUF generic map( LOC => "SLICE_X40Y0", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELG_379 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_SRINV : X_BUF generic map( LOC => "SLICE_X40Y0", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_SRINV_380 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CLKINV : X_BUF generic map( LOC => "SLICE_X40Y0", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CLKINV_381 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CEINV : X_BUF generic map( LOC => "SLICE_X40Y0", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CEINV_382 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X40Y1" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_LOGIC_ZERO_394 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DXMUX : X_BUF generic map( LOC => "SLICE_X40Y1", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORF_384, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DXMUX_383 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORF : X_XOR2 generic map( LOC => "SLICE_X40Y1" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYINIT_385, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORF_384 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X40Y1" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_LOGIC_ZERO_394, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYINIT_385, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELF_388, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(2) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X40Y1" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_LOGIC_ZERO_394, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_LOGIC_ZERO_394, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELF_388, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXF2_393 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYINIT : X_BUF generic map( LOC => "SLICE_X40Y1", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYINIT_385 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELF : X_BUF generic map( LOC => "SLICE_X40Y1", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELF_388 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DYMUX : X_BUF generic map( LOC => "SLICE_X40Y1", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORG_387, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DYMUX_386 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORG : X_XOR2 generic map( LOC => "SLICE_X40Y1" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(2), I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORG_387 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_COUTUSED : X_BUF generic map( LOC => "SLICE_X40Y1", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXFAST_389, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_FASTCARRY : X_BUF generic map( LOC => "SLICE_X40Y1", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_FASTCARRY_391 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYAND : X_AND2 generic map( LOC => "SLICE_X40Y1" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELG_395, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELF_388, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYAND_390 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X40Y1" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXG2_392, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_FASTCARRY_391, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYAND_390, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXFAST_389 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X40Y1" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_LOGIC_ZERO_394, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXF2_393, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELG_395, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXG2_392 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELG : X_BUF generic map( LOC => "SLICE_X40Y1", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELG_395 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_SRINV : X_BUF generic map( LOC => "SLICE_X40Y1", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_SRINV_396 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CLKINV : X_BUF generic map( LOC => "SLICE_X40Y1", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CLKINV_397 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CEINV : X_BUF generic map( LOC => "SLICE_X40Y1", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CEINV_398 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X40Y2" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_LOGIC_ZERO_410 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DXMUX : X_BUF generic map( LOC => "SLICE_X40Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORF_400, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DXMUX_399 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORF : X_XOR2 generic map( LOC => "SLICE_X40Y2" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYINIT_401, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORF_400 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X40Y2" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_LOGIC_ZERO_410, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYINIT_401, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELF_404, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(4) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X40Y2" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_LOGIC_ZERO_410, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_LOGIC_ZERO_410, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELF_404, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXF2_409 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYINIT : X_BUF generic map( LOC => "SLICE_X40Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYINIT_401 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELF : X_BUF generic map( LOC => "SLICE_X40Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELF_404 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DYMUX : X_BUF generic map( LOC => "SLICE_X40Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORG_403, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DYMUX_402 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORG : X_XOR2 generic map( LOC => "SLICE_X40Y2" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(4), I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORG_403 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_COUTUSED : X_BUF generic map( LOC => "SLICE_X40Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXFAST_405, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_FASTCARRY : X_BUF generic map( LOC => "SLICE_X40Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_FASTCARRY_407 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYAND : X_AND2 generic map( LOC => "SLICE_X40Y2" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELG_411, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELF_404, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYAND_406 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X40Y2" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXG2_408, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_FASTCARRY_407, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYAND_406, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXFAST_405 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X40Y2" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_LOGIC_ZERO_410, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXF2_409, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELG_411, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXG2_408 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELG : X_BUF generic map( LOC => "SLICE_X40Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELG_411 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_SRINV : X_BUF generic map( LOC => "SLICE_X40Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_SRINV_412 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CLKINV : X_BUF generic map( LOC => "SLICE_X40Y2", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CLKINV_413 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CEINV : X_BUF generic map( LOC => "SLICE_X40Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CEINV_414 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X40Y3" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_LOGIC_ZERO_426 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DXMUX : X_BUF generic map( LOC => "SLICE_X40Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORF_416, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DXMUX_415 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORF : X_XOR2 generic map( LOC => "SLICE_X40Y3" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYINIT_417, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORF_416 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X40Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_LOGIC_ZERO_426, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYINIT_417, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELF_420, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(6) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X40Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_LOGIC_ZERO_426, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_LOGIC_ZERO_426, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELF_420, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXF2_425 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYINIT : X_BUF generic map( LOC => "SLICE_X40Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYINIT_417 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELF : X_BUF generic map( LOC => "SLICE_X40Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELF_420 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DYMUX : X_BUF generic map( LOC => "SLICE_X40Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORG_419, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DYMUX_418 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORG : X_XOR2 generic map( LOC => "SLICE_X40Y3" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(6), I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORG_419 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_FASTCARRY : X_BUF generic map( LOC => "SLICE_X40Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_FASTCARRY_423 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYAND : X_AND2 generic map( LOC => "SLICE_X40Y3" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELG_427, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELF_420, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYAND_422 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X40Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXG2_424, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_FASTCARRY_423, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYAND_422, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXFAST_421 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X40Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_LOGIC_ZERO_426, IB => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXF2_425, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELG_427, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXG2_424 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELG : X_BUF generic map( LOC => "SLICE_X40Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELG_427 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_SRINV : X_BUF generic map( LOC => "SLICE_X40Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_SRINV_428 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CLKINV : X_BUF generic map( LOC => "SLICE_X40Y3", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CLKINV_429 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CEINV : X_BUF generic map( LOC => "SLICE_X40Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CEINV_430 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_DXMUX : X_BUF generic map( LOC => "SLICE_X40Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_XORF_432, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_DXMUX_431 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_XORF : X_XOR2 generic map( LOC => "SLICE_X40Y4" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CYINIT_433, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_rt_434, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_XORF_432 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CYINIT : X_BUF generic map( LOC => "SLICE_X40Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXFAST_421, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CYINIT_433 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CLKINV : X_BUF generic map( LOC => "SLICE_X40Y4", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CLKINV_435 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CEINV : X_BUF generic map( LOC => "SLICE_X40Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CEINV_436 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X38Y2" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ZERO_444 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ONE : X_ONE generic map( LOC => "SLICE_X38Y2" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ONE_438 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DXMUX : X_BUF generic map( LOC => "SLICE_X38Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0) , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DXMUX_437 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X38Y2" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ONE_438 , IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYINIT_439 , SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELF_440 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYINIT : X_BUF generic map( LOC => "SLICE_X38Y2", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYINIT_439 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELF : X_BUF generic map( LOC => "SLICE_X38Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0) , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELF_440 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DYMUX : X_BUF generic map( LOC => "SLICE_X38Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_XORG_442 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DYMUX_441 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_XORG : X_XOR2 generic map( LOC => "SLICE_X38Y2" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0) , I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_G , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_XORG_442 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_COUTUSED : X_BUF generic map( LOC => "SLICE_X38Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYMUXG_443 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X38Y2" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ZERO_444 , IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0) , SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELG_445 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYMUXG_443 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELG : X_BUF generic map( LOC => "SLICE_X38Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_G , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELG_445 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_SRINV : X_BUF generic map( LOC => "SLICE_X38Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_SRINV_446 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CLKINV : X_BUF generic map( LOC => "SLICE_X38Y2", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CLKINV_447 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CEINV : X_BUF generic map( LOC => "SLICE_X38Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CEINV_448 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X38Y3" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_460 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DXMUX : X_BUF generic map( LOC => "SLICE_X38Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORF_450 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DXMUX_449 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORF : X_XOR2 generic map( LOC => "SLICE_X38Y3" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYINIT_451 , I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_F , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORF_450 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X38Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_460 , IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYINIT_451 , SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF_454 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X38Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_460 , IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_460 , SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF_454 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXF2_459 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYINIT : X_BUF generic map( LOC => "SLICE_X38Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1) , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYINIT_451 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF : X_BUF generic map( LOC => "SLICE_X38Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_F , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF_454 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DYMUX : X_BUF generic map( LOC => "SLICE_X38Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORG_453 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DYMUX_452 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORG : X_XOR2 generic map( LOC => "SLICE_X38Y3" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(2) , I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_G , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORG_453 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_COUTUSED : X_BUF generic map( LOC => "SLICE_X38Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXFAST_455 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_FASTCARRY : X_BUF generic map( LOC => "SLICE_X38Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1) , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_FASTCARRY_457 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYAND : X_AND2 generic map( LOC => "SLICE_X38Y3" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELG_461 , I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF_454 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYAND_456 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X38Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXG2_458 , IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_FASTCARRY_457 , SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYAND_456 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXFAST_455 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X38Y3" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_460 , IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXF2_459 , SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELG_461 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXG2_458 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELG : X_BUF generic map( LOC => "SLICE_X38Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_G , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELG_461 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_SRINV : X_BUF generic map( LOC => "SLICE_X38Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_SRINV_462 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CLKINV : X_BUF generic map( LOC => "SLICE_X38Y3", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CLKINV_463 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CEINV : X_BUF generic map( LOC => "SLICE_X38Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CEINV_464 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X38Y4" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_476 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DXMUX : X_BUF generic map( LOC => "SLICE_X38Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORF_466 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DXMUX_465 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORF : X_XOR2 generic map( LOC => "SLICE_X38Y4" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYINIT_467 , I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_F , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORF_466 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X38Y4" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_476 , IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYINIT_467 , SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF_470 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X38Y4" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_476 , IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_476 , SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF_470 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXF2_475 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYINIT : X_BUF generic map( LOC => "SLICE_X38Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3) , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYINIT_467 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF : X_BUF generic map( LOC => "SLICE_X38Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_F , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF_470 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DYMUX : X_BUF generic map( LOC => "SLICE_X38Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORG_469 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DYMUX_468 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORG : X_XOR2 generic map( LOC => "SLICE_X38Y4" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(4) , I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_G , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORG_469 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_COUTUSED : X_BUF generic map( LOC => "SLICE_X38Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXFAST_471 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_FASTCARRY : X_BUF generic map( LOC => "SLICE_X38Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3) , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_FASTCARRY_473 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYAND : X_AND2 generic map( LOC => "SLICE_X38Y4" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELG_477 , I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF_470 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYAND_472 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X38Y4" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXG2_474 , IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_FASTCARRY_473 , SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYAND_472 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXFAST_471 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X38Y4" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_476 , IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXF2_475 , SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELG_477 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXG2_474 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELG : X_BUF generic map( LOC => "SLICE_X38Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_G , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELG_477 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_SRINV : X_BUF generic map( LOC => "SLICE_X38Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_SRINV_478 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CLKINV : X_BUF generic map( LOC => "SLICE_X38Y4", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CLKINV_479 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CEINV : X_BUF generic map( LOC => "SLICE_X38Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CEINV_480 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X38Y5" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_492 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DXMUX : X_BUF generic map( LOC => "SLICE_X38Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORF_482 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DXMUX_481 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORF : X_XOR2 generic map( LOC => "SLICE_X38Y5" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYINIT_483 , I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_F , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORF_482 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X38Y5" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_492 , IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYINIT_483 , SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF_486 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X38Y5" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_492 , IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_492 , SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF_486 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXF2_491 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYINIT : X_BUF generic map( LOC => "SLICE_X38Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5) , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYINIT_483 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF : X_BUF generic map( LOC => "SLICE_X38Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_F , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF_486 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DYMUX : X_BUF generic map( LOC => "SLICE_X38Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORG_485 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DYMUX_484 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORG : X_XOR2 generic map( LOC => "SLICE_X38Y5" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(6) , I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_G , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORG_485 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_FASTCARRY : X_BUF generic map( LOC => "SLICE_X38Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5) , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_FASTCARRY_489 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYAND : X_AND2 generic map( LOC => "SLICE_X38Y5" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELG_493 , I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF_486 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYAND_488 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X38Y5" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXG2_490 , IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_FASTCARRY_489 , SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYAND_488 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXFAST_487 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X38Y5" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_492 , IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXF2_491 , SEL => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELG_493 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXG2_490 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELG : X_BUF generic map( LOC => "SLICE_X38Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_G , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELG_493 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_SRINV : X_BUF generic map( LOC => "SLICE_X38Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_SRINV_494 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CLKINV : X_BUF generic map( LOC => "SLICE_X38Y5", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CLKINV_495 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CEINV : X_BUF generic map( LOC => "SLICE_X38Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CEINV_496 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DXMUX : X_BUF generic map( LOC => "SLICE_X38Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORF_498 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DXMUX_497 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORF : X_XOR2 generic map( LOC => "SLICE_X38Y6" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYINIT_499 , I1 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_rt_500 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORF_498 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYINIT : X_BUF generic map( LOC => "SLICE_X38Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXFAST_487 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYINIT_499 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CLKINV : X_BUF generic map( LOC => "SLICE_X38Y6", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CLKINV_501 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CEINV : X_BUF generic map( LOC => "SLICE_X38Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CEINV_502 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X35Y8" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ZERO_510 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ONE : X_ONE generic map( LOC => "SLICE_X35Y8" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ONE_504 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DXMUX : X_BUF generic map( LOC => "SLICE_X35Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DXMUX_503 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X35Y8" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ONE_504, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYINIT_505, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELF_506, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYINIT : X_BUF generic map( LOC => "SLICE_X35Y8", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYINIT_505 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELF : X_BUF generic map( LOC => "SLICE_X35Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELF_506 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DYMUX : X_BUF generic map( LOC => "SLICE_X35Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_XORG_508, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DYMUX_507 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_XORG : X_XOR2 generic map( LOC => "SLICE_X35Y8" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_XORG_508 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_COUTUSED : X_BUF generic map( LOC => "SLICE_X35Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYMUXG_509, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X35Y8" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ZERO_510, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELG_511, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYMUXG_509 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELG : X_BUF generic map( LOC => "SLICE_X35Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELG_511 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_SRINV : X_BUF generic map( LOC => "SLICE_X35Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_SRINV_512 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CLKINV : X_BUF generic map( LOC => "SLICE_X35Y8", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CLKINV_513 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CEINV : X_BUF generic map( LOC => "SLICE_X35Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CEINV_514 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X35Y9" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_LOGIC_ZERO_526 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DXMUX : X_BUF generic map( LOC => "SLICE_X35Y9", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORF_516, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DXMUX_515 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORF : X_XOR2 generic map( LOC => "SLICE_X35Y9" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYINIT_517, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_F, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORF_516 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X35Y9" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_LOGIC_ZERO_526, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYINIT_517, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELF_520, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X35Y9" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_LOGIC_ZERO_526, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_LOGIC_ZERO_526, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELF_520, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXF2_525 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYINIT : X_BUF generic map( LOC => "SLICE_X35Y9", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYINIT_517 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELF : X_BUF generic map( LOC => "SLICE_X35Y9", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_F, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELF_520 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DYMUX : X_BUF generic map( LOC => "SLICE_X35Y9", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORG_519, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DYMUX_518 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORG : X_XOR2 generic map( LOC => "SLICE_X35Y9" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORG_519 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_COUTUSED : X_BUF generic map( LOC => "SLICE_X35Y9", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXFAST_521, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_FASTCARRY : X_BUF generic map( LOC => "SLICE_X35Y9", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_FASTCARRY_523 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYAND : X_AND2 generic map( LOC => "SLICE_X35Y9" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELG_527, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELF_520, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYAND_522 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X35Y9" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXG2_524, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_FASTCARRY_523, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYAND_522, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXFAST_521 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X35Y9" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_LOGIC_ZERO_526, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXF2_525, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELG_527, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXG2_524 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELG : X_BUF generic map( LOC => "SLICE_X35Y9", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELG_527 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_SRINV : X_BUF generic map( LOC => "SLICE_X35Y9", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_SRINV_528 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CLKINV : X_BUF generic map( LOC => "SLICE_X35Y9", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CLKINV_529 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CEINV : X_BUF generic map( LOC => "SLICE_X35Y9", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CEINV_530 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X35Y10" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_LOGIC_ZERO_542 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DXMUX : X_BUF generic map( LOC => "SLICE_X35Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORF_532, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DXMUX_531 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORF : X_XOR2 generic map( LOC => "SLICE_X35Y10" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYINIT_533, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_F, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORF_532 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X35Y10" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_LOGIC_ZERO_542, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYINIT_533, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELF_536, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X35Y10" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_LOGIC_ZERO_542, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_LOGIC_ZERO_542, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELF_536, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXF2_541 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYINIT : X_BUF generic map( LOC => "SLICE_X35Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYINIT_533 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELF : X_BUF generic map( LOC => "SLICE_X35Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_F, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELF_536 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DYMUX : X_BUF generic map( LOC => "SLICE_X35Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORG_535, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DYMUX_534 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORG : X_XOR2 generic map( LOC => "SLICE_X35Y10" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORG_535 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_COUTUSED : X_BUF generic map( LOC => "SLICE_X35Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXFAST_537, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_FASTCARRY : X_BUF generic map( LOC => "SLICE_X35Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_FASTCARRY_539 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYAND : X_AND2 generic map( LOC => "SLICE_X35Y10" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELG_543, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELF_536, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYAND_538 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X35Y10" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXG2_540, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_FASTCARRY_539, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYAND_538, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXFAST_537 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X35Y10" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_LOGIC_ZERO_542, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXF2_541, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELG_543, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXG2_540 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELG : X_BUF generic map( LOC => "SLICE_X35Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELG_543 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_SRINV : X_BUF generic map( LOC => "SLICE_X35Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_SRINV_544 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CLKINV : X_BUF generic map( LOC => "SLICE_X35Y10", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CLKINV_545 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CEINV : X_BUF generic map( LOC => "SLICE_X35Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CEINV_546 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X35Y11" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_LOGIC_ZERO_558 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DXMUX : X_BUF generic map( LOC => "SLICE_X35Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORF_548, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DXMUX_547 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORF : X_XOR2 generic map( LOC => "SLICE_X35Y11" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYINIT_549, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_F, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORF_548 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X35Y11" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_LOGIC_ZERO_558, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYINIT_549, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELF_552, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X35Y11" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_LOGIC_ZERO_558, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_LOGIC_ZERO_558, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELF_552, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXF2_557 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYINIT : X_BUF generic map( LOC => "SLICE_X35Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYINIT_549 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELF : X_BUF generic map( LOC => "SLICE_X35Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_F, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELF_552 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DYMUX : X_BUF generic map( LOC => "SLICE_X35Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORG_551, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DYMUX_550 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORG : X_XOR2 generic map( LOC => "SLICE_X35Y11" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORG_551 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_FASTCARRY : X_BUF generic map( LOC => "SLICE_X35Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_FASTCARRY_555 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYAND : X_AND2 generic map( LOC => "SLICE_X35Y11" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELG_559, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELF_552, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYAND_554 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X35Y11" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXG2_556, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_FASTCARRY_555, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYAND_554, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXFAST_553 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X35Y11" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_LOGIC_ZERO_558, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXF2_557, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELG_559, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXG2_556 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELG : X_BUF generic map( LOC => "SLICE_X35Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_G, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELG_559 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_SRINV : X_BUF generic map( LOC => "SLICE_X35Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_SRINV_560 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CLKINV : X_BUF generic map( LOC => "SLICE_X35Y11", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CLKINV_561 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CEINV : X_BUF generic map( LOC => "SLICE_X35Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CEINV_562 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X35Y12" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_LOGIC_ZERO_565 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_DXMUX : X_BUF generic map( LOC => "SLICE_X35Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_XORF_564, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_DXMUX_563 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_XORF : X_XOR2 generic map( LOC => "SLICE_X35Y12" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CYINIT_566, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_F, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_XORF_564 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X35Y12" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_LOGIC_ZERO_565, IB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CYINIT_566, SEL => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CYSELF_567, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CYINIT : X_BUF generic map( LOC => "SLICE_X35Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXFAST_553, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CYINIT_566 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CYSELF : X_BUF generic map( LOC => "SLICE_X35Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_F, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CYSELF_567 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_DYMUX : X_BUF generic map( LOC => "SLICE_X35Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_XORG_569, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_DYMUX_568 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_XORG : X_XOR2 generic map( LOC => "SLICE_X35Y12" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q, I1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_9_rt_570, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_XORG_569 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_SRINV : X_BUF generic map( LOC => "SLICE_X35Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_SRINV_571 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CLKINV : X_BUF generic map( LOC => "SLICE_X35Y12", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CLKINV_572 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CEINV : X_BUF generic map( LOC => "SLICE_X35Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CEINV_573 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_9_rt : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X35Y12" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(9), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_9_rt_570 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X34Y4" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ZERO_581 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ONE : X_ONE generic map( LOC => "SLICE_X34Y4" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ONE_575 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DXMUX : X_BUF generic map( LOC => "SLICE_X34Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DXMUX_574 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X34Y4" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ONE_575, IB => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYINIT_576, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELF_577, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYINIT : X_BUF generic map( LOC => "SLICE_X34Y4", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYINIT_576 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELF : X_BUF generic map( LOC => "SLICE_X34Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELF_577 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DYMUX : X_BUF generic map( LOC => "SLICE_X34Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_XORG_579, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DYMUX_578 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_XORG : X_XOR2 generic map( LOC => "SLICE_X34Y4" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_XORG_579 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_COUTUSED : X_BUF generic map( LOC => "SLICE_X34Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYMUXG_580, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X34Y4" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ZERO_581, IB => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELG_582, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYMUXG_580 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELG : X_BUF generic map( LOC => "SLICE_X34Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELG_582 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_SRINV : X_BUF generic map( LOC => "SLICE_X34Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_SRINV_583 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CLKINV : X_BUF generic map( LOC => "SLICE_X34Y4", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CLKINV_584 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CEINV : X_BUF generic map( LOC => "SLICE_X34Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CEINV_585 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X34Y5" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_LOGIC_ZERO_597 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DXMUX : X_BUF generic map( LOC => "SLICE_X34Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORF_587, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DXMUX_586 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORF : X_XOR2 generic map( LOC => "SLICE_X34Y5" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYINIT_588, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORF_587 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X34Y5" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_LOGIC_ZERO_597, IB => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYINIT_588, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELF_591, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X34Y5" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_LOGIC_ZERO_597, IB => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_LOGIC_ZERO_597, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELF_591, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXF2_596 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYINIT : X_BUF generic map( LOC => "SLICE_X34Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYINIT_588 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELF : X_BUF generic map( LOC => "SLICE_X34Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELF_591 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DYMUX : X_BUF generic map( LOC => "SLICE_X34Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORG_590, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DYMUX_589 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORG : X_XOR2 generic map( LOC => "SLICE_X34Y5" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORG_590 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_COUTUSED : X_BUF generic map( LOC => "SLICE_X34Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXFAST_592, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_FASTCARRY : X_BUF generic map( LOC => "SLICE_X34Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_FASTCARRY_594 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYAND : X_AND2 generic map( LOC => "SLICE_X34Y5" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELG_598, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELF_591, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYAND_593 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X34Y5" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXG2_595, IB => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_FASTCARRY_594, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYAND_593, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXFAST_592 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X34Y5" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_LOGIC_ZERO_597, IB => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXF2_596, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELG_598, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXG2_595 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELG : X_BUF generic map( LOC => "SLICE_X34Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELG_598 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_SRINV : X_BUF generic map( LOC => "SLICE_X34Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_SRINV_599 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CLKINV : X_BUF generic map( LOC => "SLICE_X34Y5", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CLKINV_600 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CEINV : X_BUF generic map( LOC => "SLICE_X34Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CEINV_601 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X34Y6" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_LOGIC_ZERO_613 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DXMUX : X_BUF generic map( LOC => "SLICE_X34Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORF_603, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DXMUX_602 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORF : X_XOR2 generic map( LOC => "SLICE_X34Y6" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYINIT_604, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORF_603 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X34Y6" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_LOGIC_ZERO_613, IB => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYINIT_604, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELF_607, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X34Y6" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_LOGIC_ZERO_613, IB => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_LOGIC_ZERO_613, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELF_607, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXF2_612 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYINIT : X_BUF generic map( LOC => "SLICE_X34Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYINIT_604 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELF : X_BUF generic map( LOC => "SLICE_X34Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELF_607 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DYMUX : X_BUF generic map( LOC => "SLICE_X34Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORG_606, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DYMUX_605 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORG : X_XOR2 generic map( LOC => "SLICE_X34Y6" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORG_606 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_COUTUSED : X_BUF generic map( LOC => "SLICE_X34Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXFAST_608, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_FASTCARRY : X_BUF generic map( LOC => "SLICE_X34Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_FASTCARRY_610 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYAND : X_AND2 generic map( LOC => "SLICE_X34Y6" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELG_614, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELF_607, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYAND_609 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X34Y6" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXG2_611, IB => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_FASTCARRY_610, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYAND_609, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXFAST_608 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X34Y6" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_LOGIC_ZERO_613, IB => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXF2_612, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELG_614, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXG2_611 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELG : X_BUF generic map( LOC => "SLICE_X34Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELG_614 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_SRINV : X_BUF generic map( LOC => "SLICE_X34Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_SRINV_615 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CLKINV : X_BUF generic map( LOC => "SLICE_X34Y6", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CLKINV_616 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CEINV : X_BUF generic map( LOC => "SLICE_X34Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CEINV_617 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X34Y7" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_LOGIC_ZERO_629 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DXMUX : X_BUF generic map( LOC => "SLICE_X34Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORF_619, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DXMUX_618 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORF : X_XOR2 generic map( LOC => "SLICE_X34Y7" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYINIT_620, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORF_619 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X34Y7" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_LOGIC_ZERO_629, IB => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYINIT_620, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELF_623, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X34Y7" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_LOGIC_ZERO_629, IB => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_LOGIC_ZERO_629, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELF_623, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXF2_628 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYINIT : X_BUF generic map( LOC => "SLICE_X34Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYINIT_620 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELF : X_BUF generic map( LOC => "SLICE_X34Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELF_623 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DYMUX : X_BUF generic map( LOC => "SLICE_X34Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORG_622, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DYMUX_621 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORG : X_XOR2 generic map( LOC => "SLICE_X34Y7" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORG_622 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_FASTCARRY : X_BUF generic map( LOC => "SLICE_X34Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_FASTCARRY_626 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYAND : X_AND2 generic map( LOC => "SLICE_X34Y7" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELG_630, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELF_623, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYAND_625 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X34Y7" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXG2_627, IB => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_FASTCARRY_626, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYAND_625, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXFAST_624 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X34Y7" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_LOGIC_ZERO_629, IB => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXF2_628, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELG_630, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXG2_627 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELG : X_BUF generic map( LOC => "SLICE_X34Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_G, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELG_630 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_SRINV : X_BUF generic map( LOC => "SLICE_X34Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_SRINV_631 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CLKINV : X_BUF generic map( LOC => "SLICE_X34Y7", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CLKINV_632 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CEINV : X_BUF generic map( LOC => "SLICE_X34Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CEINV_633 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X34Y8" ) port map ( O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_LOGIC_ZERO_636 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_DXMUX : X_BUF generic map( LOC => "SLICE_X34Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_XORF_635, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_DXMUX_634 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_XORF : X_XOR2 generic map( LOC => "SLICE_X34Y8" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CYINIT_637, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_XORF_635 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X34Y8" ) port map ( IA => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_LOGIC_ZERO_636, IB => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CYINIT_637, SEL => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CYSELF_638, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CYINIT : X_BUF generic map( LOC => "SLICE_X34Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXFAST_624, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CYINIT_637 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CYSELF : X_BUF generic map( LOC => "SLICE_X34Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_F, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CYSELF_638 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_DYMUX : X_BUF generic map( LOC => "SLICE_X34Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_XORG_640, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_DYMUX_639 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_XORG : X_XOR2 generic map( LOC => "SLICE_X34Y8" ) port map ( I0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q, I1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_9_rt_641, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_XORG_640 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_SRINV : X_BUF generic map( LOC => "SLICE_X34Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_SRINV_642 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CLKINV : X_BUF generic map( LOC => "SLICE_X34Y8", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CLKINV_643 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CEINV : X_BUF generic map( LOC => "SLICE_X34Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CEINV_644 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_9_rt : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X34Y8" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(9), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_9_rt_641 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X10Y2" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ZERO_652 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ONE : X_ONE generic map( LOC => "SLICE_X10Y2" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ONE_646 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DXMUX : X_BUF generic map( LOC => "SLICE_X10Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DXMUX_645 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X10Y2" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ONE_646, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYINIT_647, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELF_648, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYINIT : X_BUF generic map( LOC => "SLICE_X10Y2", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYINIT_647 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELF : X_BUF generic map( LOC => "SLICE_X10Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELF_648 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DYMUX : X_BUF generic map( LOC => "SLICE_X10Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_XORG_650, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DYMUX_649 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_XORG : X_XOR2 generic map( LOC => "SLICE_X10Y2" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_XORG_650 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_COUTUSED : X_BUF generic map( LOC => "SLICE_X10Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYMUXG_651, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X10Y2" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_LOGIC_ZERO_652, IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELG_653, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYMUXG_651 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELG : X_BUF generic map( LOC => "SLICE_X10Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CYSELG_653 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_SRINV : X_BUF generic map( LOC => "SLICE_X10Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_SRINV_654 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CLKINV : X_BUF generic map( LOC => "SLICE_X10Y2", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CLKINV_655 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CEINV : X_INV generic map( LOC => "SLICE_X10Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X10Y3" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_LOGIC_ZERO_667 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DXMUX : X_BUF generic map( LOC => "SLICE_X10Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORF_657, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DXMUX_656 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORF : X_XOR2 generic map( LOC => "SLICE_X10Y3" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYINIT_658, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_F, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORF_657 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X10Y3" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_LOGIC_ZERO_667, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYINIT_658, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELF_661, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X10Y3" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_LOGIC_ZERO_667, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_LOGIC_ZERO_667, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELF_661, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXF2_666 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYINIT : X_BUF generic map( LOC => "SLICE_X10Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYINIT_658 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELF : X_BUF generic map( LOC => "SLICE_X10Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_F, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELF_661 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DYMUX : X_BUF generic map( LOC => "SLICE_X10Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORG_660, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DYMUX_659 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORG : X_XOR2 generic map( LOC => "SLICE_X10Y3" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_XORG_660 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_COUTUSED : X_BUF generic map( LOC => "SLICE_X10Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXFAST_662, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_FASTCARRY : X_BUF generic map( LOC => "SLICE_X10Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_FASTCARRY_664 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYAND : X_AND2 generic map( LOC => "SLICE_X10Y3" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELG_668, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELF_661, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYAND_663 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X10Y3" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXG2_665, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_FASTCARRY_664, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYAND_663, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXFAST_662 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X10Y3" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_LOGIC_ZERO_667, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXF2_666, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELG_668, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYMUXG2_665 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELG : X_BUF generic map( LOC => "SLICE_X10Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CYSELG_668 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_SRINV : X_BUF generic map( LOC => "SLICE_X10Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_SRINV_669 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CLKINV : X_BUF generic map( LOC => "SLICE_X10Y3", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CLKINV_670 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CEINV : X_INV generic map( LOC => "SLICE_X10Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X10Y4" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_LOGIC_ZERO_682 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DXMUX : X_BUF generic map( LOC => "SLICE_X10Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORF_672, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DXMUX_671 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORF : X_XOR2 generic map( LOC => "SLICE_X10Y4" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYINIT_673, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_F, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORF_672 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X10Y4" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_LOGIC_ZERO_682, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYINIT_673, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELF_676, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X10Y4" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_LOGIC_ZERO_682, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_LOGIC_ZERO_682, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELF_676, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXF2_681 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYINIT : X_BUF generic map( LOC => "SLICE_X10Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYINIT_673 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELF : X_BUF generic map( LOC => "SLICE_X10Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_F, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELF_676 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DYMUX : X_BUF generic map( LOC => "SLICE_X10Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORG_675, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DYMUX_674 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORG : X_XOR2 generic map( LOC => "SLICE_X10Y4" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_XORG_675 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_COUTUSED : X_BUF generic map( LOC => "SLICE_X10Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXFAST_677, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_FASTCARRY : X_BUF generic map( LOC => "SLICE_X10Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_FASTCARRY_679 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYAND : X_AND2 generic map( LOC => "SLICE_X10Y4" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELG_683, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELF_676, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYAND_678 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X10Y4" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXG2_680, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_FASTCARRY_679, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYAND_678, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXFAST_677 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X10Y4" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_LOGIC_ZERO_682, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXF2_681, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELG_683, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYMUXG2_680 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELG : X_BUF generic map( LOC => "SLICE_X10Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CYSELG_683 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_SRINV : X_BUF generic map( LOC => "SLICE_X10Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_SRINV_684 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CLKINV : X_BUF generic map( LOC => "SLICE_X10Y4", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CLKINV_685 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CEINV : X_INV generic map( LOC => "SLICE_X10Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X10Y5" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_LOGIC_ZERO_697 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DXMUX : X_BUF generic map( LOC => "SLICE_X10Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORF_687, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DXMUX_686 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORF : X_XOR2 generic map( LOC => "SLICE_X10Y5" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYINIT_688, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_F, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORF_687 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X10Y5" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_LOGIC_ZERO_697, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYINIT_688, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELF_691, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X10Y5" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_LOGIC_ZERO_697, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_LOGIC_ZERO_697, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELF_691, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXF2_696 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYINIT : X_BUF generic map( LOC => "SLICE_X10Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYINIT_688 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELF : X_BUF generic map( LOC => "SLICE_X10Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_F, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELF_691 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DYMUX : X_BUF generic map( LOC => "SLICE_X10Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORG_690, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DYMUX_689 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORG : X_XOR2 generic map( LOC => "SLICE_X10Y5" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_XORG_690 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_FASTCARRY : X_BUF generic map( LOC => "SLICE_X10Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_FASTCARRY_694 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYAND : X_AND2 generic map( LOC => "SLICE_X10Y5" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELG_698, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELF_691, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYAND_693 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X10Y5" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXG2_695, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_FASTCARRY_694, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYAND_693, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXFAST_692 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X10Y5" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_LOGIC_ZERO_697, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXF2_696, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELG_698, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXG2_695 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELG : X_BUF generic map( LOC => "SLICE_X10Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYSELG_698 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_SRINV : X_BUF generic map( LOC => "SLICE_X10Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_SRINV_699 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CLKINV : X_BUF generic map( LOC => "SLICE_X10Y5", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CLKINV_700 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CEINV : X_INV generic map( LOC => "SLICE_X10Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X10Y6" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_LOGIC_ZERO_703 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_DXMUX : X_BUF generic map( LOC => "SLICE_X10Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_XORF_702, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_DXMUX_701 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_XORF : X_XOR2 generic map( LOC => "SLICE_X10Y6" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CYINIT_704, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_F, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_XORF_702 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X10Y6" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_LOGIC_ZERO_703, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CYINIT_704, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CYSELF_705, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CYINIT : X_BUF generic map( LOC => "SLICE_X10Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CYMUXFAST_692, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CYINIT_704 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CYSELF : X_BUF generic map( LOC => "SLICE_X10Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_F, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CYSELF_705 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_DYMUX : X_BUF generic map( LOC => "SLICE_X10Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_XORG_707, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_DYMUX_706 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_XORG : X_XOR2 generic map( LOC => "SLICE_X10Y6" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_9_rt_708, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_XORG_707 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_SRINV : X_BUF generic map( LOC => "SLICE_X10Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_SRINV_709 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CLKINV : X_BUF generic map( LOC => "SLICE_X10Y6", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CLKINV_710 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CEINV : X_INV generic map( LOC => "SLICE_X10Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_9_rt : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X10Y6" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(9), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_9_rt_708 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X24Y14" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ZERO_718 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ONE : X_ONE generic map( LOC => "SLICE_X24Y14" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ONE_712 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DXMUX_711 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X24Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ONE_712, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYINIT_713, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELF_714, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYINIT : X_BUF generic map( LOC => "SLICE_X24Y14", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYINIT_713 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELF : X_BUF generic map( LOC => "SLICE_X24Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELF_714 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DYMUX : X_BUF generic map( LOC => "SLICE_X24Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_XORG_716, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DYMUX_715 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_XORG : X_XOR2 generic map( LOC => "SLICE_X24Y14" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_XORG_716 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_COUTUSED : X_BUF generic map( LOC => "SLICE_X24Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYMUXG_717, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X24Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_LOGIC_ZERO_718, IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELG_719, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYMUXG_717 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELG : X_BUF generic map( LOC => "SLICE_X24Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CYSELG_719 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_SRINV : X_BUF generic map( LOC => "SLICE_X24Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_SRINV_720 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CLKINV : X_BUF generic map( LOC => "SLICE_X24Y14", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CLKINV_721 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CEINV : X_INV generic map( LOC => "SLICE_X24Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X24Y15" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_LOGIC_ZERO_733 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORF_723, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DXMUX_722 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORF : X_XOR2 generic map( LOC => "SLICE_X24Y15" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYINIT_724, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORF_723 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X24Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_LOGIC_ZERO_733, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYINIT_724, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELF_727, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X24Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_LOGIC_ZERO_733, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_LOGIC_ZERO_733, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELF_727, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXF2_732 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYINIT : X_BUF generic map( LOC => "SLICE_X24Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYINIT_724 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELF : X_BUF generic map( LOC => "SLICE_X24Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELF_727 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DYMUX : X_BUF generic map( LOC => "SLICE_X24Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORG_726, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DYMUX_725 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORG : X_XOR2 generic map( LOC => "SLICE_X24Y15" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_XORG_726 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_COUTUSED : X_BUF generic map( LOC => "SLICE_X24Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXFAST_728, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_FASTCARRY : X_BUF generic map( LOC => "SLICE_X24Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_FASTCARRY_730 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYAND : X_AND2 generic map( LOC => "SLICE_X24Y15" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELG_734, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELF_727, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYAND_729 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X24Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXG2_731, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_FASTCARRY_730, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYAND_729, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXFAST_728 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X24Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_LOGIC_ZERO_733, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXF2_732, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELG_734, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYMUXG2_731 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELG : X_BUF generic map( LOC => "SLICE_X24Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CYSELG_734 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_SRINV : X_BUF generic map( LOC => "SLICE_X24Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_SRINV_735 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CLKINV : X_BUF generic map( LOC => "SLICE_X24Y15", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CLKINV_736 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CEINV : X_INV generic map( LOC => "SLICE_X24Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X24Y16" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_LOGIC_ZERO_748 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORF_738, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DXMUX_737 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORF : X_XOR2 generic map( LOC => "SLICE_X24Y16" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYINIT_739, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORF_738 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X24Y16" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_LOGIC_ZERO_748, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYINIT_739, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELF_742, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X24Y16" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_LOGIC_ZERO_748, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_LOGIC_ZERO_748, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELF_742, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXF2_747 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYINIT : X_BUF generic map( LOC => "SLICE_X24Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYINIT_739 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELF : X_BUF generic map( LOC => "SLICE_X24Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELF_742 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DYMUX : X_BUF generic map( LOC => "SLICE_X24Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORG_741, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DYMUX_740 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORG : X_XOR2 generic map( LOC => "SLICE_X24Y16" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_XORG_741 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_COUTUSED : X_BUF generic map( LOC => "SLICE_X24Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXFAST_743, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_FASTCARRY : X_BUF generic map( LOC => "SLICE_X24Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_FASTCARRY_745 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYAND : X_AND2 generic map( LOC => "SLICE_X24Y16" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELG_749, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELF_742, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYAND_744 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X24Y16" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXG2_746, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_FASTCARRY_745, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYAND_744, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXFAST_743 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X24Y16" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_LOGIC_ZERO_748, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXF2_747, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELG_749, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYMUXG2_746 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELG : X_BUF generic map( LOC => "SLICE_X24Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CYSELG_749 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_SRINV : X_BUF generic map( LOC => "SLICE_X24Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_SRINV_750 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CLKINV : X_BUF generic map( LOC => "SLICE_X24Y16", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CLKINV_751 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CEINV : X_INV generic map( LOC => "SLICE_X24Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X24Y17" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_LOGIC_ZERO_763 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y17", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORF_753, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DXMUX_752 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORF : X_XOR2 generic map( LOC => "SLICE_X24Y17" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYINIT_754, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORF_753 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X24Y17" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_LOGIC_ZERO_763, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYINIT_754, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELF_757, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X24Y17" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_LOGIC_ZERO_763, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_LOGIC_ZERO_763, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELF_757, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXF2_762 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYINIT : X_BUF generic map( LOC => "SLICE_X24Y17", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYINIT_754 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELF : X_BUF generic map( LOC => "SLICE_X24Y17", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELF_757 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DYMUX : X_BUF generic map( LOC => "SLICE_X24Y17", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORG_756, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DYMUX_755 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORG : X_XOR2 generic map( LOC => "SLICE_X24Y17" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_XORG_756 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_FASTCARRY : X_BUF generic map( LOC => "SLICE_X24Y17", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_FASTCARRY_760 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYAND : X_AND2 generic map( LOC => "SLICE_X24Y17" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELG_764, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELF_757, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYAND_759 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X24Y17" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXG2_761, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_FASTCARRY_760, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYAND_759, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXFAST_758 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X24Y17" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_LOGIC_ZERO_763, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXF2_762, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELG_764, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXG2_761 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELG : X_BUF generic map( LOC => "SLICE_X24Y17", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYSELG_764 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_SRINV : X_BUF generic map( LOC => "SLICE_X24Y17", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_SRINV_765 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CLKINV : X_BUF generic map( LOC => "SLICE_X24Y17", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CLKINV_766 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CEINV : X_INV generic map( LOC => "SLICE_X24Y17", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X24Y18" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_LOGIC_ZERO_769 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y18", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_XORF_768, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_DXMUX_767 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_XORF : X_XOR2 generic map( LOC => "SLICE_X24Y18" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CYINIT_770, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_XORF_768 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X24Y18" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_LOGIC_ZERO_769, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CYINIT_770, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CYSELF_771, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CYINIT : X_BUF generic map( LOC => "SLICE_X24Y18", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CYMUXFAST_758, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CYINIT_770 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CYSELF : X_BUF generic map( LOC => "SLICE_X24Y18", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CYSELF_771 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_DYMUX : X_BUF generic map( LOC => "SLICE_X24Y18", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_XORG_773, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_DYMUX_772 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_XORG : X_XOR2 generic map( LOC => "SLICE_X24Y18" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_9_rt_774, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_XORG_773 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_SRINV : X_BUF generic map( LOC => "SLICE_X24Y18", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_SRINV_775 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CLKINV : X_BUF generic map( LOC => "SLICE_X24Y18", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CLKINV_776 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CEINV : X_INV generic map( LOC => "SLICE_X24Y18", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_9_rt : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X24Y18" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(9), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_9_rt_774 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X26Y12" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ZERO_784 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ONE : X_ONE generic map( LOC => "SLICE_X26Y12" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ONE_778 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DXMUX : X_BUF generic map( LOC => "SLICE_X26Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DXMUX_777 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X26Y12" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ONE_778, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYINIT_779, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELF_780, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYINIT : X_BUF generic map( LOC => "SLICE_X26Y12", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYINIT_779 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELF : X_BUF generic map( LOC => "SLICE_X26Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELF_780 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DYMUX : X_BUF generic map( LOC => "SLICE_X26Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_XORG_782, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DYMUX_781 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_XORG : X_XOR2 generic map( LOC => "SLICE_X26Y12" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_XORG_782 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_COUTUSED : X_BUF generic map( LOC => "SLICE_X26Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYMUXG_783, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X26Y12" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_LOGIC_ZERO_784, IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELG_785, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYMUXG_783 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELG : X_BUF generic map( LOC => "SLICE_X26Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CYSELG_785 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_SRINV : X_BUF generic map( LOC => "SLICE_X26Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_SRINV_786 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CLKINV : X_BUF generic map( LOC => "SLICE_X26Y12", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CLKINV_787 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CEINV : X_INV generic map( LOC => "SLICE_X26Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X26Y13" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_LOGIC_ZERO_799 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DXMUX : X_BUF generic map( LOC => "SLICE_X26Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORF_789, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DXMUX_788 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORF : X_XOR2 generic map( LOC => "SLICE_X26Y13" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYINIT_790, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORF_789 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X26Y13" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_LOGIC_ZERO_799, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYINIT_790, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELF_793, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X26Y13" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_LOGIC_ZERO_799, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_LOGIC_ZERO_799, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELF_793, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXF2_798 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYINIT : X_BUF generic map( LOC => "SLICE_X26Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYINIT_790 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELF : X_BUF generic map( LOC => "SLICE_X26Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELF_793 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DYMUX : X_BUF generic map( LOC => "SLICE_X26Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORG_792, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DYMUX_791 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORG : X_XOR2 generic map( LOC => "SLICE_X26Y13" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_XORG_792 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_COUTUSED : X_BUF generic map( LOC => "SLICE_X26Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXFAST_794, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_FASTCARRY : X_BUF generic map( LOC => "SLICE_X26Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_FASTCARRY_796 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYAND : X_AND2 generic map( LOC => "SLICE_X26Y13" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELG_800, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELF_793, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYAND_795 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X26Y13" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXG2_797, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_FASTCARRY_796, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYAND_795, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXFAST_794 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X26Y13" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_LOGIC_ZERO_799, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXF2_798, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELG_800, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYMUXG2_797 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELG : X_BUF generic map( LOC => "SLICE_X26Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CYSELG_800 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_SRINV : X_BUF generic map( LOC => "SLICE_X26Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_SRINV_801 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CLKINV : X_BUF generic map( LOC => "SLICE_X26Y13", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CLKINV_802 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CEINV : X_INV generic map( LOC => "SLICE_X26Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X26Y14" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_LOGIC_ZERO_814 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DXMUX : X_BUF generic map( LOC => "SLICE_X26Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORF_804, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DXMUX_803 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORF : X_XOR2 generic map( LOC => "SLICE_X26Y14" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYINIT_805, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORF_804 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X26Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_LOGIC_ZERO_814, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYINIT_805, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELF_808, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X26Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_LOGIC_ZERO_814, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_LOGIC_ZERO_814, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELF_808, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXF2_813 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYINIT : X_BUF generic map( LOC => "SLICE_X26Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYINIT_805 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELF : X_BUF generic map( LOC => "SLICE_X26Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELF_808 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DYMUX : X_BUF generic map( LOC => "SLICE_X26Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORG_807, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DYMUX_806 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORG : X_XOR2 generic map( LOC => "SLICE_X26Y14" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_XORG_807 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_COUTUSED : X_BUF generic map( LOC => "SLICE_X26Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXFAST_809, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_FASTCARRY : X_BUF generic map( LOC => "SLICE_X26Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_FASTCARRY_811 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYAND : X_AND2 generic map( LOC => "SLICE_X26Y14" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELG_815, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELF_808, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYAND_810 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X26Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXG2_812, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_FASTCARRY_811, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYAND_810, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXFAST_809 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X26Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_LOGIC_ZERO_814, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXF2_813, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELG_815, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYMUXG2_812 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELG : X_BUF generic map( LOC => "SLICE_X26Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CYSELG_815 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_SRINV : X_BUF generic map( LOC => "SLICE_X26Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_SRINV_816 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CLKINV : X_BUF generic map( LOC => "SLICE_X26Y14", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CLKINV_817 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CEINV : X_INV generic map( LOC => "SLICE_X26Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X26Y15" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_LOGIC_ZERO_829 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DXMUX : X_BUF generic map( LOC => "SLICE_X26Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORF_819, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DXMUX_818 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORF : X_XOR2 generic map( LOC => "SLICE_X26Y15" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYINIT_820, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORF_819 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X26Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_LOGIC_ZERO_829, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYINIT_820, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELF_823, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X26Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_LOGIC_ZERO_829, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_LOGIC_ZERO_829, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELF_823, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXF2_828 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYINIT : X_BUF generic map( LOC => "SLICE_X26Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYINIT_820 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELF : X_BUF generic map( LOC => "SLICE_X26Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELF_823 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DYMUX : X_BUF generic map( LOC => "SLICE_X26Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORG_822, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DYMUX_821 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORG : X_XOR2 generic map( LOC => "SLICE_X26Y15" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_XORG_822 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_FASTCARRY : X_BUF generic map( LOC => "SLICE_X26Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_FASTCARRY_826 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYAND : X_AND2 generic map( LOC => "SLICE_X26Y15" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELG_830, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELF_823, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYAND_825 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X26Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXG2_827, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_FASTCARRY_826, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYAND_825, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXFAST_824 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X26Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_LOGIC_ZERO_829, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXF2_828, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELG_830, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXG2_827 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELG : X_BUF generic map( LOC => "SLICE_X26Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_G, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYSELG_830 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_SRINV : X_BUF generic map( LOC => "SLICE_X26Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_SRINV_831 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CLKINV : X_BUF generic map( LOC => "SLICE_X26Y15", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CLKINV_832 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CEINV : X_INV generic map( LOC => "SLICE_X26Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X26Y16" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_LOGIC_ZERO_835 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_DXMUX : X_BUF generic map( LOC => "SLICE_X26Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_XORF_834, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_DXMUX_833 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_XORF : X_XOR2 generic map( LOC => "SLICE_X26Y16" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CYINIT_836, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_XORF_834 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X26Y16" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_LOGIC_ZERO_835, IB => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CYINIT_836, SEL => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CYSELF_837, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CYINIT : X_BUF generic map( LOC => "SLICE_X26Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CYMUXFAST_824, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CYINIT_836 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CYSELF : X_BUF generic map( LOC => "SLICE_X26Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_F, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CYSELF_837 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_DYMUX : X_BUF generic map( LOC => "SLICE_X26Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_XORG_839, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_DYMUX_838 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_XORG : X_XOR2 generic map( LOC => "SLICE_X26Y16" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q, I1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_9_rt_840, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_XORG_839 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_SRINV : X_BUF generic map( LOC => "SLICE_X26Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_SRINV_841 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CLKINV : X_BUF generic map( LOC => "SLICE_X26Y16", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CLKINV_842 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CEINV : X_INV generic map( LOC => "SLICE_X26Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_9_rt : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X26Y16" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(9), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_9_rt_840 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X31Y12" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ZERO_850 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ONE : X_ONE generic map( LOC => "SLICE_X31Y12" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ONE_844 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DXMUX : X_BUF generic map( LOC => "SLICE_X31Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DXMUX_843 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X31Y12" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ONE_844 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYINIT_845 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELF_846 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYINIT : X_BUF generic map( LOC => "SLICE_X31Y12", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYINIT_845 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELF : X_BUF generic map( LOC => "SLICE_X31Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELF_846 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DYMUX : X_BUF generic map( LOC => "SLICE_X31Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_XORG_848 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DYMUX_847 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_XORG : X_XOR2 generic map( LOC => "SLICE_X31Y12" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_XORG_848 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_COUTUSED : X_BUF generic map( LOC => "SLICE_X31Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYMUXG_849 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X31Y12" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ZERO_850 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_0_Q , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELG_851 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYMUXG_849 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELG : X_BUF generic map( LOC => "SLICE_X31Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELG_851 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_SRINV : X_BUF generic map( LOC => "SLICE_X31Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_SRINV_852 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CLKINV : X_BUF generic map( LOC => "SLICE_X31Y12", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CLKINV_853 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CEINV : X_INV generic map( LOC => "SLICE_X31Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X31Y13" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_865 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DXMUX : X_BUF generic map( LOC => "SLICE_X31Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORF_855 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DXMUX_854 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORF : X_XOR2 generic map( LOC => "SLICE_X31Y13" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYINIT_856 , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_F, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORF_855 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X31Y13" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_865 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYINIT_856 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF_859 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X31Y13" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_865 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_865 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF_859 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXF2_864 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYINIT : X_BUF generic map( LOC => "SLICE_X31Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYINIT_856 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF : X_BUF generic map( LOC => "SLICE_X31Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_F, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF_859 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DYMUX : X_BUF generic map( LOC => "SLICE_X31Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORG_858 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DYMUX_857 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORG : X_XOR2 generic map( LOC => "SLICE_X31Y13" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_2_Q , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORG_858 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_COUTUSED : X_BUF generic map( LOC => "SLICE_X31Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXFAST_860 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_FASTCARRY : X_BUF generic map( LOC => "SLICE_X31Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_1_Q , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_FASTCARRY_862 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYAND : X_AND2 generic map( LOC => "SLICE_X31Y13" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELG_866 , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF_859 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYAND_861 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X31Y13" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXG2_863 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_FASTCARRY_862 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYAND_861 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXFAST_860 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X31Y13" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_865 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXF2_864 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELG_866 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXG2_863 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELG : X_BUF generic map( LOC => "SLICE_X31Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELG_866 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_SRINV : X_BUF generic map( LOC => "SLICE_X31Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_SRINV_867 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CLKINV : X_BUF generic map( LOC => "SLICE_X31Y13", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CLKINV_868 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CEINV : X_INV generic map( LOC => "SLICE_X31Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X31Y14" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_880 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DXMUX : X_BUF generic map( LOC => "SLICE_X31Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORF_870 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DXMUX_869 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORF : X_XOR2 generic map( LOC => "SLICE_X31Y14" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYINIT_871 , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_F, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORF_870 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X31Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_880 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYINIT_871 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF_874 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X31Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_880 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_880 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF_874 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXF2_879 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYINIT : X_BUF generic map( LOC => "SLICE_X31Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYINIT_871 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF : X_BUF generic map( LOC => "SLICE_X31Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_F, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF_874 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DYMUX : X_BUF generic map( LOC => "SLICE_X31Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORG_873 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DYMUX_872 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORG : X_XOR2 generic map( LOC => "SLICE_X31Y14" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_4_Q , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORG_873 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_COUTUSED : X_BUF generic map( LOC => "SLICE_X31Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXFAST_875 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_FASTCARRY : X_BUF generic map( LOC => "SLICE_X31Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_3_Q , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_FASTCARRY_877 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYAND : X_AND2 generic map( LOC => "SLICE_X31Y14" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELG_881 , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF_874 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYAND_876 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X31Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXG2_878 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_FASTCARRY_877 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYAND_876 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXFAST_875 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X31Y14" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_880 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXF2_879 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELG_881 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXG2_878 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELG : X_BUF generic map( LOC => "SLICE_X31Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELG_881 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_SRINV : X_BUF generic map( LOC => "SLICE_X31Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_SRINV_882 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CLKINV : X_BUF generic map( LOC => "SLICE_X31Y14", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CLKINV_883 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CEINV : X_INV generic map( LOC => "SLICE_X31Y14", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X31Y15" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_895 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DXMUX : X_BUF generic map( LOC => "SLICE_X31Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORF_885 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DXMUX_884 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORF : X_XOR2 generic map( LOC => "SLICE_X31Y15" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYINIT_886 , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_F, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORF_885 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X31Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_895 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYINIT_886 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF_889 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X31Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_895 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_895 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF_889 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXF2_894 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYINIT : X_BUF generic map( LOC => "SLICE_X31Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYINIT_886 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF : X_BUF generic map( LOC => "SLICE_X31Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_F, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF_889 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DYMUX : X_BUF generic map( LOC => "SLICE_X31Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORG_888 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DYMUX_887 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORG : X_XOR2 generic map( LOC => "SLICE_X31Y15" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_6_Q , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORG_888 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_FASTCARRY : X_BUF generic map( LOC => "SLICE_X31Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_5_Q , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_FASTCARRY_892 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYAND : X_AND2 generic map( LOC => "SLICE_X31Y15" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELG_896 , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF_889 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYAND_891 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X31Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXG2_893 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_FASTCARRY_892 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYAND_891 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXFAST_890 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X31Y15" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_895 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXF2_894 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELG_896 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXG2_893 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELG : X_BUF generic map( LOC => "SLICE_X31Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELG_896 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_SRINV : X_BUF generic map( LOC => "SLICE_X31Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_SRINV_897 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CLKINV : X_BUF generic map( LOC => "SLICE_X31Y15", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CLKINV_898 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CEINV : X_INV generic map( LOC => "SLICE_X31Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X31Y16" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_LOGIC_ZERO_901 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DXMUX : X_BUF generic map( LOC => "SLICE_X31Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORF_900 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DXMUX_899 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORF : X_XOR2 generic map( LOC => "SLICE_X31Y16" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYINIT_902 , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_F, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORF_900 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X31Y16" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_LOGIC_ZERO_901 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYINIT_902 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYSELF_903 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYINIT : X_BUF generic map( LOC => "SLICE_X31Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXFAST_890 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYINIT_902 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYSELF : X_BUF generic map( LOC => "SLICE_X31Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_F, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYSELF_903 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DYMUX : X_BUF generic map( LOC => "SLICE_X31Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORG_905 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DYMUX_904 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORG : X_XOR2 generic map( LOC => "SLICE_X31Y16" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy_8_Q , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9_rt_906 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORG_905 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_SRINV : X_BUF generic map( LOC => "SLICE_X31Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_SRINV_907 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CLKINV : X_BUF generic map( LOC => "SLICE_X31Y16", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CLKINV_908 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CEINV : X_INV generic map( LOC => "SLICE_X31Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9_rt : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X31Y16" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(9), O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9_rt_906 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X24Y6" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ZERO_916 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ONE : X_ONE generic map( LOC => "SLICE_X24Y6" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ONE_910 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DXMUX_909 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X24Y6" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ONE_910, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYINIT_911, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELF_912, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0) ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYINIT : X_BUF generic map( LOC => "SLICE_X24Y6", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYINIT_911 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELF : X_BUF generic map( LOC => "SLICE_X24Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELF_912 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DYMUX : X_BUF generic map( LOC => "SLICE_X24Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_XORG_914, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DYMUX_913 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_XORG : X_XOR2 generic map( LOC => "SLICE_X24Y6" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0), I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_XORG_914 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_COUTUSED : X_BUF generic map( LOC => "SLICE_X24Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYMUXG_915, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1) ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X24Y6" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_LOGIC_ZERO_916, IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0), SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELG_917, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYMUXG_915 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELG : X_BUF generic map( LOC => "SLICE_X24Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CYSELG_917 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_SRINV : X_BUF generic map( LOC => "SLICE_X24Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_SRINV_918 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CLKINV : X_BUF generic map( LOC => "SLICE_X24Y6", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CLKINV_919 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CEINV : X_BUF generic map( LOC => "SLICE_X24Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CEINV_920 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X24Y7" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_LOGIC_ZERO_932 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORF_922, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DXMUX_921 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORF : X_XOR2 generic map( LOC => "SLICE_X24Y7" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYINIT_923, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_F, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORF_922 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X24Y7" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_LOGIC_ZERO_932, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYINIT_923, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELF_926, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(2) ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X24Y7" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_LOGIC_ZERO_932, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_LOGIC_ZERO_932, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELF_926, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXF2_931 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYINIT : X_BUF generic map( LOC => "SLICE_X24Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYINIT_923 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELF : X_BUF generic map( LOC => "SLICE_X24Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_F, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELF_926 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DYMUX : X_BUF generic map( LOC => "SLICE_X24Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORG_925, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DYMUX_924 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORG : X_XOR2 generic map( LOC => "SLICE_X24Y7" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(2), I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_XORG_925 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_COUTUSED : X_BUF generic map( LOC => "SLICE_X24Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXFAST_927, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3) ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_FASTCARRY : X_BUF generic map( LOC => "SLICE_X24Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_FASTCARRY_929 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYAND : X_AND2 generic map( LOC => "SLICE_X24Y7" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELG_933, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELF_926, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYAND_928 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X24Y7" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXG2_930, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_FASTCARRY_929, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYAND_928, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXFAST_927 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X24Y7" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_LOGIC_ZERO_932, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXF2_931, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELG_933, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYMUXG2_930 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELG : X_BUF generic map( LOC => "SLICE_X24Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CYSELG_933 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_SRINV : X_BUF generic map( LOC => "SLICE_X24Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_SRINV_934 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CLKINV : X_BUF generic map( LOC => "SLICE_X24Y7", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CLKINV_935 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CEINV : X_BUF generic map( LOC => "SLICE_X24Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CEINV_936 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X24Y8" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_LOGIC_ZERO_948 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORF_938, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DXMUX_937 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORF : X_XOR2 generic map( LOC => "SLICE_X24Y8" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYINIT_939, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_F, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORF_938 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X24Y8" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_LOGIC_ZERO_948, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYINIT_939, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELF_942, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(4) ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X24Y8" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_LOGIC_ZERO_948, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_LOGIC_ZERO_948, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELF_942, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXF2_947 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYINIT : X_BUF generic map( LOC => "SLICE_X24Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYINIT_939 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELF : X_BUF generic map( LOC => "SLICE_X24Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_F, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELF_942 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DYMUX : X_BUF generic map( LOC => "SLICE_X24Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORG_941, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DYMUX_940 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORG : X_XOR2 generic map( LOC => "SLICE_X24Y8" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(4), I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_XORG_941 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_COUTUSED : X_BUF generic map( LOC => "SLICE_X24Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXFAST_943, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5) ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_FASTCARRY : X_BUF generic map( LOC => "SLICE_X24Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_FASTCARRY_945 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYAND : X_AND2 generic map( LOC => "SLICE_X24Y8" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELG_949, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELF_942, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYAND_944 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X24Y8" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXG2_946, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_FASTCARRY_945, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYAND_944, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXFAST_943 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X24Y8" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_LOGIC_ZERO_948, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXF2_947, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELG_949, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYMUXG2_946 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELG : X_BUF generic map( LOC => "SLICE_X24Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CYSELG_949 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_SRINV : X_BUF generic map( LOC => "SLICE_X24Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_SRINV_950 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CLKINV : X_BUF generic map( LOC => "SLICE_X24Y8", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CLKINV_951 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CEINV : X_BUF generic map( LOC => "SLICE_X24Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CEINV_952 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X24Y9" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_LOGIC_ZERO_964 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y9", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORF_954, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DXMUX_953 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORF : X_XOR2 generic map( LOC => "SLICE_X24Y9" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYINIT_955, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_F, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORF_954 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X24Y9" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_LOGIC_ZERO_964, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYINIT_955, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELF_958, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(6) ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X24Y9" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_LOGIC_ZERO_964, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_LOGIC_ZERO_964, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELF_958, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXF2_963 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYINIT : X_BUF generic map( LOC => "SLICE_X24Y9", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYINIT_955 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELF : X_BUF generic map( LOC => "SLICE_X24Y9", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_F, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELF_958 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DYMUX : X_BUF generic map( LOC => "SLICE_X24Y9", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORG_957, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DYMUX_956 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORG : X_XOR2 generic map( LOC => "SLICE_X24Y9" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(6), I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_XORG_957 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_FASTCARRY : X_BUF generic map( LOC => "SLICE_X24Y9", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_FASTCARRY_961 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYAND : X_AND2 generic map( LOC => "SLICE_X24Y9" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELG_965, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELF_958, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYAND_960 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X24Y9" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXG2_962, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_FASTCARRY_961, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYAND_960, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXFAST_959 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X24Y9" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_LOGIC_ZERO_964, IB => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXF2_963, SEL => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELG_965, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXG2_962 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELG : X_BUF generic map( LOC => "SLICE_X24Y9", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_G, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYSELG_965 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_SRINV : X_BUF generic map( LOC => "SLICE_X24Y9", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_SRINV_966 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CLKINV : X_BUF generic map( LOC => "SLICE_X24Y9", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CLKINV_967 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CEINV : X_BUF generic map( LOC => "SLICE_X24Y9", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CEINV_968 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_XORF_970, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_DXMUX_969 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_XORF : X_XOR2 generic map( LOC => "SLICE_X24Y10" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CYINIT_971, I1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_rt_972, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_XORF_970 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CYINIT : X_BUF generic map( LOC => "SLICE_X24Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CYMUXFAST_959, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CYINIT_971 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CLKINV : X_BUF generic map( LOC => "SLICE_X24Y10", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CLKINV_973 ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CEINV : X_BUF generic map( LOC => "SLICE_X24Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CEINV_974 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X31Y4" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ZERO_982 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ONE : X_ONE generic map( LOC => "SLICE_X31Y4" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ONE_976 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DXMUX : X_BUF generic map( LOC => "SLICE_X31Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DXMUX_975 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X31Y4" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ONE_976, IB => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYINIT_977, SEL => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELF_978, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0) ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYINIT : X_BUF generic map( LOC => "SLICE_X31Y4", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYINIT_977 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELF : X_BUF generic map( LOC => "SLICE_X31Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELF_978 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DYMUX : X_BUF generic map( LOC => "SLICE_X31Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_XORG_980, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DYMUX_979 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_XORG : X_XOR2 generic map( LOC => "SLICE_X31Y4" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0), I1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_G, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_XORG_980 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_COUTUSED : X_BUF generic map( LOC => "SLICE_X31Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYMUXG_981, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1) ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X31Y4" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_LOGIC_ZERO_982, IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0), SEL => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELG_983, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYMUXG_981 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELG : X_BUF generic map( LOC => "SLICE_X31Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_G, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CYSELG_983 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_SRINV : X_BUF generic map( LOC => "SLICE_X31Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_SRINV_984 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CLKINV : X_BUF generic map( LOC => "SLICE_X31Y4", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CLKINV_985 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CEINV : X_BUF generic map( LOC => "SLICE_X31Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CEINV_986 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X31Y5" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_LOGIC_ZERO_998 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DXMUX : X_BUF generic map( LOC => "SLICE_X31Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORF_988, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DXMUX_987 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORF : X_XOR2 generic map( LOC => "SLICE_X31Y5" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYINIT_989, I1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_F, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORF_988 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X31Y5" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_LOGIC_ZERO_998, IB => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYINIT_989, SEL => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELF_992, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(2) ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X31Y5" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_LOGIC_ZERO_998, IB => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_LOGIC_ZERO_998, SEL => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELF_992, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXF2_997 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYINIT : X_BUF generic map( LOC => "SLICE_X31Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1), O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYINIT_989 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELF : X_BUF generic map( LOC => "SLICE_X31Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_F, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELF_992 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DYMUX : X_BUF generic map( LOC => "SLICE_X31Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORG_991, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DYMUX_990 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORG : X_XOR2 generic map( LOC => "SLICE_X31Y5" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(2), I1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_G, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_XORG_991 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_COUTUSED : X_BUF generic map( LOC => "SLICE_X31Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXFAST_993, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3) ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_FASTCARRY : X_BUF generic map( LOC => "SLICE_X31Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1), O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_FASTCARRY_995 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYAND : X_AND2 generic map( LOC => "SLICE_X31Y5" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELG_999, I1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELF_992, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYAND_994 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X31Y5" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXG2_996, IB => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_FASTCARRY_995, SEL => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYAND_994, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXFAST_993 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X31Y5" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_LOGIC_ZERO_998, IB => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXF2_997, SEL => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELG_999, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYMUXG2_996 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELG : X_BUF generic map( LOC => "SLICE_X31Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_G, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CYSELG_999 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_SRINV : X_BUF generic map( LOC => "SLICE_X31Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_SRINV_1000 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CLKINV : X_BUF generic map( LOC => "SLICE_X31Y5", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CLKINV_1001 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CEINV : X_BUF generic map( LOC => "SLICE_X31Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CEINV_1002 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X31Y6" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_LOGIC_ZERO_1014 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DXMUX : X_BUF generic map( LOC => "SLICE_X31Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORF_1004, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DXMUX_1003 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORF : X_XOR2 generic map( LOC => "SLICE_X31Y6" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYINIT_1005, I1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_F, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORF_1004 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X31Y6" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_LOGIC_ZERO_1014, IB => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYINIT_1005, SEL => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELF_1008, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(4) ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X31Y6" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_LOGIC_ZERO_1014, IB => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_LOGIC_ZERO_1014, SEL => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELF_1008, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXF2_1013 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYINIT : X_BUF generic map( LOC => "SLICE_X31Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3), O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYINIT_1005 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELF : X_BUF generic map( LOC => "SLICE_X31Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_F, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELF_1008 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DYMUX : X_BUF generic map( LOC => "SLICE_X31Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORG_1007, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DYMUX_1006 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORG : X_XOR2 generic map( LOC => "SLICE_X31Y6" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(4), I1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_G, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_XORG_1007 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_COUTUSED : X_BUF generic map( LOC => "SLICE_X31Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXFAST_1009, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5) ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_FASTCARRY : X_BUF generic map( LOC => "SLICE_X31Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3), O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_FASTCARRY_1011 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYAND : X_AND2 generic map( LOC => "SLICE_X31Y6" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELG_1015, I1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELF_1008, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYAND_1010 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X31Y6" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXG2_1012, IB => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_FASTCARRY_1011, SEL => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYAND_1010, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXFAST_1009 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X31Y6" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_LOGIC_ZERO_1014, IB => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXF2_1013, SEL => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELG_1015, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYMUXG2_1012 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELG : X_BUF generic map( LOC => "SLICE_X31Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_G, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CYSELG_1015 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_SRINV : X_BUF generic map( LOC => "SLICE_X31Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_SRINV_1016 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CLKINV : X_BUF generic map( LOC => "SLICE_X31Y6", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CLKINV_1017 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CEINV : X_BUF generic map( LOC => "SLICE_X31Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CEINV_1018 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X31Y7" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_LOGIC_ZERO_1030 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DXMUX : X_BUF generic map( LOC => "SLICE_X31Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORF_1020, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DXMUX_1019 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORF : X_XOR2 generic map( LOC => "SLICE_X31Y7" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYINIT_1021, I1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_F, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORF_1020 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X31Y7" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_LOGIC_ZERO_1030, IB => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYINIT_1021, SEL => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELF_1024, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(6) ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X31Y7" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_LOGIC_ZERO_1030, IB => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_LOGIC_ZERO_1030, SEL => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELF_1024, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXF2_1029 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYINIT : X_BUF generic map( LOC => "SLICE_X31Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5), O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYINIT_1021 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELF : X_BUF generic map( LOC => "SLICE_X31Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_F, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELF_1024 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DYMUX : X_BUF generic map( LOC => "SLICE_X31Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORG_1023, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DYMUX_1022 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORG : X_XOR2 generic map( LOC => "SLICE_X31Y7" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(6), I1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_G, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_XORG_1023 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_FASTCARRY : X_BUF generic map( LOC => "SLICE_X31Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5), O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_FASTCARRY_1027 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYAND : X_AND2 generic map( LOC => "SLICE_X31Y7" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELG_1031, I1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELF_1024, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYAND_1026 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X31Y7" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXG2_1028, IB => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_FASTCARRY_1027, SEL => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYAND_1026, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXFAST_1025 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X31Y7" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_LOGIC_ZERO_1030, IB => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXF2_1029, SEL => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELG_1031, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXG2_1028 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELG : X_BUF generic map( LOC => "SLICE_X31Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_G, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYSELG_1031 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_SRINV : X_BUF generic map( LOC => "SLICE_X31Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_SRINV_1032 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CLKINV : X_BUF generic map( LOC => "SLICE_X31Y7", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CLKINV_1033 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CEINV : X_BUF generic map( LOC => "SLICE_X31Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CEINV_1034 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_DXMUX : X_BUF generic map( LOC => "SLICE_X31Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_XORF_1036, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_DXMUX_1035 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_XORF : X_XOR2 generic map( LOC => "SLICE_X31Y8" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CYINIT_1037, I1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_rt_1038, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_XORF_1036 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CYINIT : X_BUF generic map( LOC => "SLICE_X31Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CYMUXFAST_1025, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CYINIT_1037 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CLKINV : X_BUF generic map( LOC => "SLICE_X31Y8", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CLKINV_1039 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CEINV : X_BUF generic map( LOC => "SLICE_X31Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CEINV_1040 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X29Y0" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ZERO_1048 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ONE : X_ONE generic map( LOC => "SLICE_X29Y0" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ONE_1042 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DXMUX : X_BUF generic map( LOC => "SLICE_X29Y0", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DXMUX_1041 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X29Y0" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ONE_1042 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYINIT_1043 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELF_1044 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYINIT : X_BUF generic map( LOC => "SLICE_X29Y0", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYINIT_1043 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELF : X_BUF generic map( LOC => "SLICE_X29Y0", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELF_1044 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DYMUX : X_BUF generic map( LOC => "SLICE_X29Y0", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_XORG_1046 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DYMUX_1045 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_XORG : X_XOR2 generic map( LOC => "SLICE_X29Y0" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0) , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_XORG_1046 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_COUTUSED : X_BUF generic map( LOC => "SLICE_X29Y0", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYMUXG_1047 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X29Y0" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_LOGIC_ZERO_1048 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(0) , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELG_1049 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYMUXG_1047 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELG : X_BUF generic map( LOC => "SLICE_X29Y0", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CYSELG_1049 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_SRINV : X_BUF generic map( LOC => "SLICE_X29Y0", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_SRINV_1050 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CLKINV : X_BUF generic map( LOC => "SLICE_X29Y0", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CLKINV_1051 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CEINV : X_BUF generic map( LOC => "SLICE_X29Y0", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CEINV_1052 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X29Y1" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_1064 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DXMUX : X_BUF generic map( LOC => "SLICE_X29Y1", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORF_1054 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DXMUX_1053 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORF : X_XOR2 generic map( LOC => "SLICE_X29Y1" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYINIT_1055 , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_F, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORF_1054 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X29Y1" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_1064 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYINIT_1055 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF_1058 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X29Y1" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_1064 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_1064 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF_1058 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXF2_1063 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYINIT : X_BUF generic map( LOC => "SLICE_X29Y1", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1) , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYINIT_1055 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF : X_BUF generic map( LOC => "SLICE_X29Y1", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_F, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF_1058 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DYMUX : X_BUF generic map( LOC => "SLICE_X29Y1", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORG_1057 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DYMUX_1056 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORG : X_XOR2 generic map( LOC => "SLICE_X29Y1" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(2) , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_XORG_1057 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_COUTUSED : X_BUF generic map( LOC => "SLICE_X29Y1", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXFAST_1059 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_FASTCARRY : X_BUF generic map( LOC => "SLICE_X29Y1", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(1) , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_FASTCARRY_1061 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYAND : X_AND2 generic map( LOC => "SLICE_X29Y1" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELG_1065 , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELF_1058 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYAND_1060 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X29Y1" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXG2_1062 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_FASTCARRY_1061 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYAND_1060 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXFAST_1059 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X29Y1" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_LOGIC_ZERO_1064 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXF2_1063 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELG_1065 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYMUXG2_1062 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELG : X_BUF generic map( LOC => "SLICE_X29Y1", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CYSELG_1065 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_SRINV : X_BUF generic map( LOC => "SLICE_X29Y1", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_SRINV_1066 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CLKINV : X_BUF generic map( LOC => "SLICE_X29Y1", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CLKINV_1067 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CEINV : X_BUF generic map( LOC => "SLICE_X29Y1", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CEINV_1068 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X29Y2" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_1080 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DXMUX : X_BUF generic map( LOC => "SLICE_X29Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORF_1070 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DXMUX_1069 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORF : X_XOR2 generic map( LOC => "SLICE_X29Y2" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYINIT_1071 , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_F, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORF_1070 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X29Y2" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_1080 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYINIT_1071 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF_1074 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X29Y2" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_1080 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_1080 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF_1074 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXF2_1079 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYINIT : X_BUF generic map( LOC => "SLICE_X29Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3) , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYINIT_1071 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF : X_BUF generic map( LOC => "SLICE_X29Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_F, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF_1074 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DYMUX : X_BUF generic map( LOC => "SLICE_X29Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORG_1073 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DYMUX_1072 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORG : X_XOR2 generic map( LOC => "SLICE_X29Y2" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(4) , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_XORG_1073 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_COUTUSED : X_BUF generic map( LOC => "SLICE_X29Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXFAST_1075 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_FASTCARRY : X_BUF generic map( LOC => "SLICE_X29Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(3) , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_FASTCARRY_1077 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYAND : X_AND2 generic map( LOC => "SLICE_X29Y2" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELG_1081 , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELF_1074 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYAND_1076 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X29Y2" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXG2_1078 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_FASTCARRY_1077 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYAND_1076 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXFAST_1075 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X29Y2" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_LOGIC_ZERO_1080 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXF2_1079 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELG_1081 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYMUXG2_1078 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELG : X_BUF generic map( LOC => "SLICE_X29Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CYSELG_1081 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_SRINV : X_BUF generic map( LOC => "SLICE_X29Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_SRINV_1082 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CLKINV : X_BUF generic map( LOC => "SLICE_X29Y2", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CLKINV_1083 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CEINV : X_BUF generic map( LOC => "SLICE_X29Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CEINV_1084 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X29Y3" ) port map ( O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_1096 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DXMUX : X_BUF generic map( LOC => "SLICE_X29Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORF_1086 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DXMUX_1085 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORF : X_XOR2 generic map( LOC => "SLICE_X29Y3" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYINIT_1087 , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_F, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORF_1086 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X29Y3" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_1096 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYINIT_1087 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF_1090 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(6) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X29Y3" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_1096 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_1096 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF_1090 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXF2_1095 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYINIT : X_BUF generic map( LOC => "SLICE_X29Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5) , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYINIT_1087 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF : X_BUF generic map( LOC => "SLICE_X29Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_F, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF_1090 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DYMUX : X_BUF generic map( LOC => "SLICE_X29Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORG_1089 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DYMUX_1088 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORG : X_XOR2 generic map( LOC => "SLICE_X29Y3" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(6) , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_XORG_1089 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_FASTCARRY : X_BUF generic map( LOC => "SLICE_X29Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_cy(5) , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_FASTCARRY_1093 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYAND : X_AND2 generic map( LOC => "SLICE_X29Y3" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELG_1097 , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELF_1090 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYAND_1092 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X29Y3" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXG2_1094 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_FASTCARRY_1093 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYAND_1092 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXFAST_1091 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X29Y3" ) port map ( IA => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_LOGIC_ZERO_1096 , IB => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXF2_1095 , SEL => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELG_1097 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXG2_1094 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELG : X_BUF generic map( LOC => "SLICE_X29Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_G, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYSELG_1097 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_SRINV : X_BUF generic map( LOC => "SLICE_X29Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_SRINV_1098 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CLKINV : X_BUF generic map( LOC => "SLICE_X29Y3", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CLKINV_1099 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CEINV : X_BUF generic map( LOC => "SLICE_X29Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CEINV_1100 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DXMUX : X_BUF generic map( LOC => "SLICE_X29Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORF_1102 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DXMUX_1101 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORF : X_XOR2 generic map( LOC => "SLICE_X29Y4" ) port map ( I0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYINIT_1103 , I1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_rt_1104 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_XORF_1102 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYINIT : X_BUF generic map( LOC => "SLICE_X29Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CYMUXFAST_1091 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CYINIT_1103 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CLKINV : X_BUF generic map( LOC => "SLICE_X29Y4", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CLKINV_1105 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CEINV : X_BUF generic map( LOC => "SLICE_X29Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CEINV_1106 ); i_WRU_IBUF : X_BUF generic map( LOC => "PAD387", PATHPULSE => 757 ps ) port map ( I => i_WRU, O => i_WRU_INBUF ); i_WRU_IFF_IMUX : X_BUF generic map( LOC => "PAD387", PATHPULSE => 757 ps ) port map ( I => i_WRU_INBUF, O => i_WRU_IBUF_2 ); i_RDYU_IBUF : X_BUF generic map( LOC => "PAD388", PATHPULSE => 757 ps ) port map ( I => i_RDYU, O => i_RDYU_INBUF ); i_RDYU_IFF_IMUX : X_BUF generic map( LOC => "PAD388", PATHPULSE => 757 ps ) port map ( I => i_RDYU_INBUF, O => i_RDYU_IBUF_3 ); b_dbus_10_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD331" ) port map ( I => b_dbus_10_O, CTL => b_dbus_10_T, O => b_dbus(10) ); b_dbus_10_IOBUF_IBUF : X_BUF generic map( LOC => "PAD331", PATHPULSE => 757 ps ) port map ( I => b_dbus(10), O => b_dbus_10_INBUF ); b_dbus_11_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD370" ) port map ( I => b_dbus_11_O, CTL => b_dbus_11_T, O => b_dbus(11) ); b_dbus_11_IOBUF_IBUF : X_BUF generic map( LOC => "PAD370", PATHPULSE => 757 ps ) port map ( I => b_dbus(11), O => b_dbus_11_INBUF ); b_dbus_12_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD324" ) port map ( I => b_dbus_12_O, CTL => b_dbus_12_T, O => b_dbus(12) ); b_dbus_12_IOBUF_IBUF : X_BUF generic map( LOC => "PAD324", PATHPULSE => 757 ps ) port map ( I => b_dbus(12), O => b_dbus_12_INBUF ); b_dbus_13_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD334" ) port map ( I => b_dbus_13_O, CTL => b_dbus_13_T, O => b_dbus(13) ); b_dbus_13_IOBUF_IBUF : X_BUF generic map( LOC => "PAD334", PATHPULSE => 757 ps ) port map ( I => b_dbus(13), O => b_dbus_13_INBUF ); b_dbus_14_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD337" ) port map ( I => b_dbus_14_O, CTL => b_dbus_14_T, O => b_dbus(14) ); b_dbus_14_IOBUF_IBUF : X_BUF generic map( LOC => "PAD337", PATHPULSE => 757 ps ) port map ( I => b_dbus(14), O => b_dbus_14_INBUF ); b_dbus_15_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD338" ) port map ( I => b_dbus_15_O, CTL => b_dbus_15_T, O => b_dbus(15) ); b_dbus_15_IOBUF_IBUF : X_BUF generic map( LOC => "PAD338", PATHPULSE => 757 ps ) port map ( I => b_dbus(15), O => b_dbus_15_INBUF ); o_WRX_OBUF : X_OBUF generic map( LOC => "PAD320" ) port map ( I => o_WRX_O, O => o_WRX ); o_RDYX_OBUF : X_OBUF generic map( LOC => "PAD321" ) port map ( I => o_RDYX_O, O => o_RDYX ); o_LEDrx_OBUF : X_OBUF generic map( LOC => "PAD14" ) port map ( I => o_LEDrx_O, O => o_LEDrx ); o_LEDtx_OBUF : X_OBUF generic map( LOC => "PAD21" ) port map ( I => o_LEDtx_O, O => o_LEDtx ); b_dbus_0_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD336" ) port map ( I => b_dbus_0_O, CTL => b_dbus_0_T, O => b_dbus(0) ); b_dbus_0_IOBUF_IBUF : X_BUF generic map( LOC => "PAD336", PATHPULSE => 757 ps ) port map ( I => b_dbus(0), O => b_dbus_0_INBUF ); b_dbus_1_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD335" ) port map ( I => b_dbus_1_O, CTL => b_dbus_1_T, O => b_dbus(1) ); b_dbus_1_IOBUF_IBUF : X_BUF generic map( LOC => "PAD335", PATHPULSE => 757 ps ) port map ( I => b_dbus(1), O => b_dbus_1_INBUF ); b_dbus_2_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD328" ) port map ( I => b_dbus_2_O, CTL => b_dbus_2_T, O => b_dbus(2) ); b_dbus_2_IOBUF_IBUF : X_BUF generic map( LOC => "PAD328", PATHPULSE => 757 ps ) port map ( I => b_dbus(2), O => b_dbus_2_INBUF ); b_dbus_3_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD327" ) port map ( I => b_dbus_3_O, CTL => b_dbus_3_T, O => b_dbus(3) ); b_dbus_3_IOBUF_IBUF : X_BUF generic map( LOC => "PAD327", PATHPULSE => 757 ps ) port map ( I => b_dbus(3), O => b_dbus_3_INBUF ); b_dbus_4_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD318" ) port map ( I => b_dbus_4_O, CTL => b_dbus_4_T, O => b_dbus(4) ); b_dbus_4_IOBUF_IBUF : X_BUF generic map( LOC => "PAD318", PATHPULSE => 757 ps ) port map ( I => b_dbus(4), O => b_dbus_4_INBUF ); i_SYSCLK_BUFGP_IBUFG : X_BUF generic map( LOC => "PAD322", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK, O => i_SYSCLK_INBUF ); b_dbus_5_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD317" ) port map ( I => b_dbus_5_O, CTL => b_dbus_5_T, O => b_dbus(5) ); b_dbus_5_IOBUF_IBUF : X_BUF generic map( LOC => "PAD317", PATHPULSE => 757 ps ) port map ( I => b_dbus(5), O => b_dbus_5_INBUF ); b_dbus_6_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD311" ) port map ( I => b_dbus_6_O, CTL => b_dbus_6_T, O => b_dbus(6) ); b_dbus_6_IOBUF_IBUF : X_BUF generic map( LOC => "PAD311", PATHPULSE => 757 ps ) port map ( I => b_dbus(6), O => b_dbus_6_INBUF ); b_dbus_7_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD310" ) port map ( I => b_dbus_7_O, CTL => b_dbus_7_T, O => b_dbus(7) ); b_dbus_7_IOBUF_IBUF : X_BUF generic map( LOC => "PAD310", PATHPULSE => 757 ps ) port map ( I => b_dbus(7), O => b_dbus_7_INBUF ); b_dbus_8_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD371" ) port map ( I => b_dbus_8_O, CTL => b_dbus_8_T, O => b_dbus(8) ); b_dbus_8_IOBUF_IBUF : X_BUF generic map( LOC => "PAD371", PATHPULSE => 757 ps ) port map ( I => b_dbus(8), O => b_dbus_8_INBUF ); b_dbus_9_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD330" ) port map ( I => b_dbus_9_O, CTL => b_dbus_9_T, O => b_dbus(9) ); b_dbus_9_IOBUF_IBUF : X_BUF generic map( LOC => "PAD330", PATHPULSE => 757 ps ) port map ( I => b_dbus(9), O => b_dbus_9_INBUF ); i_nReset_IBUF : X_BUF generic map( LOC => "PAD262", PATHPULSE => 757 ps ) port map ( I => i_nReset, O => i_nReset_INBUF ); i_nReset_IFF_IMUX : X_BUF generic map( LOC => "PAD262", PATHPULSE => 757 ps ) port map ( I => i_nReset_INBUF, O => i_nReset_IBUF_4 ); i_IFCLK_BUFGP_IBUFG : X_BUF generic map( LOC => "PAD343", PATHPULSE => 757 ps ) port map ( I => i_IFCLK, O => i_IFCLK_INBUF ); o_LEDrun_OBUF : X_OBUF generic map( LOC => "PAD18" ) port map ( I => o_LEDrun_O, O => o_LEDrun ); i_SYSCLK_BUFGP_BUFG : X_BUFGMUX generic map( LOC => "BUFGMUX1" ) port map ( I0 => i_SYSCLK_BUFGP_BUFG_I0_INV, I1 => GND, S => i_SYSCLK_BUFGP_BUFG_S_INVNOT, O => i_SYSCLK_BUFGP ); i_SYSCLK_BUFGP_BUFG_SINV : X_INV generic map( LOC => "BUFGMUX1", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => i_SYSCLK_BUFGP_BUFG_S_INVNOT ); i_SYSCLK_BUFGP_BUFG_I0_USED : X_BUF generic map( LOC => "BUFGMUX1", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_INBUF, O => i_SYSCLK_BUFGP_BUFG_I0_INV ); i_IFCLK_BUFGP_BUFG : X_BUFGMUX generic map( LOC => "BUFGMUX3" ) port map ( I0 => i_IFCLK_BUFGP_BUFG_I0_INV, I1 => GND, S => i_IFCLK_BUFGP_BUFG_S_INVNOT, O => i_IFCLK_BUFGP ); i_IFCLK_BUFGP_BUFG_SINV : X_INV generic map( LOC => "BUFGMUX3", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC1, O => i_IFCLK_BUFGP_BUFG_S_INVNOT ); i_IFCLK_BUFGP_BUFG_I0_USED : X_BUF generic map( LOC => "BUFGMUX3", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_INBUF, O => i_IFCLK_BUFGP_BUFG_I0_INV ); F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_WEAINV : X_INV generic map( LOC => "RAMB16_X0Y0", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_WEA_INTNOT ); F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram : X_RAMB16_S18_S36 generic map( INIT_A => X"00000", INIT_B => X"000000000", SRVAL_A => X"00000", SRVAL_B => X"000000000", SIM_COLLISION_CHECK => "NONE", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", LOC => "RAMB16_X0Y0", SETUP_ALL => 484 ps, SETUP_READ_FIRST => 484 ps ) port map ( CLKA => i_IFCLK_BUFGP, CLKB => i_SYSCLK_BUFGP, ENA => GLOBAL_LOGIC1, ENB => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en_0, SSRA => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, SSRB => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, WEA => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_WEA_INTNOT, WEB => GLOBAL_LOGIC0, ADDRA(9) => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(9), ADDRA(8) => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(8), ADDRA(7) => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(7), ADDRA(6) => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(6), ADDRA(5) => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(5), ADDRA(4) => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(4), ADDRA(3) => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(3), ADDRA(2) => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(2), ADDRA(1) => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(1), ADDRA(0) => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(0), ADDRB(8) => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(8), ADDRB(7) => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(7), ADDRB(6) => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(6), ADDRB(5) => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(5), ADDRB(4) => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(4), ADDRB(3) => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(3), ADDRB(2) => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(2), ADDRB(1) => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(1), ADDRB(0) => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(0), DIA(15) => FSM_GPIF_o_dbus(15), DIA(14) => FSM_GPIF_o_dbus(14), DIA(13) => FSM_GPIF_o_dbus(13), DIA(12) => FSM_GPIF_o_dbus(12), DIA(11) => FSM_GPIF_o_dbus(11), DIA(10) => FSM_GPIF_o_dbus(10), DIA(9) => FSM_GPIF_o_dbus(9), DIA(8) => FSM_GPIF_o_dbus(8), DIA(7) => FSM_GPIF_o_dbus(7), DIA(6) => FSM_GPIF_o_dbus(6), DIA(5) => FSM_GPIF_o_dbus(5), DIA(4) => FSM_GPIF_o_dbus(4), DIA(3) => FSM_GPIF_o_dbus(3), DIA(2) => FSM_GPIF_o_dbus(2), DIA(1) => FSM_GPIF_o_dbus(1), DIA(0) => FSM_GPIF_o_dbus(0), DIPA(1) => GLOBAL_LOGIC0, DIPA(0) => GLOBAL_LOGIC0, DIB(31) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB31, DIB(30) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB30, DIB(29) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB29, DIB(28) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB28, DIB(27) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB27, DIB(26) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB26, DIB(25) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB25, DIB(24) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB24, DIB(23) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB23, DIB(22) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB22, DIB(21) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB21, DIB(20) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB20, DIB(19) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB19, DIB(18) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB18, DIB(17) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB17, DIB(16) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB16, DIB(15) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB15, DIB(14) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB14, DIB(13) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB13, DIB(12) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB12, DIB(11) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB11, DIB(10) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB10, DIB(9) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB9, DIB(8) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB8, DIB(7) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB7, DIB(6) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB6, DIB(5) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB5, DIB(4) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB4, DIB(3) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB3, DIB(2) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB2, DIB(1) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB1, DIB(0) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIB0, DIPB(3) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIPB3, DIPB(2) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIPB2, DIPB(1) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIPB1, DIPB(0) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DIPB0, DOA(15) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA15, DOA(14) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA14, DOA(13) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA13, DOA(12) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA12, DOA(11) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA11, DOA(10) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA10, DOA(9) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA9, DOA(8) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA8, DOA(7) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA7, DOA(6) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA6, DOA(5) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA5, DOA(4) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA4, DOA(3) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA3, DOA(2) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA2, DOA(1) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA1, DOA(0) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOA0, DOPA(1) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOPA1, DOPA(0) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOPA0, DOB(31) => s_opb_in(15), DOB(30) => s_opb_in(14), DOB(29) => s_opb_in(13), DOB(28) => s_opb_in(12), DOB(27) => s_opb_in(11), DOB(26) => s_opb_in(10), DOB(25) => s_opb_in(9), DOB(24) => s_opb_in(8), DOB(23) => s_opb_in(7), DOB(22) => s_opb_in(6), DOB(21) => s_opb_in(5), DOB(20) => s_opb_in(4), DOB(19) => s_opb_in(3), DOB(18) => s_opb_in(2), DOB(17) => s_opb_in(1), DOB(16) => s_opb_in(0), DOB(15) => s_opb_in(31), DOB(14) => s_opb_in(30), DOB(13) => s_opb_in(29), DOB(12) => s_opb_in(28), DOB(11) => s_opb_in(27), DOB(10) => s_opb_in(26), DOB(9) => s_opb_in(25), DOB(8) => s_opb_in(24), DOB(7) => s_opb_in(23), DOB(6) => s_opb_in(22), DOB(5) => s_opb_in(21), DOB(4) => s_opb_in(20), DOB(3) => s_opb_in(19), DOB(2) => s_opb_in(18), DOB(1) => s_opb_in(17), DOB(0) => s_opb_in(16), DOPB(3) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOPB3, DOPB(2) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOPB2, DOPB(1) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOPB1, DOPB(0) => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp18x36_ram_DOPB0 ); F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram : X_RAMB16_S18_S36 generic map( INIT_A => X"00000", INIT_B => X"000000000", SRVAL_A => X"00000", SRVAL_B => X"000000000", SIM_COLLISION_CHECK => "NONE", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", LOC => "RAMB16_X0Y1", SETUP_ALL => 484 ps, SETUP_READ_FIRST => 484 ps ) port map ( CLKA => i_IFCLK_BUFGP, CLKB => i_SYSCLK_BUFGP, ENA => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en_0, ENB => GLOBAL_LOGIC1, SSRA => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, SSRB => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, WEA => GLOBAL_LOGIC0, WEB => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0, ADDRA(9) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(9), ADDRA(8) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(8), ADDRA(7) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(7), ADDRA(6) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(6), ADDRA(5) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(5), ADDRA(4) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(4), ADDRA(3) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(3), ADDRA(2) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(2), ADDRA(1) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(1), ADDRA(0) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(0), ADDRB(8) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(8), ADDRB(7) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(7), ADDRB(6) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(6), ADDRB(5) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(5), ADDRB(4) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(4), ADDRB(3) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(3), ADDRB(2) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(2), ADDRB(1) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(1), ADDRB(0) => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(0), DIA(15) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA15, DIA(14) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA14, DIA(13) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA13, DIA(12) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA12, DIA(11) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA11, DIA(10) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA10, DIA(9) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA9, DIA(8) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA8, DIA(7) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA7, DIA(6) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA6, DIA(5) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA5, DIA(4) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA4, DIA(3) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA3, DIA(2) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA2, DIA(1) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA1, DIA(0) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIA0, DIPA(1) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIPA1, DIPA(0) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DIPA0, DIB(31) => Loopback_o_X2U_DATA(15), DIB(30) => Loopback_o_X2U_DATA(14), DIB(29) => Loopback_o_X2U_DATA(13), DIB(28) => Loopback_o_X2U_DATA(12), DIB(27) => Loopback_o_X2U_DATA(11), DIB(26) => Loopback_o_X2U_DATA(10), DIB(25) => Loopback_o_X2U_DATA(9), DIB(24) => Loopback_o_X2U_DATA(8), DIB(23) => Loopback_o_X2U_DATA(7), DIB(22) => Loopback_o_X2U_DATA(6), DIB(21) => Loopback_o_X2U_DATA(5), DIB(20) => Loopback_o_X2U_DATA(4), DIB(19) => Loopback_o_X2U_DATA(3), DIB(18) => Loopback_o_X2U_DATA(2), DIB(17) => Loopback_o_X2U_DATA(1), DIB(16) => Loopback_o_X2U_DATA(0), DIB(15) => Loopback_o_X2U_DATA(31), DIB(14) => Loopback_o_X2U_DATA(30), DIB(13) => Loopback_o_X2U_DATA(29), DIB(12) => Loopback_o_X2U_DATA(28), DIB(11) => Loopback_o_X2U_DATA(27), DIB(10) => Loopback_o_X2U_DATA(26), DIB(9) => Loopback_o_X2U_DATA(25), DIB(8) => Loopback_o_X2U_DATA(24), DIB(7) => Loopback_o_X2U_DATA(23), DIB(6) => Loopback_o_X2U_DATA(22), DIB(5) => Loopback_o_X2U_DATA(21), DIB(4) => Loopback_o_X2U_DATA(20), DIB(3) => Loopback_o_X2U_DATA(19), DIB(2) => Loopback_o_X2U_DATA(18), DIB(1) => Loopback_o_X2U_DATA(17), DIB(0) => Loopback_o_X2U_DATA(16), DIPB(3) => GLOBAL_LOGIC0, DIPB(2) => GLOBAL_LOGIC0, DIPB(1) => GLOBAL_LOGIC0, DIPB(0) => GLOBAL_LOGIC0, DOA(15) => s_dbus_out(15), DOA(14) => s_dbus_out(14), DOA(13) => s_dbus_out(13), DOA(12) => s_dbus_out(12), DOA(11) => s_dbus_out(11), DOA(10) => s_dbus_out(10), DOA(9) => s_dbus_out(9), DOA(8) => s_dbus_out(8), DOA(7) => s_dbus_out(7), DOA(6) => s_dbus_out(6), DOA(5) => s_dbus_out(5), DOA(4) => s_dbus_out(4), DOA(3) => s_dbus_out(3), DOA(2) => s_dbus_out(2), DOA(1) => s_dbus_out(1), DOA(0) => s_dbus_out(0), DOPA(1) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOPA1, DOPA(0) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOPA0, DOB(31) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB31, DOB(30) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB30, DOB(29) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB29, DOB(28) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB28, DOB(27) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB27, DOB(26) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB26, DOB(25) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB25, DOB(24) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB24, DOB(23) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB23, DOB(22) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB22, DOB(21) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB21, DOB(20) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB20, DOB(19) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB19, DOB(18) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB18, DOB(17) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB17, DOB(16) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB16, DOB(15) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB15, DOB(14) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB14, DOB(13) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB13, DOB(12) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB12, DOB(11) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB11, DOB(10) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB10, DOB(9) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB9, DOB(8) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB8, DOB(7) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB7, DOB(6) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB6, DOB(5) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB5, DOB(4) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB4, DOB(3) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB3, DOB(2) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB2, DOB(1) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB1, DOB(0) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOB0, DOPB(3) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOPB3, DOPB(2) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOPB2, DOPB(1) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOPB1, DOPB(0) => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_bmem_bmg_bmg_inst_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_ram_dp36x18_ram_DOPB0 ); s_X2U_RD_EN_XUSED : X_BUF generic map( LOC => "SLICE_X35Y7", PATHPULSE => 757 ps ) port map ( I => s_X2U_RD_EN_F5MUX_1107, O => s_X2U_RD_EN ); s_X2U_RD_EN_F5MUX : X_MUX2 generic map( LOC => "SLICE_X35Y7" ) port map ( IA => N361, IB => N360, SEL => s_X2U_RD_EN_BXINV_1108, O => s_X2U_RD_EN_F5MUX_1107 ); s_X2U_RD_EN_BXINV : X_BUF generic map( LOC => "SLICE_X35Y7", PATHPULSE => 757 ps ) port map ( I => s_X2U_EMPTY, O => s_X2U_RD_EN_BXINV_1108 ); FSM_GPIF_pr_state_FFd4_In_map18_XUSED : X_BUF generic map( LOC => "SLICE_X34Y9", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_FFd4_In_map18_F5MUX_1109, O => FSM_GPIF_pr_state_FFd4_In_map18 ); FSM_GPIF_pr_state_FFd4_In_map18_F5MUX : X_MUX2 generic map( LOC => "SLICE_X34Y9" ) port map ( IA => N363, IB => N362, SEL => FSM_GPIF_pr_state_FFd4_In_map18_BXINV_1110, O => FSM_GPIF_pr_state_FFd4_In_map18_F5MUX_1109 ); FSM_GPIF_pr_state_FFd4_In_map18_BXINV : X_BUF generic map( LOC => "SLICE_X34Y9", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_FFd3_7, O => FSM_GPIF_pr_state_FFd4_In_map18_BXINV_1110 ); Loopback_pr_stateLoop_FFd2_DXMUX : X_BUF generic map( LOC => "SLICE_X28Y7", PATHPULSE => 757 ps ) port map ( I => Loopback_pr_stateLoop_FFd2_F5MUX_1112, O => Loopback_pr_stateLoop_FFd2_DXMUX_1111 ); Loopback_pr_stateLoop_FFd2_F5MUX : X_MUX2 generic map( LOC => "SLICE_X28Y7" ) port map ( IA => N358, IB => N357, SEL => Loopback_pr_stateLoop_FFd2_BXINV_1113, O => Loopback_pr_stateLoop_FFd2_F5MUX_1112 ); Loopback_pr_stateLoop_FFd2_BXINV : X_BUF generic map( LOC => "SLICE_X28Y7", PATHPULSE => 757 ps ) port map ( I => s_X2U_AM_FULL, O => Loopback_pr_stateLoop_FFd2_BXINV_1113 ); Loopback_pr_stateLoop_FFd2_CLKINV : X_BUF generic map( LOC => "SLICE_X28Y7", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_pr_stateLoop_FFd2_CLKINV_1114 ); Loopback_pr_stateLoop_FFd2_In2 : X_LUT4 generic map( INIT => X"4EFF", LOC => "SLICE_X28Y7" ) port map ( ADR0 => Loopback_pr_stateLoop_FFd3_8, ADR1 => s_U2X_AM_EMPTY, ADR2 => s_U2X_EMPTY, ADR3 => Loopback_pr_stateLoop_FFd2_9, O => N358 ); o_RDYX_OBUF_F5MUX : X_MUX2 generic map( LOC => "SLICE_X38Y11" ) port map ( IA => N354, IB => N355, SEL => o_RDYX_OBUF_BXINV_1116, O => o_RDYX_OBUF_F5MUX_1115 ); o_RDYX_OBUF_BXINV : X_BUF generic map( LOC => "SLICE_X38Y11", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_FFd4_6, O => o_RDYX_OBUF_BXINV_1116 ); FSM_GPIF_v_setup_not0001_XUSED : X_BUF generic map( LOC => "SLICE_X37Y9", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_v_setup_not0001_1117, O => FSM_GPIF_v_setup_not0001_0 ); FSM_GPIF_v_setup_not0001_YUSED : X_BUF generic map( LOC => "SLICE_X37Y9", PATHPULSE => 757 ps ) port map ( I => N4_pack_1, O => N4 ); FSM_GPIF_pr_state_FFd3_In11 : X_LUT4 generic map( INIT => X"ACA1", LOC => "SLICE_X37Y9" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd1_5, ADR1 => FSM_GPIF_pr_state_FFd3_7, ADR2 => FSM_GPIF_pr_state_FFd4_6, ADR3 => FSM_GPIF_pr_state_FFd2_10, O => N4_pack_1 ); FSM_GPIF_pr_state_FFd3_DXMUX : X_BUF generic map( LOC => "SLICE_X36Y11", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_FFd3_In, O => FSM_GPIF_pr_state_FFd3_DXMUX_1118 ); FSM_GPIF_pr_state_FFd3_YUSED : X_BUF generic map( LOC => "SLICE_X36Y11", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_FFd3_In98_SW0_O_pack_1, O => FSM_GPIF_pr_state_FFd3_In98_SW0_O ); FSM_GPIF_pr_state_FFd3_CLKINV : X_BUF generic map( LOC => "SLICE_X36Y11", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => FSM_GPIF_pr_state_FFd3_CLKINV_1119 ); FSM_GPIF_pr_state_FFd3_CEINV : X_BUF generic map( LOC => "SLICE_X36Y11", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_not0001_0, O => FSM_GPIF_pr_state_FFd3_CEINV_1120 ); FSM_GPIF_v_setup_3_DXMUX : X_BUF generic map( LOC => "SLICE_X39Y7", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_Mcount_v_setup_eqn_3, O => FSM_GPIF_v_setup_3_DXMUX_1121 ); FSM_GPIF_v_setup_3_YUSED : X_BUF generic map( LOC => "SLICE_X39Y7", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_Mcount_v_setup_eqn_332_O_pack_1, O => FSM_GPIF_Mcount_v_setup_eqn_332_O ); FSM_GPIF_v_setup_3_CLKINV : X_BUF generic map( LOC => "SLICE_X39Y7", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => FSM_GPIF_v_setup_3_CLKINV_1122 ); FSM_GPIF_v_setup_3_CEINV : X_BUF generic map( LOC => "SLICE_X39Y7", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_v_setup_not0001_0, O => FSM_GPIF_v_setup_3_CEINV_1123 ); FSM_GPIF_pr_state_FFd4_DXMUX : X_BUF generic map( LOC => "SLICE_X36Y9", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_FFd4_In, O => FSM_GPIF_pr_state_FFd4_DXMUX_1124 ); FSM_GPIF_pr_state_FFd4_YUSED : X_BUF generic map( LOC => "SLICE_X36Y9", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_FFd4_In13_O_pack_1, O => FSM_GPIF_pr_state_FFd4_In13_O ); FSM_GPIF_pr_state_FFd4_CLKINV : X_BUF generic map( LOC => "SLICE_X36Y9", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => FSM_GPIF_pr_state_FFd4_CLKINV_1125 ); FSM_GPIF_pr_state_FFd4_CEINV : X_BUF generic map( LOC => "SLICE_X36Y9", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_not0001_0, O => FSM_GPIF_pr_state_FFd4_CEINV_1126 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_DXMUX : X_BUF generic map( LOC => "SLICE_X42Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0007, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_DXMUX_1127 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_YUSED : X_BUF generic map( LOC => "SLICE_X42Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1_O_pack_1, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1_O ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_CLKINV : X_BUF generic map( LOC => "SLICE_X42Y2", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_CLKINV_1128 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_0_DXMUX : X_BUF generic map( LOC => "SLICE_X28Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0007, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_0_DXMUX_1129 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_0_YUSED : X_BUF generic map( LOC => "SLICE_X28Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1_O_pack_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1_O ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_0_CLKINV : X_BUF generic map( LOC => "SLICE_X28Y13", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_0_CLKINV_1130 ); FSM_GPIF_v_setup_0_DXMUX : X_BUF generic map( LOC => "SLICE_X36Y4", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_Mcount_v_setup_eqn_0_1132, O => FSM_GPIF_v_setup_0_DXMUX_1131 ); FSM_GPIF_v_setup_0_YUSED : X_BUF generic map( LOC => "SLICE_X36Y4", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_Mcount_v_setup_eqn_3_map0_pack_1, O => FSM_GPIF_Mcount_v_setup_eqn_3_map0 ); FSM_GPIF_v_setup_0_CLKINV : X_BUF generic map( LOC => "SLICE_X36Y4", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => FSM_GPIF_v_setup_0_CLKINV_1133 ); FSM_GPIF_v_setup_0_CEINV : X_BUF generic map( LOC => "SLICE_X36Y4", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_v_setup_not0001_0, O => FSM_GPIF_v_setup_0_CEINV_1134 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_0_DXMUX : X_BUF generic map( LOC => "SLICE_X43Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0007, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_0_DXMUX_1135 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_0_YUSED : X_BUF generic map( LOC => "SLICE_X43Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1_O_pack_1, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1_O ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_0_CLKINV : X_BUF generic map( LOC => "SLICE_X43Y6", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_0_CLKINV_1136 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_DXMUX : X_BUF generic map( LOC => "SLICE_X26Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0007, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_DXMUX_1137 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_YUSED : X_BUF generic map( LOC => "SLICE_X26Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1_O_pack_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1_O ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_CLKINV : X_BUF generic map( LOC => "SLICE_X26Y2", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_CLKINV_1138 ); FSM_GPIF_pr_state_FFd2_DXMUX : X_BUF generic map( LOC => "SLICE_X36Y10", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_FFd2_In, O => FSM_GPIF_pr_state_FFd2_DXMUX_1139 ); FSM_GPIF_pr_state_FFd2_YUSED : X_BUF generic map( LOC => "SLICE_X36Y10", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_FFd2_In5_O_pack_1, O => FSM_GPIF_pr_state_FFd2_In5_O ); FSM_GPIF_pr_state_FFd2_CLKINV : X_BUF generic map( LOC => "SLICE_X36Y10", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => FSM_GPIF_pr_state_FFd2_CLKINV_1140 ); FSM_GPIF_pr_state_FFd2_CEINV : X_BUF generic map( LOC => "SLICE_X36Y10", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_not0001_0, O => FSM_GPIF_pr_state_FFd2_CEINV_1141 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_DYMUX : X_BUF generic map( LOC => "SLICE_X29Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0006, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_DYMUX_1142 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_CLKINV : X_BUF generic map( LOC => "SLICE_X29Y13", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_CLKINV_1143 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_2_DYMUX : X_BUF generic map( LOC => "SLICE_X43Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0006, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_2_DYMUX_1144 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_2_CLKINV : X_BUF generic map( LOC => "SLICE_X43Y5", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_2_CLKINV_1145 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_DXMUX : X_BUF generic map( LOC => "SLICE_X28Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0004, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_DXMUX_1146 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_DYMUX : X_BUF generic map( LOC => "SLICE_X28Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0005, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_DYMUX_1147 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_SRINV : X_BUF generic map( LOC => "SLICE_X28Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_SRINV_1148 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_CLKINV : X_BUF generic map( LOC => "SLICE_X28Y12", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_CLKINV_1149 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00051 : X_LUT4 generic map( INIT => X"6996", LOC => "SLICE_X28Y12" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(4), ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(3), ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0005 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DXMUX : X_BUF generic map( LOC => "SLICE_X42Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0004, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DXMUX_1150 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DYMUX : X_BUF generic map( LOC => "SLICE_X42Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0005, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DYMUX_1151 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_SRINV : X_BUF generic map( LOC => "SLICE_X42Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_SRINV_1152 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_CLKINV : X_BUF generic map( LOC => "SLICE_X42Y3", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_CLKINV_1153 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00051 : X_LUT4 generic map( INIT => X"6996", LOC => "SLICE_X42Y3" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(5), ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(4), ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(3), ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0005 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DXMUX : X_BUF generic map( LOC => "SLICE_X29Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0003, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DXMUX_1154 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DYMUX : X_BUF generic map( LOC => "SLICE_X29Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_GYMUX_1156, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DYMUX_1155 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_YUSED : X_BUF generic map( LOC => "SLICE_X29Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_GYMUX_1156, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_GYMUX : X_BUF generic map( LOC => "SLICE_X29Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002_pack_1, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_GYMUX_1156 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_SRINV : X_BUF generic map( LOC => "SLICE_X29Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_SRINV_1157 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_CLKINV : X_BUF generic map( LOC => "SLICE_X29Y12", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_CLKINV_1158 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00021 : X_LUT4 generic map( INIT => X"6996", LOC => "SLICE_X29Y12" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(7), ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(6), ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(5), ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(8), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002_pack_1 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_DXMUX : X_BUF generic map( LOC => "SLICE_X44Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0003, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_DXMUX_1159 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_DYMUX : X_BUF generic map( LOC => "SLICE_X44Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_GYMUX_1161, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_DYMUX_1160 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_YUSED : X_BUF generic map( LOC => "SLICE_X44Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_GYMUX_1161, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_GYMUX : X_BUF generic map( LOC => "SLICE_X44Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002_pack_1, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_GYMUX_1161 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_SRINV : X_BUF generic map( LOC => "SLICE_X44Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_SRINV_1162 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_CLKINV : X_BUF generic map( LOC => "SLICE_X44Y2", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_CLKINV_1163 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00021 : X_LUT4 generic map( INIT => X"6996", LOC => "SLICE_X44Y2" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(7), ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(9), ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(8), ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(6), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002_pack_1 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_DXMUX : X_BUF generic map( LOC => "SLICE_X30Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0000, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_DXMUX_1164 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_DYMUX : X_BUF generic map( LOC => "SLICE_X30Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0001, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_DYMUX_1165 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_SRINV : X_BUF generic map( LOC => "SLICE_X30Y15", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_SRINV_1166 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_CLKINV : X_BUF generic map( LOC => "SLICE_X30Y15", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_CLKINV_1167 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00011 : X_LUT4 generic map( INIT => X"A55A", LOC => "SLICE_X30Y15" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(7), ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(8), ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(6), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0001 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_DXMUX : X_BUF generic map( LOC => "SLICE_X44Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0000, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_DXMUX_1168 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_DYMUX : X_BUF generic map( LOC => "SLICE_X44Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0001, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_DYMUX_1169 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_SRINV : X_BUF generic map( LOC => "SLICE_X44Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_SRINV_1170 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_CLKINV : X_BUF generic map( LOC => "SLICE_X44Y3", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_CLKINV_1171 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00011 : X_LUT4 generic map( INIT => X"A55A", LOC => "SLICE_X44Y3" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(7), ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(8), ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(9), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0001 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_DXMUX : X_BUF generic map( LOC => "SLICE_X50Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0006, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_DXMUX_1172 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_DYMUX : X_BUF generic map( LOC => "SLICE_X50Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0007, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_DYMUX_1173 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_SRINV : X_BUF generic map( LOC => "SLICE_X50Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_SRINV_1174 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_CLKINV : X_BUF generic map( LOC => "SLICE_X50Y10", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_CLKINV_1175 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0007_Result1 : X_LUT4 generic map( INIT => X"3C3C", LOC => "SLICE_X50Y10" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(0), ADR2 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(1), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0007 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_DXMUX : X_BUF generic map( LOC => "SLICE_X14Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0006, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_DXMUX_1176 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_DYMUX : X_BUF generic map( LOC => "SLICE_X14Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0007, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_DYMUX_1177 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_SRINV : X_BUF generic map( LOC => "SLICE_X14Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_SRINV_1178 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_CLKINV : X_BUF generic map( LOC => "SLICE_X14Y4", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_CLKINV_1179 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0007_Result1 : X_LUT4 generic map( INIT => X"3C3C", LOC => "SLICE_X14Y4" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(1), ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(2), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0007 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_DXMUX : X_BUF generic map( LOC => "SLICE_X52Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0004, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_DXMUX_1180 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_DYMUX : X_BUF generic map( LOC => "SLICE_X52Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0005, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_DYMUX_1181 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_SRINV : X_BUF generic map( LOC => "SLICE_X52Y10", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_SRINV_1182 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_CLKINV : X_BUF generic map( LOC => "SLICE_X52Y10", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_CLKINV_1183 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0005_Result1 : X_LUT4 generic map( INIT => X"55AA", LOC => "SLICE_X52Y10" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(2), ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0005 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_DXMUX : X_BUF generic map( LOC => "SLICE_X14Y11", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0004, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_DXMUX_1184 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_DYMUX : X_BUF generic map( LOC => "SLICE_X14Y11", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0005, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_DYMUX_1185 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_SRINV : X_BUF generic map( LOC => "SLICE_X14Y11", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_SRINV_1186 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_CLKINV : X_BUF generic map( LOC => "SLICE_X14Y11", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_CLKINV_1187 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0005_Result1 : X_LUT4 generic map( INIT => X"6666", LOC => "SLICE_X14Y11" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(4), ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(3), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0005 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_DXMUX : X_BUF generic map( LOC => "SLICE_X52Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0002, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_DXMUX_1188 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_DYMUX : X_BUF generic map( LOC => "SLICE_X52Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0003, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_DYMUX_1189 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_SRINV : X_BUF generic map( LOC => "SLICE_X52Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_SRINV_1190 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_CLKINV : X_BUF generic map( LOC => "SLICE_X52Y11", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_CLKINV_1191 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0003_Result1 : X_LUT4 generic map( INIT => X"33CC", LOC => "SLICE_X52Y11" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(4), ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(5), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0003 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_DXMUX : X_BUF generic map( LOC => "SLICE_X15Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0002, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_DXMUX_1192 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_DYMUX : X_BUF generic map( LOC => "SLICE_X15Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0003, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_DYMUX_1193 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_SRINV : X_BUF generic map( LOC => "SLICE_X15Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_SRINV_1194 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_CLKINV : X_BUF generic map( LOC => "SLICE_X15Y10", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_CLKINV_1195 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0003_Result1 : X_LUT4 generic map( INIT => X"3C3C", LOC => "SLICE_X15Y10" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(6), ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(5), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0003 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_DXMUX : X_BUF generic map( LOC => "SLICE_X53Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0000, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_DXMUX_1196 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_DYMUX : X_BUF generic map( LOC => "SLICE_X53Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0001, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_DYMUX_1197 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_SRINV : X_BUF generic map( LOC => "SLICE_X53Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_SRINV_1198 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_CLKINV : X_BUF generic map( LOC => "SLICE_X53Y8", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_CLKINV_1199 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0001_Result1 : X_LUT4 generic map( INIT => X"6666", LOC => "SLICE_X53Y8" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(7), ADR1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(6), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0001 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_DXMUX : X_BUF generic map( LOC => "SLICE_X15Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0000, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_DXMUX_1200 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_DYMUX : X_BUF generic map( LOC => "SLICE_X15Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0001, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_DYMUX_1201 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_SRINV : X_BUF generic map( LOC => "SLICE_X15Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_SRINV_1202 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_CLKINV : X_BUF generic map( LOC => "SLICE_X15Y8", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_CLKINV_1203 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0001_Result1 : X_LUT4 generic map( INIT => X"33CC", LOC => "SLICE_X15Y8" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(8), ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(7), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0001 ); s_X2U_AM_FULL_XUSED : X_BUF generic map( LOC => "SLICE_X28Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0 ); s_X2U_AM_FULL_DYMUX : X_BUF generic map( LOC => "SLICE_X28Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_almost_full_i_or0000, O => s_X2U_AM_FULL_DYMUX_1204 ); s_X2U_AM_FULL_CLKINV : X_BUF generic map( LOC => "SLICE_X28Y6", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => s_X2U_AM_FULL_CLKINV_1205 ); s_X2U_AM_FULL_CEINV : X_INV generic map( LOC => "SLICE_X28Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_full, O => s_X2U_AM_FULL_CEINVNOT ); s_U2X_AM_FULL_DYMUX : X_BUF generic map( LOC => "SLICE_X30Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_almost_full_i_or0000, O => s_U2X_AM_FULL_DYMUX_1206 ); s_U2X_AM_FULL_CLKINV : X_BUF generic map( LOC => "SLICE_X30Y16", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => s_U2X_AM_FULL_CLKINV_1207 ); s_U2X_AM_FULL_CEINV : X_INV generic map( LOC => "SLICE_X30Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_full, O => s_U2X_AM_FULL_CEINVNOT ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_DYMUX : X_BUF generic map( LOC => "SLICE_X42Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0006, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_DYMUX_1208 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_CLKINV : X_BUF generic map( LOC => "SLICE_X42Y7", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_CLKINV_1209 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_DXMUX : X_BUF generic map( LOC => "SLICE_X41Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0004, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_DXMUX_1210 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_DYMUX : X_BUF generic map( LOC => "SLICE_X41Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0005, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_DYMUX_1211 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_SRINV : X_BUF generic map( LOC => "SLICE_X41Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_SRINV_1212 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_CLKINV : X_BUF generic map( LOC => "SLICE_X41Y6", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_CLKINV_1213 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00051 : X_LUT4 generic map( INIT => X"6996", LOC => "SLICE_X41Y6" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(3), ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002, ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(4), ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(2), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0005 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_2_DYMUX : X_BUF generic map( LOC => "SLICE_X27Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0006, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_2_DYMUX_1214 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_2_CLKINV : X_BUF generic map( LOC => "SLICE_X27Y2", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_2_CLKINV_1215 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DXMUX : X_BUF generic map( LOC => "SLICE_X27Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0004, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DXMUX_1216 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DYMUX : X_BUF generic map( LOC => "SLICE_X27Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0005, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DYMUX_1217 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_SRINV : X_BUF generic map( LOC => "SLICE_X27Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_SRINV_1218 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_CLKINV : X_BUF generic map( LOC => "SLICE_X27Y3", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_CLKINV_1219 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00051 : X_LUT4 generic map( INIT => X"6996", LOC => "SLICE_X27Y3" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(3), ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(4), ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(5), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0005 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DXMUX : X_BUF generic map( LOC => "SLICE_X40Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0003, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DXMUX_1220 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DYMUX : X_BUF generic map( LOC => "SLICE_X40Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_GYMUX_1222, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DYMUX_1221 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_YUSED : X_BUF generic map( LOC => "SLICE_X40Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_GYMUX_1222, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_GYMUX : X_BUF generic map( LOC => "SLICE_X40Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002_pack_1, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_GYMUX_1222 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_SRINV : X_BUF generic map( LOC => "SLICE_X40Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_SRINV_1223 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_CLKINV : X_BUF generic map( LOC => "SLICE_X40Y7", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_CLKINV_1224 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00021 : X_LUT4 generic map( INIT => X"6996", LOC => "SLICE_X40Y7" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(7), ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(5), ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(8), ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(6), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002_pack_1 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_DXMUX : X_BUF generic map( LOC => "SLICE_X40Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0000, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_DXMUX_1225 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_DYMUX : X_BUF generic map( LOC => "SLICE_X40Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0001, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_DYMUX_1226 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_SRINV : X_BUF generic map( LOC => "SLICE_X40Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_SRINV_1227 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_CLKINV : X_BUF generic map( LOC => "SLICE_X40Y6", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_CLKINV_1228 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00011 : X_LUT4 generic map( INIT => X"A55A", LOC => "SLICE_X40Y6" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(7), ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(8), ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(6), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0001 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0003, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_DXMUX_1229 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_DYMUX : X_BUF generic map( LOC => "SLICE_X24Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_GYMUX_1231, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_DYMUX_1230 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_YUSED : X_BUF generic map( LOC => "SLICE_X24Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_GYMUX_1231, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_GYMUX : X_BUF generic map( LOC => "SLICE_X24Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002_pack_1, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_GYMUX_1231 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_SRINV : X_BUF generic map( LOC => "SLICE_X24Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_SRINV_1232 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_CLKINV : X_BUF generic map( LOC => "SLICE_X24Y5", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_CLKINV_1233 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00021 : X_LUT4 generic map( INIT => X"6996", LOC => "SLICE_X24Y5" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(7), ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(9), ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(8), ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(6), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002_pack_1 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_DXMUX : X_BUF generic map( LOC => "SLICE_X25Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0000, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_DXMUX_1234 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_DYMUX : X_BUF generic map( LOC => "SLICE_X25Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0001, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_DYMUX_1235 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_SRINV : X_BUF generic map( LOC => "SLICE_X25Y3", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_SRINV_1236 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_CLKINV : X_BUF generic map( LOC => "SLICE_X25Y3", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_CLKINV_1237 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00011 : X_LUT4 generic map( INIT => X"9696", LOC => "SLICE_X25Y3" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(7), ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(8), ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(9), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0001 ); FSM_GPIF_v_setup_1_XUSED : X_BUF generic map( LOC => "SLICE_X38Y7", PATHPULSE => 757 ps ) port map ( I => N120, O => N120_0 ); FSM_GPIF_v_setup_1_DYMUX : X_BUF generic map( LOC => "SLICE_X38Y7", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_Mcount_v_setup_eqn_1_1239, O => FSM_GPIF_v_setup_1_DYMUX_1238 ); FSM_GPIF_v_setup_1_CLKINV : X_BUF generic map( LOC => "SLICE_X38Y7", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => FSM_GPIF_v_setup_1_CLKINV_1240 ); FSM_GPIF_v_setup_1_CEINV : X_BUF generic map( LOC => "SLICE_X38Y7", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_v_setup_not0001_0, O => FSM_GPIF_v_setup_1_CEINV_1241 ); s_U2X_AM_EMPTY_XUSED : X_BUF generic map( LOC => "SLICE_X25Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en, O => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en_0 ); s_U2X_AM_EMPTY_DYMUX : X_BUF generic map( LOC => "SLICE_X25Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_almost_empty_i_or0000, O => s_U2X_AM_EMPTY_DYMUX_1242 ); s_U2X_AM_EMPTY_CLKINV : X_BUF generic map( LOC => "SLICE_X25Y5", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => s_U2X_AM_EMPTY_CLKINV_1243 ); s_U2X_AM_EMPTY_CEINV : X_INV generic map( LOC => "SLICE_X25Y5", PATHPULSE => 757 ps ) port map ( I => s_U2X_EMPTY, O => s_U2X_AM_EMPTY_CEINVNOT ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_DXMUX : X_BUF generic map( LOC => "SLICE_X25Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0006, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_DXMUX_1244 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_DYMUX : X_BUF generic map( LOC => "SLICE_X25Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0007, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_DYMUX_1245 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_SRINV : X_BUF generic map( LOC => "SLICE_X25Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_SRINV_1246 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_CLKINV : X_BUF generic map( LOC => "SLICE_X25Y4", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_CLKINV_1247 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0007_Result1 : X_LUT4 generic map( INIT => X"5A5A", LOC => "SLICE_X25Y4" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(0), ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(1), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0007 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_DXMUX : X_BUF generic map( LOC => "SLICE_X50Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0006, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_DXMUX_1248 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_DYMUX : X_BUF generic map( LOC => "SLICE_X50Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0007, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_DYMUX_1249 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_SRINV : X_BUF generic map( LOC => "SLICE_X50Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_SRINV_1250 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_CLKINV : X_BUF generic map( LOC => "SLICE_X50Y2", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_CLKINV_1251 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0007_Result1 : X_LUT4 generic map( INIT => X"55AA", LOC => "SLICE_X50Y2" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(2), ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(1), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0007 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_DXMUX : X_BUF generic map( LOC => "SLICE_X25Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0004, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_DXMUX_1252 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_DYMUX : X_BUF generic map( LOC => "SLICE_X25Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0005, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_DYMUX_1253 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_SRINV : X_BUF generic map( LOC => "SLICE_X25Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_SRINV_1254 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_CLKINV : X_BUF generic map( LOC => "SLICE_X25Y8", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_CLKINV_1255 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0005_Result1 : X_LUT4 generic map( INIT => X"33CC", LOC => "SLICE_X25Y8" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(3), ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0005 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_DXMUX : X_BUF generic map( LOC => "SLICE_X51Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0004, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_DXMUX_1256 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_DYMUX : X_BUF generic map( LOC => "SLICE_X51Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0005, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_DYMUX_1257 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_SRINV : X_BUF generic map( LOC => "SLICE_X51Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_SRINV_1258 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_CLKINV : X_BUF generic map( LOC => "SLICE_X51Y3", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_CLKINV_1259 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0005_Result1 : X_LUT4 generic map( INIT => X"55AA", LOC => "SLICE_X51Y3" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(3), ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0005 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_DXMUX : X_BUF generic map( LOC => "SLICE_X27Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0002, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_DXMUX_1260 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_DYMUX : X_BUF generic map( LOC => "SLICE_X27Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0003, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_DYMUX_1261 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_SRINV : X_BUF generic map( LOC => "SLICE_X27Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_SRINV_1262 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_CLKINV : X_BUF generic map( LOC => "SLICE_X27Y8", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_CLKINV_1263 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0003_Result1 : X_LUT4 generic map( INIT => X"0FF0", LOC => "SLICE_X27Y8" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(5), ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0003 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_DXMUX : X_BUF generic map( LOC => "SLICE_X52Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0002, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_DXMUX_1264 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_DYMUX : X_BUF generic map( LOC => "SLICE_X52Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0003, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_DYMUX_1265 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_SRINV : X_BUF generic map( LOC => "SLICE_X52Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_SRINV_1266 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_CLKINV : X_BUF generic map( LOC => "SLICE_X52Y2", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_CLKINV_1267 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0003_Result1 : X_LUT4 generic map( INIT => X"33CC", LOC => "SLICE_X52Y2" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(5), ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(6), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0003 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y11", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0000, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_DXMUX_1268 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_DYMUX : X_BUF generic map( LOC => "SLICE_X24Y11", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0001, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_DYMUX_1269 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_SRINV : X_BUF generic map( LOC => "SLICE_X24Y11", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_SRINV_1270 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_CLKINV : X_BUF generic map( LOC => "SLICE_X24Y11", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_CLKINV_1271 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0001_Result1 : X_LUT4 generic map( INIT => X"5A5A", LOC => "SLICE_X24Y11" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(6), ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(7), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0001 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_DXMUX : X_BUF generic map( LOC => "SLICE_X53Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0000, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_DXMUX_1272 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_DYMUX : X_BUF generic map( LOC => "SLICE_X53Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0001, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_DYMUX_1273 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_SRINV : X_BUF generic map( LOC => "SLICE_X53Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_SRINV_1274 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_CLKINV : X_BUF generic map( LOC => "SLICE_X53Y7", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_CLKINV_1275 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0001_Result1 : X_LUT4 generic map( INIT => X"33CC", LOC => "SLICE_X53Y7" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(8), ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(7), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0001 ); s_X2U_EMPTY_XUSED : X_BUF generic map( LOC => "SLICE_X35Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0 ); s_X2U_EMPTY_DYMUX : X_BUF generic map( LOC => "SLICE_X35Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_EMPTY_NONREG, O => s_X2U_EMPTY_DYMUX_1276 ); s_X2U_EMPTY_CLKINV : X_BUF generic map( LOC => "SLICE_X35Y6", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => s_X2U_EMPTY_CLKINV_1277 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_EMPTY_NONREG_i1 : X_LUT4 generic map( INIT => X"FF08", LOC => "SLICE_X35Y6" ) port map ( ADR0 => s_X2U_RD_EN, ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out, ADR2 => s_X2U_EMPTY, ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_EMPTY_NONREG ); Loopback_pr_stateLoop_FFd3_XUSED : X_BUF generic map( LOC => "SLICE_X29Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0 ); Loopback_pr_stateLoop_FFd3_DYMUX : X_BUF generic map( LOC => "SLICE_X29Y7", PATHPULSE => 757 ps ) port map ( I => N333, O => Loopback_pr_stateLoop_FFd3_DYMUX_1278 ); Loopback_pr_stateLoop_FFd3_CLKINV : X_BUF generic map( LOC => "SLICE_X29Y7", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_pr_stateLoop_FFd3_CLKINV_1279 ); Loopback_pr_stateLoop_FFd3_CEINV : X_BUF generic map( LOC => "SLICE_X29Y7", PATHPULSE => 757 ps ) port map ( I => Loopback_pr_stateLoop_FFd2_9, O => Loopback_pr_stateLoop_FFd3_CEINV_1280 ); F_IN_full_DYMUX : X_BUF generic map( LOC => "SLICE_X26Y17", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG, O => F_IN_full_DYMUX_1281 ); F_IN_full_CLKINV : X_BUF generic map( LOC => "SLICE_X26Y17", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_full_CLKINV_1282 ); o_LEDrx_OBUF_YUSED : X_BUF generic map( LOC => "SLICE_X37Y11", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_FFd3_In_map22, O => FSM_GPIF_pr_state_FFd3_In_map22_0 ); FSM_GPIF_pr_state_FFd3_In67 : X_LUT4 generic map( INIT => X"5400", LOC => "SLICE_X37Y11" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd2_10, ADR1 => i_RDYU_IBUF_3, ADR2 => FSM_GPIF_pr_state_FFd4_6, ADR3 => FSM_GPIF_pr_state_FFd3_7, O => FSM_GPIF_pr_state_FFd3_In_map22 ); FSM_GPIF_o_RDYX_map9_XUSED : X_BUF generic map( LOC => "SLICE_X37Y10", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_o_RDYX_map9, O => FSM_GPIF_o_RDYX_map9_0 ); FSM_GPIF_o_RDYX_map9_YUSED : X_BUF generic map( LOC => "SLICE_X37Y10", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_FFd3_In_map18, O => FSM_GPIF_pr_state_FFd3_In_map18_0 ); FSM_GPIF_pr_state_FFd3_In59 : X_LUT4 generic map( INIT => X"C0F4", LOC => "SLICE_X37Y10" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd1_5, ADR1 => s_U2X_AM_FULL, ADR2 => FSM_GPIF_pr_state_FFd2_10, ADR3 => FSM_GPIF_pr_state_FFd3_7, O => FSM_GPIF_pr_state_FFd3_In_map18 ); Loopback_o_X2U_DATA_1_DXMUX : X_BUF generic map( LOC => "SLICE_X4Y1", PATHPULSE => 757 ps ) port map ( I => s_opb_in(1), O => Loopback_o_X2U_DATA_1_DXMUX_1284 ); Loopback_o_X2U_DATA_1_DYMUX : X_BUF generic map( LOC => "SLICE_X4Y1", PATHPULSE => 757 ps ) port map ( I => s_opb_in(0), O => Loopback_o_X2U_DATA_1_DYMUX_1285 ); Loopback_o_X2U_DATA_1_CLKINV : X_BUF generic map( LOC => "SLICE_X4Y1", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_1_CLKINV_1286 ); Loopback_o_X2U_DATA_3_DXMUX : X_BUF generic map( LOC => "SLICE_X5Y1", PATHPULSE => 757 ps ) port map ( I => s_opb_in(3), O => Loopback_o_X2U_DATA_3_DXMUX_1287 ); Loopback_o_X2U_DATA_3_DYMUX : X_BUF generic map( LOC => "SLICE_X5Y1", PATHPULSE => 757 ps ) port map ( I => s_opb_in(2), O => Loopback_o_X2U_DATA_3_DYMUX_1288 ); Loopback_o_X2U_DATA_3_CLKINV : X_BUF generic map( LOC => "SLICE_X5Y1", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_3_CLKINV_1289 ); Loopback_o_X2U_DATA_5_DXMUX : X_BUF generic map( LOC => "SLICE_X4Y3", PATHPULSE => 757 ps ) port map ( I => s_opb_in(5), O => Loopback_o_X2U_DATA_5_DXMUX_1290 ); Loopback_o_X2U_DATA_5_DYMUX : X_BUF generic map( LOC => "SLICE_X4Y3", PATHPULSE => 757 ps ) port map ( I => s_opb_in(4), O => Loopback_o_X2U_DATA_5_DYMUX_1291 ); Loopback_o_X2U_DATA_5_CLKINV : X_BUF generic map( LOC => "SLICE_X4Y3", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_5_CLKINV_1292 ); Loopback_o_X2U_DATA_7_DXMUX : X_BUF generic map( LOC => "SLICE_X5Y3", PATHPULSE => 757 ps ) port map ( I => s_opb_in(7), O => Loopback_o_X2U_DATA_7_DXMUX_1293 ); Loopback_o_X2U_DATA_7_DYMUX : X_BUF generic map( LOC => "SLICE_X5Y3", PATHPULSE => 757 ps ) port map ( I => s_opb_in(6), O => Loopback_o_X2U_DATA_7_DYMUX_1294 ); Loopback_o_X2U_DATA_7_CLKINV : X_BUF generic map( LOC => "SLICE_X5Y3", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_7_CLKINV_1295 ); Loopback_o_X2U_DATA_9_DXMUX : X_BUF generic map( LOC => "SLICE_X4Y5", PATHPULSE => 757 ps ) port map ( I => s_opb_in(9), O => Loopback_o_X2U_DATA_9_DXMUX_1296 ); Loopback_o_X2U_DATA_9_DYMUX : X_BUF generic map( LOC => "SLICE_X4Y5", PATHPULSE => 757 ps ) port map ( I => s_opb_in(8), O => Loopback_o_X2U_DATA_9_DYMUX_1297 ); Loopback_o_X2U_DATA_9_CLKINV : X_BUF generic map( LOC => "SLICE_X4Y5", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_9_CLKINV_1298 ); FSM_GPIF_pr_state_FFd4_In_map30_XUSED : X_BUF generic map( LOC => "SLICE_X34Y10", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_FFd4_In_map30, O => FSM_GPIF_pr_state_FFd4_In_map30_0 ); FSM_GPIF_pr_state_FFd4_In_map30_YUSED : X_BUF generic map( LOC => "SLICE_X34Y10", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_FFd4_In_map29_pack_1, O => FSM_GPIF_pr_state_FFd4_In_map29 ); FSM_GPIF_pr_state_FFd4_In96 : X_LUT4 generic map( INIT => X"0C0C", LOC => "SLICE_X34Y10" ) port map ( ADR0 => VCC, ADR1 => i_WRU_IBUF_2, ADR2 => i_RDYU_IBUF_3, ADR3 => VCC, O => FSM_GPIF_pr_state_FFd4_In_map29_pack_1 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_DYMUX : X_BUF generic map( LOC => "SLICE_X32Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_11, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_DYMUX_1299 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_CLKINV : X_BUF generic map( LOC => "SLICE_X32Y11", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_CLKINV_1300 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_DYMUX : X_BUF generic map( LOC => "SLICE_X22Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_12, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_DYMUX_1301 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_CLKINV : X_BUF generic map( LOC => "SLICE_X22Y12", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_CLKINV_1302 ); N124_XUSED : X_BUF generic map( LOC => "SLICE_X38Y8", PATHPULSE => 757 ps ) port map ( I => N124, O => N124_0 ); N124_YUSED : X_BUF generic map( LOC => "SLICE_X38Y8", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_Mcount_v_setup_eqn_3_map16, O => FSM_GPIF_Mcount_v_setup_eqn_3_map16_0 ); FSM_GPIF_Mcount_v_setup_eqn_352 : X_LUT4 generic map( INIT => X"0202", LOC => "SLICE_X38Y8" ) port map ( ADR0 => FSM_GPIF_v_setup(3), ADR1 => FSM_GPIF_v_setup(1), ADR2 => FSM_GPIF_v_setup(2), ADR3 => VCC, O => FSM_GPIF_Mcount_v_setup_eqn_3_map16 ); N350_XUSED : X_BUF generic map( LOC => "SLICE_X38Y10", PATHPULSE => 757 ps ) port map ( I => N350, O => N350_0 ); N350_YUSED : X_BUF generic map( LOC => "SLICE_X38Y10", PATHPULSE => 757 ps ) port map ( I => s_FIFOrst, O => s_FIFOrst_0 ); FSM_GPIF_pr_state_Out11 : X_LUT4 generic map( INIT => X"0001", LOC => "SLICE_X38Y10" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd3_7, ADR1 => FSM_GPIF_pr_state_FFd1_5, ADR2 => FSM_GPIF_pr_state_FFd4_6, ADR3 => FSM_GPIF_pr_state_FFd2_10, O => s_FIFOrst ); FSM_GPIF_pr_state_FFd2_In_map8_XUSED : X_BUF generic map( LOC => "SLICE_X33Y10", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_FFd2_In_map8, O => FSM_GPIF_pr_state_FFd2_In_map8_0 ); FSM_GPIF_pr_state_Out61 : X_LUT4 generic map( INIT => X"3030", LOC => "SLICE_X33Y10" ) port map ( ADR0 => VCC, ADR1 => FSM_GPIF_pr_state_FFd4_6, ADR2 => FSM_GPIF_pr_state_FFd1_5, ADR3 => VCC, O => o_LEDtx_OBUF_1303 ); FSM_GPIF_o_RDYX_map19_XUSED : X_BUF generic map( LOC => "SLICE_X32Y10", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_o_RDYX_map19, O => FSM_GPIF_o_RDYX_map19_0 ); FSM_GPIF_pr_state_Out91 : X_LUT4 generic map( INIT => X"FFFE", LOC => "SLICE_X32Y10" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd3_7, ADR1 => FSM_GPIF_pr_state_FFd2_10, ADR2 => FSM_GPIF_pr_state_FFd4_6, ADR3 => FSM_GPIF_pr_state_FFd1_5, O => o_LEDrun_OBUF_1304 ); FSM_GPIF_pr_state_FFd1_DXMUX : X_BUF generic map( LOC => "SLICE_X37Y5", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_FFd1_In_1306, O => FSM_GPIF_pr_state_FFd1_DXMUX_1305 ); FSM_GPIF_pr_state_FFd1_YUSED : X_BUF generic map( LOC => "SLICE_X37Y5", PATHPULSE => 757 ps ) port map ( I => N89_pack_1, O => N89 ); FSM_GPIF_pr_state_FFd1_CLKINV : X_BUF generic map( LOC => "SLICE_X37Y5", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => FSM_GPIF_pr_state_FFd1_CLKINV_1307 ); FSM_GPIF_pr_state_FFd1_CEINV : X_BUF generic map( LOC => "SLICE_X37Y5", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_not0001_0, O => FSM_GPIF_pr_state_FFd1_CEINV_1308 ); FSM_GPIF_s_bus_trans_dir_inv_XUSED : X_BUF generic map( LOC => "SLICE_X38Y0", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv, O => FSM_GPIF_s_bus_trans_dir_inv_0 ); FSM_GPIF_s_bus_trans_dir_inv_YUSED : X_BUF generic map( LOC => "SLICE_X38Y0", PATHPULSE => 757 ps ) port map ( I => N90, O => N90_0 ); FSM_GPIF_pr_state_FFd1_In_SW1 : X_LUT4 generic map( INIT => X"8F8E", LOC => "SLICE_X38Y0" ) port map ( ADR0 => i_WRU_IBUF_2, ADR1 => i_RDYU_IBUF_3, ADR2 => FSM_GPIF_pr_state_FFd1_5, ADR3 => FSM_GPIF_pr_state_FFd2_10, O => N90 ); Loopback_o_X2U_DATA_11_DXMUX : X_BUF generic map( LOC => "SLICE_X5Y4", PATHPULSE => 757 ps ) port map ( I => s_opb_in(11), O => Loopback_o_X2U_DATA_11_DXMUX_1309 ); Loopback_o_X2U_DATA_11_DYMUX : X_BUF generic map( LOC => "SLICE_X5Y4", PATHPULSE => 757 ps ) port map ( I => s_opb_in(10), O => Loopback_o_X2U_DATA_11_DYMUX_1310 ); Loopback_o_X2U_DATA_11_CLKINV : X_BUF generic map( LOC => "SLICE_X5Y4", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_11_CLKINV_1311 ); Loopback_o_X2U_DATA_13_DXMUX : X_BUF generic map( LOC => "SLICE_X5Y6", PATHPULSE => 757 ps ) port map ( I => s_opb_in(13), O => Loopback_o_X2U_DATA_13_DXMUX_1312 ); Loopback_o_X2U_DATA_13_DYMUX : X_BUF generic map( LOC => "SLICE_X5Y6", PATHPULSE => 757 ps ) port map ( I => s_opb_in(12), O => Loopback_o_X2U_DATA_13_DYMUX_1313 ); Loopback_o_X2U_DATA_13_CLKINV : X_BUF generic map( LOC => "SLICE_X5Y6", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_13_CLKINV_1314 ); Loopback_o_X2U_DATA_21_DXMUX : X_BUF generic map( LOC => "SLICE_X5Y2", PATHPULSE => 757 ps ) port map ( I => s_opb_in(21), O => Loopback_o_X2U_DATA_21_DXMUX_1315 ); Loopback_o_X2U_DATA_21_DYMUX : X_BUF generic map( LOC => "SLICE_X5Y2", PATHPULSE => 757 ps ) port map ( I => s_opb_in(20), O => Loopback_o_X2U_DATA_21_DYMUX_1316 ); Loopback_o_X2U_DATA_21_CLKINV : X_BUF generic map( LOC => "SLICE_X5Y2", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_21_CLKINV_1317 ); Loopback_o_X2U_DATA_15_DXMUX : X_BUF generic map( LOC => "SLICE_X4Y6", PATHPULSE => 757 ps ) port map ( I => s_opb_in(15), O => Loopback_o_X2U_DATA_15_DXMUX_1318 ); Loopback_o_X2U_DATA_15_DYMUX : X_BUF generic map( LOC => "SLICE_X4Y6", PATHPULSE => 757 ps ) port map ( I => s_opb_in(14), O => Loopback_o_X2U_DATA_15_DYMUX_1319 ); Loopback_o_X2U_DATA_15_CLKINV : X_BUF generic map( LOC => "SLICE_X4Y6", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_15_CLKINV_1320 ); Loopback_o_X2U_DATA_23_DXMUX : X_BUF generic map( LOC => "SLICE_X4Y2", PATHPULSE => 757 ps ) port map ( I => s_opb_in(23), O => Loopback_o_X2U_DATA_23_DXMUX_1321 ); Loopback_o_X2U_DATA_23_DYMUX : X_BUF generic map( LOC => "SLICE_X4Y2", PATHPULSE => 757 ps ) port map ( I => s_opb_in(22), O => Loopback_o_X2U_DATA_23_DYMUX_1322 ); Loopback_o_X2U_DATA_23_CLKINV : X_BUF generic map( LOC => "SLICE_X4Y2", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_23_CLKINV_1323 ); Loopback_o_X2U_DATA_31_DXMUX : X_BUF generic map( LOC => "SLICE_X4Y7", PATHPULSE => 757 ps ) port map ( I => s_opb_in(31), O => Loopback_o_X2U_DATA_31_DXMUX_1324 ); Loopback_o_X2U_DATA_31_DYMUX : X_BUF generic map( LOC => "SLICE_X4Y7", PATHPULSE => 757 ps ) port map ( I => s_opb_in(30), O => Loopback_o_X2U_DATA_31_DYMUX_1325 ); Loopback_o_X2U_DATA_31_CLKINV : X_BUF generic map( LOC => "SLICE_X4Y7", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_31_CLKINV_1326 ); Loopback_o_X2U_DATA_17_DXMUX : X_BUF generic map( LOC => "SLICE_X5Y0", PATHPULSE => 757 ps ) port map ( I => s_opb_in(17), O => Loopback_o_X2U_DATA_17_DXMUX_1327 ); Loopback_o_X2U_DATA_17_DYMUX : X_BUF generic map( LOC => "SLICE_X5Y0", PATHPULSE => 757 ps ) port map ( I => s_opb_in(16), O => Loopback_o_X2U_DATA_17_DYMUX_1328 ); Loopback_o_X2U_DATA_17_CLKINV : X_BUF generic map( LOC => "SLICE_X5Y0", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_17_CLKINV_1329 ); Loopback_o_X2U_DATA_25_DXMUX : X_BUF generic map( LOC => "SLICE_X5Y5", PATHPULSE => 757 ps ) port map ( I => s_opb_in(25), O => Loopback_o_X2U_DATA_25_DXMUX_1330 ); Loopback_o_X2U_DATA_25_DYMUX : X_BUF generic map( LOC => "SLICE_X5Y5", PATHPULSE => 757 ps ) port map ( I => s_opb_in(24), O => Loopback_o_X2U_DATA_25_DYMUX_1331 ); Loopback_o_X2U_DATA_25_CLKINV : X_BUF generic map( LOC => "SLICE_X5Y5", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_25_CLKINV_1332 ); Loopback_o_X2U_DATA_19_DXMUX : X_BUF generic map( LOC => "SLICE_X4Y0", PATHPULSE => 757 ps ) port map ( I => s_opb_in(19), O => Loopback_o_X2U_DATA_19_DXMUX_1333 ); Loopback_o_X2U_DATA_19_DYMUX : X_BUF generic map( LOC => "SLICE_X4Y0", PATHPULSE => 757 ps ) port map ( I => s_opb_in(18), O => Loopback_o_X2U_DATA_19_DYMUX_1334 ); Loopback_o_X2U_DATA_19_CLKINV : X_BUF generic map( LOC => "SLICE_X4Y0", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_19_CLKINV_1335 ); Loopback_o_X2U_DATA_27_DXMUX : X_BUF generic map( LOC => "SLICE_X4Y4", PATHPULSE => 757 ps ) port map ( I => s_opb_in(27), O => Loopback_o_X2U_DATA_27_DXMUX_1336 ); Loopback_o_X2U_DATA_27_DYMUX : X_BUF generic map( LOC => "SLICE_X4Y4", PATHPULSE => 757 ps ) port map ( I => s_opb_in(26), O => Loopback_o_X2U_DATA_27_DYMUX_1337 ); Loopback_o_X2U_DATA_27_CLKINV : X_BUF generic map( LOC => "SLICE_X4Y4", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_27_CLKINV_1338 ); Loopback_o_X2U_DATA_29_DXMUX : X_BUF generic map( LOC => "SLICE_X5Y7", PATHPULSE => 757 ps ) port map ( I => s_opb_in(29), O => Loopback_o_X2U_DATA_29_DXMUX_1339 ); Loopback_o_X2U_DATA_29_DYMUX : X_BUF generic map( LOC => "SLICE_X5Y7", PATHPULSE => 757 ps ) port map ( I => s_opb_in(28), O => Loopback_o_X2U_DATA_29_DYMUX_1340 ); Loopback_o_X2U_DATA_29_CLKINV : X_BUF generic map( LOC => "SLICE_X5Y7", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => Loopback_o_X2U_DATA_29_CLKINV_1341 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_DYMUX : X_BUF generic map( LOC => "SLICE_X30Y17", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(8), O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_DYMUX_1342 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_CLKINV : X_BUF generic map( LOC => "SLICE_X30Y17", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_CLKINV_1343 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_9_DYMUX : X_BUF generic map( LOC => "SLICE_X45Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(9), O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_9_DYMUX_1344 ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_9_CLKINV : X_BUF generic map( LOC => "SLICE_X45Y5", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_9_CLKINV_1345 ); F_OUT_full_DXMUX : X_BUF generic map( LOC => "SLICE_X30Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG, O => F_OUT_full_DXMUX_1346 ); F_OUT_full_YUSED : X_BUF generic map( LOC => "SLICE_X30Y6", PATHPULSE => 757 ps ) port map ( I => s_X2U_WR_EN_pack_1, O => s_X2U_WR_EN ); F_OUT_full_CLKINV : X_BUF generic map( LOC => "SLICE_X30Y6", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_full_CLKINV_1347 ); Loopback_pr_stateLoop_Out11 : X_LUT4 generic map( INIT => X"CC00", LOC => "SLICE_X30Y6" ) port map ( ADR0 => VCC, ADR1 => Loopback_pr_stateLoop_FFd3_8, ADR2 => VCC, ADR3 => Loopback_pr_stateLoop_FFd2_9, O => s_X2U_WR_EN_pack_1 ); F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en_YUSED : X_BUF generic map( LOC => "SLICE_X28Y9", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en, O => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en_0 ); F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en1 : X_LUT4 generic map( INIT => X"F2F2", LOC => "SLICE_X28Y9" ) port map ( ADR0 => s_X2U_RD_EN, ADR1 => s_X2U_EMPTY, ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_DYMUX : X_BUF generic map( LOC => "SLICE_X39Y9", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_DYMUX_1348 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CLKINV : X_BUF generic map( LOC => "SLICE_X39Y9", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CLKINV_1349 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CEINV : X_BUF generic map( LOC => "SLICE_X39Y9", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CEINV_1350 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_DYMUX : X_BUF generic map( LOC => "SLICE_X26Y9", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_DYMUX_1351 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CLKINV : X_BUF generic map( LOC => "SLICE_X26Y9", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CLKINV_1352 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CEINV : X_BUF generic map( LOC => "SLICE_X26Y9", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CEINV_1353 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_DXMUX : X_BUF generic map( LOC => "SLICE_X50Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(1), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_DXMUX_1354 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_DYMUX : X_BUF generic map( LOC => "SLICE_X50Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(0), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_DYMUX_1355 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_SRINV : X_BUF generic map( LOC => "SLICE_X50Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_SRINV_1356 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_CLKINV : X_BUF generic map( LOC => "SLICE_X50Y4", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_CLKINV_1357 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_DXMUX : X_BUF generic map( LOC => "SLICE_X23Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_DXMUX_1358 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_DYMUX : X_BUF generic map( LOC => "SLICE_X23Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_DYMUX_1359 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_SRINV : X_BUF generic map( LOC => "SLICE_X23Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_SRINV_1360 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_CLKINV : X_BUF generic map( LOC => "SLICE_X23Y5", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_CLKINV_1361 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_DXMUX : X_BUF generic map( LOC => "SLICE_X52Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_DXMUX_1362 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_DYMUX : X_BUF generic map( LOC => "SLICE_X52Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(2), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_DYMUX_1363 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_SRINV : X_BUF generic map( LOC => "SLICE_X52Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_SRINV_1364 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_CLKINV : X_BUF generic map( LOC => "SLICE_X52Y7", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_CLKINV_1365 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_DXMUX : X_BUF generic map( LOC => "SLICE_X18Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_DXMUX_1366 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_DYMUX : X_BUF generic map( LOC => "SLICE_X18Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_DYMUX_1367 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_SRINV : X_BUF generic map( LOC => "SLICE_X18Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_SRINV_1368 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_CLKINV : X_BUF generic map( LOC => "SLICE_X18Y10", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_CLKINV_1369 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_DXMUX : X_BUF generic map( LOC => "SLICE_X52Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(5), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_DXMUX_1370 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_DYMUX : X_BUF generic map( LOC => "SLICE_X52Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_DYMUX_1371 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_SRINV : X_BUF generic map( LOC => "SLICE_X52Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_SRINV_1372 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_CLKINV : X_BUF generic map( LOC => "SLICE_X52Y8", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_CLKINV_1373 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_DXMUX : X_BUF generic map( LOC => "SLICE_X22Y11", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(6), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_DXMUX_1374 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_DYMUX : X_BUF generic map( LOC => "SLICE_X22Y11", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(5), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_DYMUX_1375 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_SRINV : X_BUF generic map( LOC => "SLICE_X22Y11", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_SRINV_1376 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_CLKINV : X_BUF generic map( LOC => "SLICE_X22Y11", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_CLKINV_1377 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_DXMUX : X_BUF generic map( LOC => "SLICE_X52Y9", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(7), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_DXMUX_1378 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_DYMUX : X_BUF generic map( LOC => "SLICE_X52Y9", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(6), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_DYMUX_1379 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_SRINV : X_BUF generic map( LOC => "SLICE_X52Y9", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_SRINV_1380 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_CLKINV : X_BUF generic map( LOC => "SLICE_X52Y9", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_CLKINV_1381 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_DXMUX : X_BUF generic map( LOC => "SLICE_X23Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(8), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_DXMUX_1382 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_DYMUX : X_BUF generic map( LOC => "SLICE_X23Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(7), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_DYMUX_1383 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_SRINV : X_BUF generic map( LOC => "SLICE_X23Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_SRINV_1384 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_CLKINV : X_BUF generic map( LOC => "SLICE_X23Y8", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_CLKINV_1385 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_DYMUX : X_BUF generic map( LOC => "SLICE_X52Y13", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(8), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_DYMUX_1386 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_CLKINV : X_BUF generic map( LOC => "SLICE_X52Y13", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_CLKINV_1387 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_9_DYMUX : X_BUF generic map( LOC => "SLICE_X22Y9", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(9), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_9_DYMUX_1388 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_9_CLKINV : X_BUF generic map( LOC => "SLICE_X22Y9", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_9_CLKINV_1389 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_DYMUX : X_BUF generic map( LOC => "SLICE_X32Y8", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_DYMUX_1390 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CLKINV : X_BUF generic map( LOC => "SLICE_X32Y8", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CLKINV_1391 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CEINV : X_BUF generic map( LOC => "SLICE_X32Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CEINV_1392 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_DYMUX : X_BUF generic map( LOC => "SLICE_X22Y13", PATHPULSE => 757 ps ) port map ( I => GLOBAL_LOGIC0, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_DYMUX_1393 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CLKINV : X_BUF generic map( LOC => "SLICE_X22Y13", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CLKINV_1394 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CEINV : X_BUF generic map( LOC => "SLICE_X22Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CEINV_1395 ); F_OUT_BU2_U0_gen_as_fgas_N86_XUSED : X_BUF generic map( LOC => "SLICE_X46Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_N86, O => F_OUT_BU2_U0_gen_as_fgas_N86_0 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW0 : X_LUT4 generic map( INIT => X"3C3C", LOC => "SLICE_X46Y2" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(3), ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(2), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_N86 ); F_IN_BU2_U0_gen_as_fgas_N86_XUSED : X_BUF generic map( LOC => "SLICE_X28Y11", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_N86, O => F_IN_BU2_U0_gen_as_fgas_N86_0 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW0 : X_LUT4 generic map( INIT => X"33CC", LOC => "SLICE_X28Y11" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(1), ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(2), O => F_IN_BU2_U0_gen_as_fgas_N86 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_DYMUX : X_BUF generic map( LOC => "SLICE_X52Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(8), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_DYMUX_1396 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_CLKINV : X_BUF generic map( LOC => "SLICE_X52Y12", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_CLKINV_1397 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_9_DYMUX : X_BUF generic map( LOC => "SLICE_X16Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(9), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_9_DYMUX_1398 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_9_CLKINV : X_BUF generic map( LOC => "SLICE_X16Y8", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_9_CLKINV_1399 ); N30_XUSED : X_BUF generic map( LOC => "SLICE_X39Y4", PATHPULSE => 757 ps ) port map ( I => N30, O => N30_0 ); N30_YUSED : X_BUF generic map( LOC => "SLICE_X39Y4", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_o_RDYX_map2, O => FSM_GPIF_o_RDYX_map2_0 ); FSM_GPIF_o_RDYX3 : X_LUT4 generic map( INIT => X"0FFF", LOC => "SLICE_X39Y4" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => i_WRU_IBUF_2, ADR3 => i_RDYU_IBUF_3, O => FSM_GPIF_o_RDYX_map2 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_DXMUX : X_BUF generic map( LOC => "SLICE_X26Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_DXMUX_1400 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_DYMUX : X_BUF generic map( LOC => "SLICE_X26Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_DYMUX_1401 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_SRINV : X_BUF generic map( LOC => "SLICE_X26Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_SRINV_1402 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_CLKINV : X_BUF generic map( LOC => "SLICE_X26Y7", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_CLKINV_1403 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_DXMUX : X_BUF generic map( LOC => "SLICE_X51Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(2), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_DXMUX_1404 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_DYMUX : X_BUF generic map( LOC => "SLICE_X51Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(1), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_DYMUX_1405 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_SRINV : X_BUF generic map( LOC => "SLICE_X51Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_SRINV_1406 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_CLKINV : X_BUF generic map( LOC => "SLICE_X51Y2", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_CLKINV_1407 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_DYMUX : X_BUF generic map( LOC => "SLICE_X34Y11", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_13, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_DYMUX_1408 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_CLKINV : X_BUF generic map( LOC => "SLICE_X34Y11", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_CLKINV_1409 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_DXMUX : X_BUF generic map( LOC => "SLICE_X26Y11", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_DXMUX_1410 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_DYMUX : X_BUF generic map( LOC => "SLICE_X26Y11", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_DYMUX_1411 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_SRINV : X_BUF generic map( LOC => "SLICE_X26Y11", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_SRINV_1412 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_CLKINV : X_BUF generic map( LOC => "SLICE_X26Y11", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_CLKINV_1413 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_DYMUX : X_BUF generic map( LOC => "SLICE_X27Y9", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_14, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_DYMUX_1414 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_CLKINV : X_BUF generic map( LOC => "SLICE_X27Y9", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_CLKINV_1415 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_DXMUX : X_BUF generic map( LOC => "SLICE_X50Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_DXMUX_1416 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_DYMUX : X_BUF generic map( LOC => "SLICE_X50Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_DYMUX_1417 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_SRINV : X_BUF generic map( LOC => "SLICE_X50Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_SRINV_1418 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_CLKINV : X_BUF generic map( LOC => "SLICE_X50Y3", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_CLKINV_1419 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_DXMUX : X_BUF generic map( LOC => "SLICE_X26Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(5), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_DXMUX_1420 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_DYMUX : X_BUF generic map( LOC => "SLICE_X26Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_DYMUX_1421 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_SRINV : X_BUF generic map( LOC => "SLICE_X26Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_SRINV_1422 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_CLKINV : X_BUF generic map( LOC => "SLICE_X26Y10", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_CLKINV_1423 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_DXMUX : X_BUF generic map( LOC => "SLICE_X52Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(6), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_DXMUX_1424 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_DYMUX : X_BUF generic map( LOC => "SLICE_X52Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(5), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_DYMUX_1425 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_SRINV : X_BUF generic map( LOC => "SLICE_X52Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_SRINV_1426 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_CLKINV : X_BUF generic map( LOC => "SLICE_X52Y3", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_CLKINV_1427 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(7), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_DXMUX_1428 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_DYMUX : X_BUF generic map( LOC => "SLICE_X24Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(6), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_DYMUX_1429 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_SRINV : X_BUF generic map( LOC => "SLICE_X24Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_SRINV_1430 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_CLKINV : X_BUF generic map( LOC => "SLICE_X24Y13", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_CLKINV_1431 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_DXMUX : X_BUF generic map( LOC => "SLICE_X52Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(8), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_DXMUX_1432 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_DYMUX : X_BUF generic map( LOC => "SLICE_X52Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(7), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_DYMUX_1433 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_SRINV : X_BUF generic map( LOC => "SLICE_X52Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_SRINV_1434 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_CLKINV : X_BUF generic map( LOC => "SLICE_X52Y6", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_CLKINV_1435 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_DYMUX : X_BUF generic map( LOC => "SLICE_X25Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(8), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_DYMUX_1436 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_CLKINV : X_BUF generic map( LOC => "SLICE_X25Y12", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_CLKINV_1437 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9_DYMUX : X_BUF generic map( LOC => "SLICE_X49Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(9), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9_DYMUX_1438 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9_CLKINV : X_BUF generic map( LOC => "SLICE_X49Y6", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9_CLKINV_1439 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_DYMUX : X_BUF generic map( LOC => "SLICE_X30Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_13, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_DYMUX_1440 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_CLKINV : X_BUF generic map( LOC => "SLICE_X30Y8", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_CLKINV_1441 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_DYMUX : X_BUF generic map( LOC => "SLICE_X26Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_14, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_DYMUX_1442 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_CLKINV : X_BUF generic map( LOC => "SLICE_X26Y8", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_CLKINV_1443 ); FSM_GPIF_pr_state_not0001_YUSED : X_BUF generic map( LOC => "SLICE_X37Y4", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_pr_state_not0001, O => FSM_GPIF_pr_state_not0001_0 ); FSM_GPIF_pr_state_not00011 : X_LUT4 generic map( INIT => X"FC00", LOC => "SLICE_X37Y4" ) port map ( ADR0 => VCC, ADR1 => FSM_GPIF_v_setup(2), ADR2 => FSM_GPIF_v_setup(1), ADR3 => FSM_GPIF_v_setup(3), O => FSM_GPIF_pr_state_not0001 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_DXMUX : X_BUF generic map( LOC => "SLICE_X47Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(1), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_DXMUX_1444 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_DYMUX : X_BUF generic map( LOC => "SLICE_X47Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(0), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_DYMUX_1445 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_SRINV : X_BUF generic map( LOC => "SLICE_X47Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_SRINV_1446 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_CLKINV : X_BUF generic map( LOC => "SLICE_X47Y5", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_CLKINV_1447 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_DXMUX : X_BUF generic map( LOC => "SLICE_X22Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_DXMUX_1448 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_DYMUX : X_BUF generic map( LOC => "SLICE_X22Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_DYMUX_1449 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_SRINV : X_BUF generic map( LOC => "SLICE_X22Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_SRINV_1450 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_CLKINV : X_BUF generic map( LOC => "SLICE_X22Y5", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_CLKINV_1451 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_DXMUX : X_BUF generic map( LOC => "SLICE_X53Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_DXMUX_1452 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_DYMUX : X_BUF generic map( LOC => "SLICE_X53Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(2), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_DYMUX_1453 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_SRINV : X_BUF generic map( LOC => "SLICE_X53Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_SRINV_1454 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_CLKINV : X_BUF generic map( LOC => "SLICE_X53Y6", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_CLKINV_1455 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_DXMUX : X_BUF generic map( LOC => "SLICE_X23Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_DXMUX_1456 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_DYMUX : X_BUF generic map( LOC => "SLICE_X23Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_DYMUX_1457 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_SRINV : X_BUF generic map( LOC => "SLICE_X23Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_SRINV_1458 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_CLKINV : X_BUF generic map( LOC => "SLICE_X23Y6", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_CLKINV_1459 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_DXMUX : X_BUF generic map( LOC => "SLICE_X47Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(5), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_DXMUX_1460 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_DYMUX : X_BUF generic map( LOC => "SLICE_X47Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_DYMUX_1461 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_SRINV : X_BUF generic map( LOC => "SLICE_X47Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_SRINV_1462 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_CLKINV : X_BUF generic map( LOC => "SLICE_X47Y6", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_CLKINV_1463 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_DXMUX : X_BUF generic map( LOC => "SLICE_X22Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(6), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_DXMUX_1464 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_DYMUX : X_BUF generic map( LOC => "SLICE_X22Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(5), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_DYMUX_1465 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_SRINV : X_BUF generic map( LOC => "SLICE_X22Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_SRINV_1466 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_CLKINV : X_BUF generic map( LOC => "SLICE_X22Y7", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_CLKINV_1467 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_DXMUX : X_BUF generic map( LOC => "SLICE_X45Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(7), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_DXMUX_1468 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_DYMUX : X_BUF generic map( LOC => "SLICE_X45Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(6), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_DYMUX_1469 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_SRINV : X_BUF generic map( LOC => "SLICE_X45Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_SRINV_1470 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_CLKINV : X_BUF generic map( LOC => "SLICE_X45Y7", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_CLKINV_1471 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_DXMUX : X_BUF generic map( LOC => "SLICE_X22Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(8), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_DXMUX_1472 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_DYMUX : X_BUF generic map( LOC => "SLICE_X22Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(7), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_DYMUX_1473 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_SRINV : X_BUF generic map( LOC => "SLICE_X22Y6", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_SRINV_1474 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_CLKINV : X_BUF generic map( LOC => "SLICE_X22Y6", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_CLKINV_1475 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_DYMUX : X_BUF generic map( LOC => "SLICE_X50Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(8), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_DYMUX_1476 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_CLKINV : X_BUF generic map( LOC => "SLICE_X50Y6", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_CLKINV_1477 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_9_DYMUX : X_BUF generic map( LOC => "SLICE_X22Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(9), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_9_DYMUX_1478 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_9_CLKINV : X_BUF generic map( LOC => "SLICE_X22Y8", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_9_CLKINV_1479 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_DYMUX : X_BUF generic map( LOC => "SLICE_X45Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(8), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_DYMUX_1480 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_CLKINV : X_BUF generic map( LOC => "SLICE_X45Y6", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_CLKINV_1481 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_9_DYMUX : X_BUF generic map( LOC => "SLICE_X29Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(9), O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_9_DYMUX_1482 ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_9_CLKINV : X_BUF generic map( LOC => "SLICE_X29Y5", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_9_CLKINV_1483 ); s_U2X_EMPTY_DXMUX : X_BUF generic map( LOC => "SLICE_X27Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_EMPTY_NONREG, O => s_U2X_EMPTY_DXMUX_1484 ); s_U2X_EMPTY_YUSED : X_BUF generic map( LOC => "SLICE_X27Y7", PATHPULSE => 757 ps ) port map ( I => s_U2X_RD_EN_pack_1, O => s_U2X_RD_EN ); s_U2X_EMPTY_CLKINV : X_BUF generic map( LOC => "SLICE_X27Y7", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => s_U2X_EMPTY_CLKINV_1485 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_DYMUX : X_BUF generic map( LOC => "SLICE_X25Y11", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(8), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_DYMUX_1486 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_CLKINV : X_BUF generic map( LOC => "SLICE_X25Y11", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_CLKINV_1487 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_9_DYMUX : X_BUF generic map( LOC => "SLICE_X48Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(9), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_9_DYMUX_1488 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_9_CLKINV : X_BUF generic map( LOC => "SLICE_X48Y7", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_9_CLKINV_1489 ); o_WRX_OBUF_YUSED : X_BUF generic map( LOC => "SLICE_X39Y1", PATHPULSE => 757 ps ) port map ( I => N31_pack_1, O => N31 ); FSM_GPIF_o_WRX_SW1 : X_LUT4 generic map( INIT => X"AA00", LOC => "SLICE_X39Y1" ) port map ( ADR0 => i_RDYU_IBUF_3, ADR1 => VCC, ADR2 => VCC, ADR3 => i_WRU_IBUF_2, O => N31_pack_1 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_DXMUX : X_BUF generic map( LOC => "SLICE_X28Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_DXMUX_1491 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_DYMUX : X_BUF generic map( LOC => "SLICE_X28Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_DYMUX_1492 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_SRINV : X_BUF generic map( LOC => "SLICE_X28Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_SRINV_1493 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_CLKINV : X_BUF generic map( LOC => "SLICE_X28Y8", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_CLKINV_1494 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_DXMUX : X_BUF generic map( LOC => "SLICE_X49Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(2), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_DXMUX_1495 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_DYMUX : X_BUF generic map( LOC => "SLICE_X49Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(1), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_DYMUX_1496 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_SRINV : X_BUF generic map( LOC => "SLICE_X49Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_SRINV_1497 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_CLKINV : X_BUF generic map( LOC => "SLICE_X49Y3", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_CLKINV_1498 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_DXMUX : X_BUF generic map( LOC => "SLICE_X29Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_DXMUX_1499 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_DYMUX : X_BUF generic map( LOC => "SLICE_X29Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_DYMUX_1500 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_SRINV : X_BUF generic map( LOC => "SLICE_X29Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_SRINV_1501 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_CLKINV : X_BUF generic map( LOC => "SLICE_X29Y10", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_CLKINV_1502 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_DXMUX : X_BUF generic map( LOC => "SLICE_X48Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_DXMUX_1503 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_DYMUX : X_BUF generic map( LOC => "SLICE_X48Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_DYMUX_1504 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_SRINV : X_BUF generic map( LOC => "SLICE_X48Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_SRINV_1505 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_CLKINV : X_BUF generic map( LOC => "SLICE_X48Y2", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_CLKINV_1506 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_DXMUX : X_BUF generic map( LOC => "SLICE_X27Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(5), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_DXMUX_1507 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_DYMUX : X_BUF generic map( LOC => "SLICE_X27Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_DYMUX_1508 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_SRINV : X_BUF generic map( LOC => "SLICE_X27Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_SRINV_1509 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_CLKINV : X_BUF generic map( LOC => "SLICE_X27Y10", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_CLKINV_1510 ); F_OUT_BU2_U0_gen_as_fgas_N90_XUSED : X_BUF generic map( LOC => "SLICE_X43Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_N90, O => F_OUT_BU2_U0_gen_as_fgas_N90_0 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW0 : X_LUT4 generic map( INIT => X"55AA", LOC => "SLICE_X43Y7" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(1), ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(2), O => F_OUT_BU2_U0_gen_as_fgas_N90 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_DXMUX : X_BUF generic map( LOC => "SLICE_X48Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(6), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_DXMUX_1511 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_DYMUX : X_BUF generic map( LOC => "SLICE_X48Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(5), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_DYMUX_1512 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_SRINV : X_BUF generic map( LOC => "SLICE_X48Y3", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_SRINV_1513 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_CLKINV : X_BUF generic map( LOC => "SLICE_X48Y3", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_CLKINV_1514 ); F_IN_BU2_U0_gen_as_fgas_N90_XUSED : X_BUF generic map( LOC => "SLICE_X25Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_N90, O => F_IN_BU2_U0_gen_as_fgas_N90_0 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW0 : X_LUT4 generic map( INIT => X"55AA", LOC => "SLICE_X25Y2" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(3), ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(2), O => F_IN_BU2_U0_gen_as_fgas_N90 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_DXMUX : X_BUF generic map( LOC => "SLICE_X27Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(7), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_DXMUX_1515 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_DYMUX : X_BUF generic map( LOC => "SLICE_X27Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(6), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_DYMUX_1516 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_SRINV : X_BUF generic map( LOC => "SLICE_X27Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_SRINV_1517 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_CLKINV : X_BUF generic map( LOC => "SLICE_X27Y12", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_CLKINV_1518 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_DXMUX : X_BUF generic map( LOC => "SLICE_X46Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(8), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_DXMUX_1519 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_DYMUX : X_BUF generic map( LOC => "SLICE_X46Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(7), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_DYMUX_1520 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_SRINV : X_BUF generic map( LOC => "SLICE_X46Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_SRINV_1521 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_CLKINV : X_BUF generic map( LOC => "SLICE_X46Y6", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_CLKINV_1522 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_DYMUX : X_BUF generic map( LOC => "SLICE_X27Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(8), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_DYMUX_1523 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_CLKINV : X_BUF generic map( LOC => "SLICE_X27Y13", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_CLKINV_1524 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9_DYMUX : X_BUF generic map( LOC => "SLICE_X48Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(9), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9_DYMUX_1525 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9_CLKINV : X_BUF generic map( LOC => "SLICE_X48Y6", PATHPULSE => 757 ps ) port map ( I => i_SYSCLK_BUFGP, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9_CLKINV_1526 ); FSM_GPIF_v_setup_2_DXMUX : X_BUF generic map( LOC => "SLICE_X39Y6", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_Mcount_v_setup_eqn_2_1528, O => FSM_GPIF_v_setup_2_DXMUX_1527 ); FSM_GPIF_v_setup_2_YUSED : X_BUF generic map( LOC => "SLICE_X39Y6", PATHPULSE => 757 ps ) port map ( I => N23_pack_1, O => N23 ); FSM_GPIF_v_setup_2_CLKINV : X_BUF generic map( LOC => "SLICE_X39Y6", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => FSM_GPIF_v_setup_2_CLKINV_1529 ); FSM_GPIF_v_setup_2_CEINV : X_BUF generic map( LOC => "SLICE_X39Y6", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_v_setup_not0001_0, O => FSM_GPIF_v_setup_2_CEINV_1530 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1_1_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X42Y4" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(3), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(3), ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(2), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1_3_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X42Y5" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(7), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(8), ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(7), ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(6), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1_1_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X30Y12" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(1), ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(2), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(2), ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1_3_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X30Y13" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(6), ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(7), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(6), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(5), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1_1_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X36Y6" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(1), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(3), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(2), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(2), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1_3_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X36Y7" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(5), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(6), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(6), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(7), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1_1_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X26Y4" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(3), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(3), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(4), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1_3_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X26Y5" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(8), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(7), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(7), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(6), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1_1_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X45Y2" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(4), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(2), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(3), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1_3_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X45Y3" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(7), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(6), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(7), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(8), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1_1_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X27Y14" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(2), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(2), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(3), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1_3_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X27Y15" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(6), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(6), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(5), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(7), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1_1_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X28Y2" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(4), ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(2), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(3), ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1_3_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X28Y3" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(6), ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(7), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(8), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(7), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1_1_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X24Y2" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(3), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(2), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(3), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1_3_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X24Y3" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(7), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(8), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(7), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(6), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1_1_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X41Y2" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(3), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(2), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(4), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1_3_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X41Y3" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(6), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(7), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(8), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(7), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1_1_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X28Y14" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(1), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(3), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(2), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1_3_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X28Y15" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(6), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(6), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(5), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(7), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1_1_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X37Y6" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(2), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(1), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(2), ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1_3_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X37Y7" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(7), ADR1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(6), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(6), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(5), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1_1_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X27Y4" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(3), ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(2), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(4), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1_3_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X27Y5" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(8), ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(6), ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(7), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(7), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1_1_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X43Y2" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(3), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(3), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(4), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(2), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1_3_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X43Y3" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(6), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(8), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(7), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(7), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1_1_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X29Y14" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(2), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(2), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(3), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1_3_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X29Y15" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(7), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(6), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(5), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(6), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(3) ); FSM_GPIF_o_dbus_10 : X_FF generic map( LOC => "PAD331", INIT => '0' ) port map ( I => b_dbus_10_IFF_IFFDMUX_1533, CE => b_dbus_10_IFF_ICEINV_1532, CLK => b_dbus_10_IFF_ICLK1INV_1531, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(10) ); b_dbus_10_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD331", PATHPULSE => 757 ps ) port map ( I => b_dbus_10_INBUF, O => b_dbus_10_IFF_IFFDMUX_1533 ); b_dbus_10_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD331", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_10_IFF_ICLK1INV_1531 ); b_dbus_10_IFF_ICEINV : X_BUF generic map( LOC => "PAD331", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_10_IFF_ICEINV_1532 ); FSM_GPIF_o_dbus_11 : X_FF generic map( LOC => "PAD370", INIT => '0' ) port map ( I => b_dbus_11_IFF_IFFDMUX_1536, CE => b_dbus_11_IFF_ICEINV_1535, CLK => b_dbus_11_IFF_ICLK1INV_1534, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(11) ); b_dbus_11_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD370", PATHPULSE => 757 ps ) port map ( I => b_dbus_11_INBUF, O => b_dbus_11_IFF_IFFDMUX_1536 ); b_dbus_11_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD370", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_11_IFF_ICLK1INV_1534 ); b_dbus_11_IFF_ICEINV : X_BUF generic map( LOC => "PAD370", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_11_IFF_ICEINV_1535 ); FSM_GPIF_o_dbus_12 : X_FF generic map( LOC => "PAD324", INIT => '0' ) port map ( I => b_dbus_12_IFF_IFFDMUX_1539, CE => b_dbus_12_IFF_ICEINV_1538, CLK => b_dbus_12_IFF_ICLK1INV_1537, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(12) ); b_dbus_12_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD324", PATHPULSE => 757 ps ) port map ( I => b_dbus_12_INBUF, O => b_dbus_12_IFF_IFFDMUX_1539 ); b_dbus_12_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD324", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_12_IFF_ICLK1INV_1537 ); b_dbus_12_IFF_ICEINV : X_BUF generic map( LOC => "PAD324", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_12_IFF_ICEINV_1538 ); FSM_GPIF_o_dbus_13 : X_FF generic map( LOC => "PAD334", INIT => '0' ) port map ( I => b_dbus_13_IFF_IFFDMUX_1542, CE => b_dbus_13_IFF_ICEINV_1541, CLK => b_dbus_13_IFF_ICLK1INV_1540, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(13) ); b_dbus_13_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD334", PATHPULSE => 757 ps ) port map ( I => b_dbus_13_INBUF, O => b_dbus_13_IFF_IFFDMUX_1542 ); b_dbus_13_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD334", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_13_IFF_ICLK1INV_1540 ); b_dbus_13_IFF_ICEINV : X_BUF generic map( LOC => "PAD334", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_13_IFF_ICEINV_1541 ); FSM_GPIF_o_dbus_14 : X_FF generic map( LOC => "PAD337", INIT => '0' ) port map ( I => b_dbus_14_IFF_IFFDMUX_1545, CE => b_dbus_14_IFF_ICEINV_1544, CLK => b_dbus_14_IFF_ICLK1INV_1543, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(14) ); b_dbus_14_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD337", PATHPULSE => 757 ps ) port map ( I => b_dbus_14_INBUF, O => b_dbus_14_IFF_IFFDMUX_1545 ); b_dbus_14_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD337", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_14_IFF_ICLK1INV_1543 ); b_dbus_14_IFF_ICEINV : X_BUF generic map( LOC => "PAD337", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_14_IFF_ICEINV_1544 ); FSM_GPIF_o_dbus_15 : X_FF generic map( LOC => "PAD338", INIT => '0' ) port map ( I => b_dbus_15_IFF_IFFDMUX_1548, CE => b_dbus_15_IFF_ICEINV_1547, CLK => b_dbus_15_IFF_ICLK1INV_1546, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(15) ); b_dbus_15_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD338", PATHPULSE => 757 ps ) port map ( I => b_dbus_15_INBUF, O => b_dbus_15_IFF_IFFDMUX_1548 ); b_dbus_15_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD338", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_15_IFF_ICLK1INV_1546 ); b_dbus_15_IFF_ICEINV : X_BUF generic map( LOC => "PAD338", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_15_IFF_ICEINV_1547 ); FSM_GPIF_o_dbus_0 : X_FF generic map( LOC => "PAD336", INIT => '0' ) port map ( I => b_dbus_0_IFF_IFFDMUX_1551, CE => b_dbus_0_IFF_ICEINV_1550, CLK => b_dbus_0_IFF_ICLK1INV_1549, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(0) ); b_dbus_0_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD336", PATHPULSE => 757 ps ) port map ( I => b_dbus_0_INBUF, O => b_dbus_0_IFF_IFFDMUX_1551 ); b_dbus_0_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD336", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_0_IFF_ICLK1INV_1549 ); b_dbus_0_IFF_ICEINV : X_BUF generic map( LOC => "PAD336", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_0_IFF_ICEINV_1550 ); FSM_GPIF_o_dbus_1 : X_FF generic map( LOC => "PAD335", INIT => '0' ) port map ( I => b_dbus_1_IFF_IFFDMUX_1554, CE => b_dbus_1_IFF_ICEINV_1553, CLK => b_dbus_1_IFF_ICLK1INV_1552, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(1) ); b_dbus_1_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD335", PATHPULSE => 757 ps ) port map ( I => b_dbus_1_INBUF, O => b_dbus_1_IFF_IFFDMUX_1554 ); b_dbus_1_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD335", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_1_IFF_ICLK1INV_1552 ); b_dbus_1_IFF_ICEINV : X_BUF generic map( LOC => "PAD335", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_1_IFF_ICEINV_1553 ); FSM_GPIF_o_dbus_2 : X_FF generic map( LOC => "PAD328", INIT => '0' ) port map ( I => b_dbus_2_IFF_IFFDMUX_1557, CE => b_dbus_2_IFF_ICEINV_1556, CLK => b_dbus_2_IFF_ICLK1INV_1555, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(2) ); b_dbus_2_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD328", PATHPULSE => 757 ps ) port map ( I => b_dbus_2_INBUF, O => b_dbus_2_IFF_IFFDMUX_1557 ); b_dbus_2_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD328", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_2_IFF_ICLK1INV_1555 ); b_dbus_2_IFF_ICEINV : X_BUF generic map( LOC => "PAD328", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_2_IFF_ICEINV_1556 ); FSM_GPIF_o_dbus_3 : X_FF generic map( LOC => "PAD327", INIT => '0' ) port map ( I => b_dbus_3_IFF_IFFDMUX_1560, CE => b_dbus_3_IFF_ICEINV_1559, CLK => b_dbus_3_IFF_ICLK1INV_1558, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(3) ); b_dbus_3_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD327", PATHPULSE => 757 ps ) port map ( I => b_dbus_3_INBUF, O => b_dbus_3_IFF_IFFDMUX_1560 ); b_dbus_3_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD327", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_3_IFF_ICLK1INV_1558 ); b_dbus_3_IFF_ICEINV : X_BUF generic map( LOC => "PAD327", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_3_IFF_ICEINV_1559 ); FSM_GPIF_o_dbus_4 : X_FF generic map( LOC => "PAD318", INIT => '0' ) port map ( I => b_dbus_4_IFF_IFFDMUX_1563, CE => b_dbus_4_IFF_ICEINV_1562, CLK => b_dbus_4_IFF_ICLK1INV_1561, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(4) ); b_dbus_4_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD318", PATHPULSE => 757 ps ) port map ( I => b_dbus_4_INBUF, O => b_dbus_4_IFF_IFFDMUX_1563 ); b_dbus_4_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD318", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_4_IFF_ICLK1INV_1561 ); b_dbus_4_IFF_ICEINV : X_BUF generic map( LOC => "PAD318", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_4_IFF_ICEINV_1562 ); FSM_GPIF_o_dbus_5 : X_FF generic map( LOC => "PAD317", INIT => '0' ) port map ( I => b_dbus_5_IFF_IFFDMUX_1566, CE => b_dbus_5_IFF_ICEINV_1565, CLK => b_dbus_5_IFF_ICLK1INV_1564, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(5) ); b_dbus_5_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD317", PATHPULSE => 757 ps ) port map ( I => b_dbus_5_INBUF, O => b_dbus_5_IFF_IFFDMUX_1566 ); b_dbus_5_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD317", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_5_IFF_ICLK1INV_1564 ); b_dbus_5_IFF_ICEINV : X_BUF generic map( LOC => "PAD317", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_5_IFF_ICEINV_1565 ); FSM_GPIF_o_dbus_6 : X_FF generic map( LOC => "PAD311", INIT => '0' ) port map ( I => b_dbus_6_IFF_IFFDMUX_1569, CE => b_dbus_6_IFF_ICEINV_1568, CLK => b_dbus_6_IFF_ICLK1INV_1567, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(6) ); b_dbus_6_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD311", PATHPULSE => 757 ps ) port map ( I => b_dbus_6_INBUF, O => b_dbus_6_IFF_IFFDMUX_1569 ); b_dbus_6_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD311", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_6_IFF_ICLK1INV_1567 ); b_dbus_6_IFF_ICEINV : X_BUF generic map( LOC => "PAD311", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_6_IFF_ICEINV_1568 ); FSM_GPIF_o_dbus_7 : X_FF generic map( LOC => "PAD310", INIT => '0' ) port map ( I => b_dbus_7_IFF_IFFDMUX_1572, CE => b_dbus_7_IFF_ICEINV_1571, CLK => b_dbus_7_IFF_ICLK1INV_1570, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(7) ); b_dbus_7_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD310", PATHPULSE => 757 ps ) port map ( I => b_dbus_7_INBUF, O => b_dbus_7_IFF_IFFDMUX_1572 ); b_dbus_7_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD310", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_7_IFF_ICLK1INV_1570 ); b_dbus_7_IFF_ICEINV : X_BUF generic map( LOC => "PAD310", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_7_IFF_ICEINV_1571 ); FSM_GPIF_o_dbus_8 : X_FF generic map( LOC => "PAD371", INIT => '0' ) port map ( I => b_dbus_8_IFF_IFFDMUX_1575, CE => b_dbus_8_IFF_ICEINV_1574, CLK => b_dbus_8_IFF_ICLK1INV_1573, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(8) ); b_dbus_8_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD371", PATHPULSE => 757 ps ) port map ( I => b_dbus_8_INBUF, O => b_dbus_8_IFF_IFFDMUX_1575 ); b_dbus_8_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD371", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_8_IFF_ICLK1INV_1573 ); b_dbus_8_IFF_ICEINV : X_BUF generic map( LOC => "PAD371", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_8_IFF_ICEINV_1574 ); FSM_GPIF_o_dbus_9 : X_FF generic map( LOC => "PAD330", INIT => '0' ) port map ( I => b_dbus_9_IFF_IFFDMUX_1578, CE => b_dbus_9_IFF_ICEINV_1577, CLK => b_dbus_9_IFF_ICLK1INV_1576, SET => GND, RST => GND, O => FSM_GPIF_o_dbus(9) ); b_dbus_9_IFF_IFFDMUX : X_BUF generic map( LOC => "PAD330", PATHPULSE => 757 ps ) port map ( I => b_dbus_9_INBUF, O => b_dbus_9_IFF_IFFDMUX_1578 ); b_dbus_9_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD330", PATHPULSE => 757 ps ) port map ( I => i_IFCLK_BUFGP, O => b_dbus_9_IFF_ICLK1INV_1576 ); b_dbus_9_IFF_ICEINV : X_BUF generic map( LOC => "PAD330", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_9_IFF_ICEINV_1577 ); FSM_GPIF_s_X2U_RD_EN2 : X_LUT4 generic map( INIT => X"AA20", LOC => "SLICE_X35Y7" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd1_5, ADR1 => i_WRU_IBUF_2, ADR2 => i_RDYU_IBUF_3, ADR3 => FSM_GPIF_pr_state_FFd4_6, O => N361 ); FSM_GPIF_pr_state_FFd4_In412 : X_LUT4 generic map( INIT => X"020A", LOC => "SLICE_X34Y9" ) port map ( ADR0 => s_U2X_AM_FULL, ADR1 => i_RDYU_IBUF_3, ADR2 => FSM_GPIF_pr_state_FFd1_5, ADR3 => i_WRU_IBUF_2, O => N363 ); FSM_GPIF_o_RDYX59_F : X_LUT4 generic map( INIT => X"0200", LOC => "SLICE_X38Y11" ) port map ( ADR0 => i_WRU_IBUF_2, ADR1 => i_RDYU_IBUF_3, ADR2 => FSM_GPIF_pr_state_FFd3_7, ADR3 => FSM_GPIF_pr_state_FFd2_10, O => N354 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1_0_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X42Y4" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(2), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(1), ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(1), ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(0), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1_0_and00001 : X_LUT4 generic map( INIT => X"0909", LOC => "SLICE_X30Y12" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(1), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(0), ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(0), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1_0_and00001 : X_LUT4 generic map( INIT => X"4411", LOC => "SLICE_X36Y6" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(0), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(0), ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(1), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1_2_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X45Y3" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(5), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(6), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(5), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1_2_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X27Y15" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(4), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(4), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(3), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(5), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1_2_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X28Y3" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(6), ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(5), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(5), ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1_2_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X24Y3" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(4), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(5), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(6), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(5), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1_2_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X41Y3" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(5), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(5), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(4), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(6), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1_0_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X26Y4" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(0), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(1), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(1), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1_0_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X45Y2" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(1), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(2), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(0), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(1), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1_0_and00001 : X_LUT4 generic map( INIT => X"2121", LOC => "SLICE_X27Y14" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(0), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(0), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(1), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp1_v1(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1_0_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X28Y2" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(0), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(1), ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(1), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(2), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae2_v1(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1_0_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X24Y2" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(2), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(0), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(1), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_cae1_v1(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1_0_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X41Y2" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(1), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(1), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(2), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(0), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1_0_and00001 : X_LUT4 generic map( INIT => X"2211", LOC => "SLICE_X28Y14" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(0), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(0), ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1_0_and00001 : X_LUT4 generic map( INIT => X"00A5", LOC => "SLICE_X37Y6" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(1), ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(0), ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(0), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1_0_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X27Y4" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(2), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(1), ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(0), ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1_0_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X43Y2" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(1), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(2), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(0), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(1), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1_0_and00001 : X_LUT4 generic map( INIT => X"0A05", LOC => "SLICE_X29Y14" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(1), ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(0), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(0) ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_rt : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X53Y14" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(8), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_rt_302 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_rt : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X44Y8" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(8), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_rt_368 ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_rt : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X40Y4" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(8), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_rt_434 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_rt : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X38Y6" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(8), O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_rt_500 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9 : X_FF generic map( LOC => "SLICE_X35Y12", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_DYMUX_568, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CEINV_573, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CLKINV_572, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_SRINV_571, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(9) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9 : X_FF generic map( LOC => "SLICE_X34Y8", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_DYMUX_639, CE => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CEINV_644, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CLKINV_643, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_SRINV_642, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(9) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9 : X_FF generic map( LOC => "SLICE_X10Y6", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_DYMUX_706, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CLKINV_710, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_SRINV_709, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(9) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9 : X_FF generic map( LOC => "SLICE_X24Y18", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_DYMUX_772, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CLKINV_776, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_SRINV_775, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(9) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9 : X_FF generic map( LOC => "SLICE_X26Y16", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_DYMUX_838, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CLKINV_842, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_SRINV_841, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(9) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_9 : X_FF generic map( LOC => "SLICE_X31Y16", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DYMUX_904 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CEINVNOT , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CLKINV_908 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_SRINV_907 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(9) ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_rt : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X24Y10" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(8), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_rt_972 ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_rt : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X31Y8" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(8), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_rt_1038 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_rt : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X29Y4" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(8), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_rt_1104 ); FSM_GPIF_s_X2U_RD_EN1 : X_LUT4 generic map( INIT => X"AA2A", LOC => "SLICE_X35Y7" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd1_5, ADR1 => i_WRU_IBUF_2, ADR2 => i_RDYU_IBUF_3, ADR3 => FSM_GPIF_pr_state_FFd4_6, O => N360 ); FSM_GPIF_pr_state_FFd4_In411 : X_LUT4 generic map( INIT => X"0088", LOC => "SLICE_X34Y9" ) port map ( ADR0 => s_X2U_EMPTY, ADR1 => FSM_GPIF_pr_state_FFd4_6, ADR2 => VCC, ADR3 => i_WRU_IBUF_2, O => N362 ); Loopback_pr_stateLoop_FFd2_In1 : X_LUT4 generic map( INIT => X"33FF", LOC => "SLICE_X28Y7" ) port map ( ADR0 => VCC, ADR1 => Loopback_pr_stateLoop_FFd3_8, ADR2 => VCC, ADR3 => Loopback_pr_stateLoop_FFd2_9, O => N357 ); FSM_GPIF_o_RDYX59_G : X_LUT4 generic map( INIT => X"44FC", LOC => "SLICE_X38Y11" ) port map ( ADR0 => i_RDYU_IBUF_3, ADR1 => FSM_GPIF_o_RDYX_map9_0, ADR2 => FSM_GPIF_o_RDYX_map19_0, ADR3 => i_WRU_IBUF_2, O => N355 ); FSM_GPIF_pr_state_FFd3_In98_SW0 : X_LUT4 generic map( INIT => X"F0FE", LOC => "SLICE_X36Y11" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd3_In_map22_0, ADR1 => FSM_GPIF_pr_state_FFd3_In_map18_0, ADR2 => N4, ADR3 => i_WRU_IBUF_2, O => FSM_GPIF_pr_state_FFd3_In98_SW0_O_pack_1 ); FSM_GPIF_Mcount_v_setup_eqn_332 : X_LUT4 generic map( INIT => X"7F80", LOC => "SLICE_X39Y7" ) port map ( ADR0 => FSM_GPIF_v_setup(0), ADR1 => FSM_GPIF_v_setup(2), ADR2 => FSM_GPIF_v_setup(1), ADR3 => FSM_GPIF_v_setup(3), O => FSM_GPIF_Mcount_v_setup_eqn_332_O_pack_1 ); FSM_GPIF_pr_state_FFd4_In13 : X_LUT4 generic map( INIT => X"EAAA", LOC => "SLICE_X36Y9" ) port map ( ADR0 => N4, ADR1 => s_X2U_EMPTY, ADR2 => FSM_GPIF_o_RDYX_map2_0, ADR3 => FSM_GPIF_pr_state_FFd1_5, O => FSM_GPIF_pr_state_FFd4_In13_O_pack_1 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1 : X_LUT4 generic map( INIT => X"6969", LOC => "SLICE_X42Y2" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(2), ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(1), ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(3), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1_O_pack_1 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1 : X_LUT4 generic map( INIT => X"6699", LOC => "SLICE_X28Y13" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(0), ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(2), ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1_O_pack_1 ); FSM_GPIF_Mcount_v_setup_eqn_0_SW0 : X_LUT4 generic map( INIT => X"DFFF", LOC => "SLICE_X36Y4" ) port map ( ADR0 => FSM_GPIF_v_setup(3), ADR1 => N4, ADR2 => i_WRU_IBUF_2, ADR3 => i_RDYU_IBUF_3, O => FSM_GPIF_Mcount_v_setup_eqn_3_map0_pack_1 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1 : X_LUT4 generic map( INIT => X"6699", LOC => "SLICE_X43Y6" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(1), ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(0), ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(2), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1_O_pack_1 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1 : X_LUT4 generic map( INIT => X"3CC3", LOC => "SLICE_X26Y2" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(1), ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(2), ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1_O_pack_1 ); FSM_GPIF_pr_state_FFd2_In5 : X_LUT4 generic map( INIT => X"DD00", LOC => "SLICE_X36Y10" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd3_7, ADR1 => FSM_GPIF_pr_state_FFd4_6, ADR2 => VCC, ADR3 => FSM_GPIF_pr_state_FFd2_10, O => FSM_GPIF_pr_state_FFd2_In5_O_pack_1 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00062 : X_LUT4 generic map( INIT => X"6996", LOC => "SLICE_X29Y13" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(3), ADR1 => F_IN_BU2_U0_gen_as_fgas_N86_0, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0006 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00062 : X_LUT4 generic map( INIT => X"6996", LOC => "SLICE_X43Y5" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002, ADR1 => F_OUT_BU2_U0_gen_as_fgas_N86_0, ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(4), ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(5), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0006 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_almost_full_i_or00001 : X_LUT4 generic map( INIT => X"DCCC", LOC => "SLICE_X28Y6" ) port map ( ADR0 => F_OUT_full, ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1, ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2, ADR3 => s_X2U_WR_EN, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_almost_full_i_or0000 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00062 : X_LUT4 generic map( INIT => X"6996", LOC => "SLICE_X42Y7" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002, ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(4), ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(3), ADR3 => F_OUT_BU2_U0_gen_as_fgas_N90_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0006 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00062 : X_LUT4 generic map( INIT => X"6996", LOC => "SLICE_X27Y2" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002, ADR1 => F_IN_BU2_U0_gen_as_fgas_N90_0, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(4), ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(5), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0006 ); FSM_GPIF_Mcount_v_setup_eqn_1 : X_LUT4 generic map( INIT => X"4588", LOC => "SLICE_X38Y7" ) port map ( ADR0 => FSM_GPIF_v_setup(1), ADR1 => FSM_GPIF_Mcount_v_setup_eqn_3_map0, ADR2 => FSM_GPIF_v_setup(2), ADR3 => FSM_GPIF_v_setup(0), O => FSM_GPIF_Mcount_v_setup_eqn_1_1239 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_almost_empty_i_or00001 : X_LUT4 generic map( INIT => X"FF40", LOC => "SLICE_X25Y5" ) port map ( ADR0 => s_U2X_EMPTY, ADR1 => s_U2X_RD_EN, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae2, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_comp_ae1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_almost_empty_i_or0000 ); Loopback_pr_stateLoop_FFd3_In1 : X_LUT4 generic map( INIT => X"1105", LOC => "SLICE_X29Y7" ) port map ( ADR0 => s_X2U_AM_FULL, ADR1 => s_U2X_EMPTY, ADR2 => s_U2X_AM_EMPTY, ADR3 => Loopback_pr_stateLoop_FFd3_8, O => N333 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG_i1 : X_LUT4 generic map( INIT => X"FF0C", LOC => "SLICE_X26Y17" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2, ADR2 => F_IN_full, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG ); FSM_GPIF_pr_state_FFd1_In_SW0 : X_LUT4 generic map( INIT => X"C0FF", LOC => "SLICE_X37Y5" ) port map ( ADR0 => VCC, ADR1 => i_WRU_IBUF_2, ADR2 => i_RDYU_IBUF_3, ADR3 => FSM_GPIF_pr_state_FFd1_5, O => N89_pack_1 ); Loopback_s_U2X_RD_EN1 : X_LUT4 generic map( INIT => X"30F0", LOC => "SLICE_X27Y7" ) port map ( ADR0 => VCC, ADR1 => s_X2U_AM_FULL, ADR2 => Loopback_pr_stateLoop_FFd3_8, ADR3 => Loopback_pr_stateLoop_FFd2_9, O => s_U2X_RD_EN_pack_1 ); FSM_GPIF_Mcount_v_setup_eqn_1211 : X_LUT4 generic map( INIT => X"5FFF", LOC => "SLICE_X39Y6" ) port map ( ADR0 => i_WRU_IBUF_2, ADR1 => VCC, ADR2 => i_RDYU_IBUF_3, ADR3 => FSM_GPIF_v_setup(3), O => N23_pack_1 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1_2_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X42Y5" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(6), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(5), ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(5), ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1_2_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X30Y13" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(4), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(3), ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(4), ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(5), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf2_v1(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1_2_and00001 : X_LUT4 generic map( INIT => X"8421", LOC => "SLICE_X36Y7" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(3), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(5), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(4), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1_2_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X26Y5" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(5), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(5), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(4), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(6), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 : X_FF generic map( LOC => "SLICE_X53Y14", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_DXMUX_299, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CEINV_304, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CLKINV_303, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_FFX_RSTAND_1579, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(8) ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_FFX_RSTAND : X_BUF generic map( LOC => "SLICE_X53Y14", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_FFX_RSTAND_1579 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 : X_FF generic map( LOC => "SLICE_X44Y4", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DYMUX_309, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CEINV_316, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CLKINV_315, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_SRINV_314, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_INV_0 : X_LUT4 generic map( INIT => X"3333", LOC => "SLICE_X44Y4" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(0), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 : X_FF generic map( LOC => "SLICE_X44Y4", INIT => '1' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DXMUX_305, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CEINV_316, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CLKINV_315, SET => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_SRINV_314, RST => GND, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 : X_FF generic map( LOC => "SLICE_X44Y5", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DYMUX_320, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CEINV_332, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CLKINV_331, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_SRINV_330, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 : X_FF generic map( LOC => "SLICE_X44Y5", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DXMUX_317, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CEINV_332, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CLKINV_331, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_SRINV_330, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 : X_FF generic map( LOC => "SLICE_X24Y18", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_DXMUX_767, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CLKINV_776, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_SRINV_775, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(8) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 : X_FF generic map( LOC => "SLICE_X26Y12", INIT => '1' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DYMUX_781, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CLKINV_787, SET => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_SRINV_786, RST => GND, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_INV_0 : X_LUT4 generic map( INIT => X"00FF", LOC => "SLICE_X26Y12" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 : X_FF generic map( LOC => "SLICE_X26Y12", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DXMUX_777, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CLKINV_787, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_SRINV_786, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 : X_FF generic map( LOC => "SLICE_X26Y13", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DYMUX_791, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CLKINV_802, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_SRINV_801, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 : X_FF generic map( LOC => "SLICE_X35Y8", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DYMUX_507, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CEINV_514, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CLKINV_513, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_SRINV_512, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_INV_0 : X_LUT4 generic map( INIT => X"0F0F", LOC => "SLICE_X35Y8" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(0), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 : X_FF generic map( LOC => "SLICE_X35Y8", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DXMUX_503, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CEINV_514, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CLKINV_513, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_SRINV_512, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 : X_FF generic map( LOC => "SLICE_X35Y9", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DYMUX_518, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CEINV_530, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CLKINV_529, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_SRINV_528, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 : X_FF generic map( LOC => "SLICE_X35Y9", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DXMUX_515, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CEINV_530, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CLKINV_529, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_SRINV_528, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 : X_FF generic map( LOC => "SLICE_X35Y10", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DYMUX_534, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CEINV_546, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CLKINV_545, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_SRINV_544, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1_2_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X28Y15" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(5), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(3), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(4), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_caf1_v1(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1_2_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X37Y7" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(4), ADR1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(5), ADR2 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(4), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1_2_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X27Y5" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(6), ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(4), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(5), ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(5), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1_2_and00001 : X_LUT4 generic map( INIT => X"9009", LOC => "SLICE_X43Y3" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(6), ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(5), ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(4), ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(5), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 : X_FF generic map( LOC => "SLICE_X53Y11", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DXMUX_251, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CEINV_266, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CLKINV_265, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_SRINV_264, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 : X_FF generic map( LOC => "SLICE_X53Y12", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DYMUX_270, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CEINV_282, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CLKINV_281, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_SRINV_280, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(5) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 : X_FF generic map( LOC => "SLICE_X53Y12", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DXMUX_267, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CEINV_282, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CLKINV_281, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_SRINV_280, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 : X_FF generic map( LOC => "SLICE_X53Y13", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DYMUX_286, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CEINV_298, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CLKINV_297, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_SRINV_296, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(7) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 : X_FF generic map( LOC => "SLICE_X53Y13", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DXMUX_283, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CEINV_298, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CLKINV_297, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_SRINV_296, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(6) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1_2_and00001 : X_LUT4 generic map( INIT => X"8241", LOC => "SLICE_X29Y15" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(4), ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(4), ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(3), ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(5), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp2_v1(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 : X_FF generic map( LOC => "SLICE_X53Y10", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DYMUX_243, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CEINV_250, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CLKINV_249, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_SRINV_248, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_INV_0 : X_LUT4 generic map( INIT => X"0F0F", LOC => "SLICE_X53Y10" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(0), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 : X_FF generic map( LOC => "SLICE_X53Y10", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DXMUX_239, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CEINV_250, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CLKINV_249, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_SRINV_248, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 : X_FF generic map( LOC => "SLICE_X53Y11", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DYMUX_254, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CEINV_266, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CLKINV_265, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_SRINV_264, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 : X_FF generic map( LOC => "SLICE_X44Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DYMUX_336, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CEINV_348, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CLKINV_347, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_SRINV_346, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(5) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 : X_FF generic map( LOC => "SLICE_X44Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DXMUX_333, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CEINV_348, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CLKINV_347, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_SRINV_346, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 : X_FF generic map( LOC => "SLICE_X44Y7", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DYMUX_352, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CEINV_364, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CLKINV_363, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_SRINV_362, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(7) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 : X_FF generic map( LOC => "SLICE_X44Y7", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DXMUX_349, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CEINV_364, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CLKINV_363, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_SRINV_362, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 : X_FF generic map( LOC => "SLICE_X44Y8", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_DXMUX_365, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CEINV_370, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_CLKINV_369, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_FFX_RSTAND_1580, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(8) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_FFX_RSTAND : X_BUF generic map( LOC => "SLICE_X44Y8", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_FFX_RSTAND_1580 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 : X_FF generic map( LOC => "SLICE_X40Y0", INIT => '1' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DYMUX_375, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CEINV_382, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CLKINV_381, SET => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_SRINV_380, RST => GND, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_INV_0 : X_LUT4 generic map( INIT => X"00FF", LOC => "SLICE_X40Y0" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(0), O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 : X_FF generic map( LOC => "SLICE_X40Y0", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_DXMUX_371, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CEINV_382, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_CLKINV_381, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_SRINV_380, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 : X_FF generic map( LOC => "SLICE_X40Y1", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DYMUX_386, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CEINV_398, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CLKINV_397, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_SRINV_396, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 : X_FF generic map( LOC => "SLICE_X40Y1", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DXMUX_383, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CEINV_398, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CLKINV_397, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_SRINV_396, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 : X_FF generic map( LOC => "SLICE_X40Y2", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DYMUX_402, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CEINV_414, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CLKINV_413, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_SRINV_412, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(5) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 : X_FF generic map( LOC => "SLICE_X40Y2", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DXMUX_399, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CEINV_414, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CLKINV_413, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_SRINV_412, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 : X_FF generic map( LOC => "SLICE_X40Y3", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DYMUX_418, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CEINV_430, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CLKINV_429, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_SRINV_428, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(7) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 : X_FF generic map( LOC => "SLICE_X40Y3", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DXMUX_415, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CEINV_430, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CLKINV_429, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_SRINV_428, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 : X_FF generic map( LOC => "SLICE_X38Y4", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DYMUX_468 , CE => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CEINV_480 , CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CLKINV_479 , SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_SRINV_478 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(5) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 : X_FF generic map( LOC => "SLICE_X38Y4", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DXMUX_465 , CE => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CEINV_480 , CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CLKINV_479 , SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_SRINV_478 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 : X_FF generic map( LOC => "SLICE_X38Y5", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DYMUX_484 , CE => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CEINV_496 , CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CLKINV_495 , SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_SRINV_494 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(7) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 : X_FF generic map( LOC => "SLICE_X38Y5", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DXMUX_481 , CE => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CEINV_496 , CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CLKINV_495 , SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_SRINV_494 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 : X_FF generic map( LOC => "SLICE_X38Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DXMUX_497 , CE => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CEINV_502 , CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CLKINV_501 , SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_FFX_RSTAND_1581 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(8) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_FFX_RSTAND : X_BUF generic map( LOC => "SLICE_X38Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_FFX_RSTAND_1581 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 : X_FF generic map( LOC => "SLICE_X31Y13", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DXMUX_854 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CEINVNOT , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CLKINV_868 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_SRINV_867 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 : X_FF generic map( LOC => "SLICE_X31Y14", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DYMUX_872 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CEINVNOT , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CLKINV_883 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_SRINV_882 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 : X_FF generic map( LOC => "SLICE_X31Y14", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DXMUX_869 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CEINVNOT , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CLKINV_883 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_SRINV_882 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 : X_FF generic map( LOC => "SLICE_X31Y15", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DYMUX_887 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CEINVNOT , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CLKINV_898 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_SRINV_897 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(7) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 : X_FF generic map( LOC => "SLICE_X31Y15", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DXMUX_884 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CEINVNOT , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CLKINV_898 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_SRINV_897 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 : X_FF generic map( LOC => "SLICE_X40Y4", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_DXMUX_431, CE => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CEINV_436, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CLKINV_435, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_FFX_RSTAND_1582, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(8) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_FFX_RSTAND : X_BUF generic map( LOC => "SLICE_X40Y4", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_FFX_RSTAND_1582 ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 : X_FF generic map( LOC => "SLICE_X38Y2", INIT => '1' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DYMUX_441 , CE => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CEINV_448 , CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CLKINV_447 , SET => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_SRINV_446 , RST => GND, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_INV_0 : X_LUT4 generic map( INIT => X"00FF", LOC => "SLICE_X38Y2" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(0), O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 : X_FF generic map( LOC => "SLICE_X38Y2", INIT => '1' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DXMUX_437 , CE => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CEINV_448 , CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CLKINV_447 , SET => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_SRINV_446 , RST => GND, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 : X_FF generic map( LOC => "SLICE_X38Y3", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DYMUX_452 , CE => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CEINV_464 , CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CLKINV_463 , SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_SRINV_462 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 : X_FF generic map( LOC => "SLICE_X38Y3", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DXMUX_449 , CE => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CEINV_464 , CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CLKINV_463 , SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_SRINV_462 , O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 : X_FF generic map( LOC => "SLICE_X31Y5", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DXMUX_987, CE => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CEINV_1002, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CLKINV_1001, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_SRINV_1000, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 : X_FF generic map( LOC => "SLICE_X31Y6", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DYMUX_1006, CE => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CEINV_1018, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CLKINV_1017, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_SRINV_1016, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 : X_FF generic map( LOC => "SLICE_X31Y6", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DXMUX_1003, CE => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CEINV_1018, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CLKINV_1017, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_SRINV_1016, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 : X_FF generic map( LOC => "SLICE_X31Y7", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DYMUX_1022, CE => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CEINV_1034, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CLKINV_1033, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_SRINV_1032, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(7) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 : X_FF generic map( LOC => "SLICE_X31Y7", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DXMUX_1019, CE => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CEINV_1034, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CLKINV_1033, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_SRINV_1032, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 : X_FF generic map( LOC => "SLICE_X35Y10", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DXMUX_531, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CEINV_546, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CLKINV_545, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_SRINV_544, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 : X_FF generic map( LOC => "SLICE_X35Y11", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DYMUX_550, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CEINV_562, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CLKINV_561, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_SRINV_560, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(7) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 : X_FF generic map( LOC => "SLICE_X35Y11", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DXMUX_547, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CEINV_562, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CLKINV_561, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_SRINV_560, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 : X_FF generic map( LOC => "SLICE_X35Y12", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_DXMUX_563, CE => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CEINV_573, CLK => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CLKINV_572, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_SRINV_571, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(8) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 : X_FF generic map( LOC => "SLICE_X34Y4", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DYMUX_578, CE => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CEINV_585, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CLKINV_584, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_SRINV_583, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_INV_0 : X_LUT4 generic map( INIT => X"00FF", LOC => "SLICE_X34Y4" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(0), O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 : X_FF generic map( LOC => "SLICE_X34Y4", INIT => '1' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DXMUX_574, CE => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CEINV_585, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CLKINV_584, SET => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_SRINV_583, RST => GND, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 : X_FF generic map( LOC => "SLICE_X34Y5", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DYMUX_589, CE => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CEINV_601, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CLKINV_600, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_SRINV_599, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 : X_FF generic map( LOC => "SLICE_X34Y5", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DXMUX_586, CE => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CEINV_601, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CLKINV_600, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_SRINV_599, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 : X_FF generic map( LOC => "SLICE_X34Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DYMUX_605, CE => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CEINV_617, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CLKINV_616, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_SRINV_615, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(5) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 : X_FF generic map( LOC => "SLICE_X34Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_DXMUX_602, CE => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CEINV_617, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_CLKINV_616, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_SRINV_615, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 : X_FF generic map( LOC => "SLICE_X34Y7", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DYMUX_621, CE => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CEINV_633, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CLKINV_632, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_SRINV_631, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(7) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 : X_FF generic map( LOC => "SLICE_X34Y7", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_DXMUX_618, CE => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CEINV_633, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_CLKINV_632, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_SRINV_631, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 : X_FF generic map( LOC => "SLICE_X34Y8", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_DXMUX_634, CE => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CEINV_644, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CLKINV_643, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_SRINV_642, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(8) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 : X_FF generic map( LOC => "SLICE_X10Y2", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DYMUX_649, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CLKINV_655, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_SRINV_654, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_INV_0 : X_LUT4 generic map( INIT => X"3333", LOC => "SLICE_X10Y2" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(0), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 : X_FF generic map( LOC => "SLICE_X10Y2", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_DXMUX_645, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_CLKINV_655, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_SRINV_654, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 : X_FF generic map( LOC => "SLICE_X10Y3", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DYMUX_659, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CLKINV_670, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_SRINV_669, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 : X_FF generic map( LOC => "SLICE_X10Y3", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_DXMUX_656, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_CLKINV_670, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_SRINV_669, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 : X_FF generic map( LOC => "SLICE_X10Y4", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DYMUX_674, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CLKINV_685, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_SRINV_684, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 : X_FF generic map( LOC => "SLICE_X10Y4", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_DXMUX_671, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_CLKINV_685, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_SRINV_684, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 : X_FF generic map( LOC => "SLICE_X10Y5", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DYMUX_689, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CLKINV_700, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_SRINV_699, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(7) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 : X_FF generic map( LOC => "SLICE_X10Y5", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_DXMUX_686, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_CLKINV_700, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_SRINV_699, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(6) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 : X_FF generic map( LOC => "SLICE_X10Y6", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_DXMUX_701, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_CLKINV_710, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_SRINV_709, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(8) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 : X_FF generic map( LOC => "SLICE_X24Y14", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DYMUX_715, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CLKINV_721, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_SRINV_720, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_INV_0 : X_LUT4 generic map( INIT => X"00FF", LOC => "SLICE_X24Y14" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 : X_FF generic map( LOC => "SLICE_X24Y14", INIT => '1' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_DXMUX_711, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_CLKINV_721, SET => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_SRINV_720, RST => GND, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 : X_FF generic map( LOC => "SLICE_X24Y15", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DYMUX_725, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CLKINV_736, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_SRINV_735, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 : X_FF generic map( LOC => "SLICE_X24Y15", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_DXMUX_722, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_CLKINV_736, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_SRINV_735, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 : X_FF generic map( LOC => "SLICE_X24Y16", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DYMUX_740, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CLKINV_751, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_SRINV_750, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 : X_FF generic map( LOC => "SLICE_X24Y16", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_DXMUX_737, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_CLKINV_751, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_SRINV_750, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 : X_FF generic map( LOC => "SLICE_X24Y17", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DYMUX_755, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CLKINV_766, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_SRINV_765, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(7) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 : X_FF generic map( LOC => "SLICE_X24Y17", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_DXMUX_752, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_CLKINV_766, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_SRINV_765, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(6) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 : X_FF generic map( LOC => "SLICE_X26Y13", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_DXMUX_788, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_CLKINV_802, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_SRINV_801, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 : X_FF generic map( LOC => "SLICE_X26Y14", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DYMUX_806, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CLKINV_817, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_SRINV_816, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 : X_FF generic map( LOC => "SLICE_X26Y14", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_DXMUX_803, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_CLKINV_817, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_SRINV_816, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 : X_FF generic map( LOC => "SLICE_X26Y15", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DYMUX_821, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CLKINV_832, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_SRINV_831, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(7) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 : X_FF generic map( LOC => "SLICE_X26Y15", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_DXMUX_818, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_CLKINV_832, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_SRINV_831, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(6) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 : X_FF generic map( LOC => "SLICE_X26Y16", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_DXMUX_833, CE => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CEINVNOT, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_CLKINV_842, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_SRINV_841, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(8) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 : X_FF generic map( LOC => "SLICE_X31Y12", INIT => '1' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DYMUX_847 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CEINVNOT , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CLKINV_853 , SET => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_SRINV_852 , RST => GND, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_INV_0 : X_LUT4 generic map( INIT => X"3333", LOC => "SLICE_X31Y12" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(0), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 : X_FF generic map( LOC => "SLICE_X31Y12", INIT => '1' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DXMUX_843 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CEINVNOT , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CLKINV_853 , SET => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_SRINV_852 , RST => GND, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 : X_FF generic map( LOC => "SLICE_X31Y13", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DYMUX_857 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CEINVNOT , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CLKINV_868 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_SRINV_867 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 : X_FF generic map( LOC => "SLICE_X29Y1", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DXMUX_1053 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CEINV_1068 , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CLKINV_1067 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_SRINV_1066 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 : X_FF generic map( LOC => "SLICE_X29Y2", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DYMUX_1072 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CEINV_1084 , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CLKINV_1083 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_SRINV_1082 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 : X_FF generic map( LOC => "SLICE_X29Y2", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_DXMUX_1069 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CEINV_1084 , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_CLKINV_1083 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_SRINV_1082 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 : X_FF generic map( LOC => "SLICE_X29Y3", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DYMUX_1088 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CEINV_1100 , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CLKINV_1099 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_SRINV_1098 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(7) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 : X_FF generic map( LOC => "SLICE_X29Y3", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_DXMUX_1085 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CEINV_1100 , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_CLKINV_1099 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_SRINV_1098 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(6) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 : X_FF generic map( LOC => "SLICE_X31Y16", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DXMUX_899 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CEINVNOT , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CLKINV_908 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_SRINV_907 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(8) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 : X_FF generic map( LOC => "SLICE_X24Y6", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DYMUX_913, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CEINV_920, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CLKINV_919, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_SRINV_918, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_INV_0 : X_LUT4 generic map( INIT => X"3333", LOC => "SLICE_X24Y6" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(0), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 : X_FF generic map( LOC => "SLICE_X24Y6", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_DXMUX_909, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CEINV_920, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_CLKINV_919, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_SRINV_918, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 : X_FF generic map( LOC => "SLICE_X24Y7", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DYMUX_924, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CEINV_936, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CLKINV_935, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_SRINV_934, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7 : X_FF generic map( LOC => "SLICE_X24Y11", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_DXMUX_1268, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_CLKINV_1271, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_SRINV_1270, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(7) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7 : X_FF generic map( LOC => "SLICE_X53Y7", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_DYMUX_1273, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_CLKINV_1275, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_SRINV_1274, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(7) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0000_Result1 : X_LUT4 generic map( INIT => X"6666", LOC => "SLICE_X53Y7" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(9), ADR1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(8), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0000 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8 : X_FF generic map( LOC => "SLICE_X53Y7", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_DXMUX_1272, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_CLKINV_1275, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_SRINV_1274, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(8) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_RAM_EMPTY_i : X_FF generic map( LOC => "SLICE_X35Y6", INIT => '1' ) port map ( I => s_X2U_EMPTY_DYMUX_1276, CE => VCC, CLK => s_X2U_EMPTY_CLKINV_1277, SET => s_X2U_EMPTY_FFY_SET, RST => GND, O => s_X2U_EMPTY ); s_X2U_EMPTY_FFY_SETOR : X_BUF generic map( LOC => "SLICE_X35Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => s_X2U_EMPTY_FFY_SET ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_rpremod_RAM_RD_EN1 : X_LUT4 generic map( INIT => X"00AA", LOC => "SLICE_X35Y6" ) port map ( ADR0 => s_X2U_RD_EN, ADR1 => VCC, ADR2 => VCC, ADR3 => s_X2U_EMPTY, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN ); Loopback_pr_stateLoop_FFd3 : X_FF generic map( LOC => "SLICE_X29Y7", INIT => '0' ) port map ( I => Loopback_pr_stateLoop_FFd3_DYMUX_1278, CE => Loopback_pr_stateLoop_FFd3_CEINV_1280, CLK => Loopback_pr_stateLoop_FFd3_CLKINV_1279, SET => GND, RST => Loopback_pr_stateLoop_FFd3_FFY_RSTAND_1583, O => Loopback_pr_stateLoop_FFd3_8 ); Loopback_pr_stateLoop_FFd3_FFY_RSTAND : X_INV generic map( LOC => "SLICE_X29Y7", PATHPULSE => 757 ps ) port map ( I => i_nReset_IBUF_4, O => Loopback_pr_stateLoop_FFd3_FFY_RSTAND_1583 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_rpremod_RAM_RD_EN1 : X_LUT4 generic map( INIT => X"1030", LOC => "SLICE_X29Y7" ) port map ( ADR0 => Loopback_pr_stateLoop_FFd2_9, ADR1 => s_U2X_EMPTY, ADR2 => Loopback_pr_stateLoop_FFd3_8, ADR3 => s_X2U_AM_FULL, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2 : X_FF generic map( LOC => "SLICE_X24Y7", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_DXMUX_921, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CEINV_936, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_CLKINV_935, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_SRINV_934, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_5 : X_FF generic map( LOC => "SLICE_X24Y8", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DYMUX_940, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CEINV_952, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CLKINV_951, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_SRINV_950, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4 : X_FF generic map( LOC => "SLICE_X24Y8", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_DXMUX_937, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CEINV_952, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_CLKINV_951, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_SRINV_950, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_7 : X_FF generic map( LOC => "SLICE_X24Y9", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DYMUX_956, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CEINV_968, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CLKINV_967, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_SRINV_966, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(7) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6 : X_FF generic map( LOC => "SLICE_X24Y9", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_DXMUX_953, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CEINV_968, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_CLKINV_967, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_SRINV_966, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(6) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 : X_FF generic map( LOC => "SLICE_X24Y10", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_DXMUX_969, CE => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CEINV_974, CLK => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_CLKINV_973, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_FFX_RSTAND_1584, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(8) ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_FFX_RSTAND : X_BUF generic map( LOC => "SLICE_X24Y10", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_FFX_RSTAND_1584 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 : X_FF generic map( LOC => "SLICE_X31Y4", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DYMUX_979, CE => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CEINV_986, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CLKINV_985, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_SRINV_984, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_INV_0 : X_LUT4 generic map( INIT => X"00FF", LOC => "SLICE_X31Y4" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(0), O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 : X_FF generic map( LOC => "SLICE_X31Y4", INIT => '1' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_DXMUX_975, CE => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CEINV_986, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_CLKINV_985, SET => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_SRINV_984, RST => GND, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 : X_FF generic map( LOC => "SLICE_X31Y5", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_DYMUX_990, CE => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CEINV_1002, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_CLKINV_1001, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_SRINV_1000, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 : X_FF generic map( LOC => "SLICE_X31Y8", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_DXMUX_1035, CE => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CEINV_1040, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_CLKINV_1039, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_FFX_RSTAND_1585, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(8) ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_FFX_RSTAND : X_BUF generic map( LOC => "SLICE_X31Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_FFX_RSTAND_1585 ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_1 : X_FF generic map( LOC => "SLICE_X29Y0", INIT => '1' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DYMUX_1045 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CEINV_1052 , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CLKINV_1051 , SET => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_SRINV_1050 , RST => GND, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Mcount_count_lut_0_INV_0 : X_LUT4 generic map( INIT => X"5555", LOC => "SLICE_X29Y0" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(0), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0 : X_FF generic map( LOC => "SLICE_X29Y0", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_DXMUX_1041 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CEINV_1052 , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_CLKINV_1051 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_SRINV_1050 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_3 : X_FF generic map( LOC => "SLICE_X29Y1", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_DYMUX_1056 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CEINV_1068 , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_CLKINV_1067 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_SRINV_1066 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8 : X_FF generic map( LOC => "SLICE_X29Y4", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_DXMUX_1101 , CE => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CEINV_1106 , CLK => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_CLKINV_1105 , SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_FFX_RSTAND_1586 , O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(8) ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_FFX_RSTAND : X_BUF generic map( LOC => "SLICE_X29Y4", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_FFX_RSTAND_1586 ); Loopback_pr_stateLoop_FFd2 : X_FF generic map( LOC => "SLICE_X28Y7", INIT => '0' ) port map ( I => Loopback_pr_stateLoop_FFd2_DXMUX_1111, CE => VCC, CLK => Loopback_pr_stateLoop_FFd2_CLKINV_1114, SET => GND, RST => Loopback_pr_stateLoop_FFd2_FFX_RSTAND_1587, O => Loopback_pr_stateLoop_FFd2_9 ); Loopback_pr_stateLoop_FFd2_FFX_RSTAND : X_INV generic map( LOC => "SLICE_X28Y7", PATHPULSE => 757 ps ) port map ( I => i_nReset_IBUF_4, O => Loopback_pr_stateLoop_FFd2_FFX_RSTAND_1587 ); FSM_GPIF_v_setup_not0001 : X_LUT4 generic map( INIT => X"AAEA", LOC => "SLICE_X37Y9" ) port map ( ADR0 => N124_0, ADR1 => i_WRU_IBUF_2, ADR2 => i_RDYU_IBUF_3, ADR3 => N4, O => FSM_GPIF_v_setup_not0001_1117 ); FSM_GPIF_pr_state_FFd3_In98 : X_LUT4 generic map( INIT => X"F0F2", LOC => "SLICE_X36Y11" ) port map ( ADR0 => s_U2X_AM_FULL, ADR1 => i_RDYU_IBUF_3, ADR2 => FSM_GPIF_pr_state_FFd3_In98_SW0_O, ADR3 => N350_0, O => FSM_GPIF_pr_state_FFd3_In ); FSM_GPIF_pr_state_FFd3 : X_FF generic map( LOC => "SLICE_X36Y11", INIT => '0' ) port map ( I => FSM_GPIF_pr_state_FFd3_DXMUX_1118, CE => FSM_GPIF_pr_state_FFd3_CEINV_1120, CLK => FSM_GPIF_pr_state_FFd3_CLKINV_1119, SET => GND, RST => FSM_GPIF_pr_state_FFd3_FFX_RSTAND_1588, O => FSM_GPIF_pr_state_FFd3_7 ); FSM_GPIF_pr_state_FFd3_FFX_RSTAND : X_INV generic map( LOC => "SLICE_X36Y11", PATHPULSE => 757 ps ) port map ( I => i_nReset_IBUF_4, O => FSM_GPIF_pr_state_FFd3_FFX_RSTAND_1588 ); FSM_GPIF_Mcount_v_setup_eqn_354 : X_LUT4 generic map( INIT => X"FEAA", LOC => "SLICE_X39Y7" ) port map ( ADR0 => FSM_GPIF_Mcount_v_setup_eqn_3_map16_0, ADR1 => N4, ADR2 => N23, ADR3 => FSM_GPIF_Mcount_v_setup_eqn_332_O, O => FSM_GPIF_Mcount_v_setup_eqn_3 ); FSM_GPIF_v_setup_3 : X_FF generic map( LOC => "SLICE_X39Y7", INIT => '0' ) port map ( I => FSM_GPIF_v_setup_3_DXMUX_1121, CE => FSM_GPIF_v_setup_3_CEINV_1123, CLK => FSM_GPIF_v_setup_3_CLKINV_1122, SET => GND, RST => FSM_GPIF_v_setup_3_FFX_RSTAND_1589, O => FSM_GPIF_v_setup(3) ); FSM_GPIF_v_setup_3_FFX_RSTAND : X_INV generic map( LOC => "SLICE_X39Y7", PATHPULSE => 757 ps ) port map ( I => i_nReset_IBUF_4, O => FSM_GPIF_v_setup_3_FFX_RSTAND_1589 ); FSM_GPIF_pr_state_FFd4_In108 : X_LUT4 generic map( INIT => X"FAFE", LOC => "SLICE_X36Y9" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd4_In_map30_0, ADR1 => FSM_GPIF_pr_state_FFd4_In_map18, ADR2 => FSM_GPIF_pr_state_FFd4_In13_O, ADR3 => FSM_GPIF_pr_state_FFd2_10, O => FSM_GPIF_pr_state_FFd4_In ); FSM_GPIF_pr_state_FFd4_In103 : X_LUT4 generic map( INIT => X"BC00", LOC => "SLICE_X34Y10" ) port map ( ADR0 => s_U2X_AM_FULL, ADR1 => FSM_GPIF_pr_state_FFd2_10, ADR2 => FSM_GPIF_pr_state_FFd3_7, ADR3 => FSM_GPIF_pr_state_FFd4_In_map29, O => FSM_GPIF_pr_state_FFd4_In_map30 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb : X_FF generic map( LOC => "SLICE_X32Y11", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_DYMUX_1299, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_CLKINV_1300, SET => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_FFY_SET, RST => GND, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_FFY_SETOR : X_BUF generic map( LOC => "SLICE_X32Y11", PATHPULSE => 757 ps ) port map ( I => s_FIFOrst_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_FFY_SET ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb : X_FF generic map( LOC => "SLICE_X22Y12", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_DYMUX_1301, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_CLKINV_1302, SET => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_FFY_SET, RST => GND, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_FFY_SETOR : X_BUF generic map( LOC => "SLICE_X22Y12", PATHPULSE => 757 ps ) port map ( I => s_FIFOrst_0, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_FFY_SET ); FSM_GPIF_v_setup_not0001_SW0 : X_LUT4 generic map( INIT => X"5757", LOC => "SLICE_X38Y8" ) port map ( ADR0 => FSM_GPIF_v_setup(3), ADR1 => FSM_GPIF_v_setup(1), ADR2 => FSM_GPIF_v_setup(2), ADR3 => VCC, O => N124 ); FSM_GPIF_pr_state_FFd3_In20_SW0 : X_LUT4 generic map( INIT => X"0FEE", LOC => "SLICE_X38Y10" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd3_7, ADR1 => FSM_GPIF_pr_state_FFd1_5, ADR2 => FSM_GPIF_pr_state_FFd4_6, ADR3 => FSM_GPIF_pr_state_FFd2_10, O => N350 ); FSM_GPIF_pr_state_FFd2_In17 : X_LUT4 generic map( INIT => X"0004", LOC => "SLICE_X33Y10" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd1_5, ADR1 => FSM_GPIF_pr_state_FFd4_6, ADR2 => FSM_GPIF_pr_state_FFd3_7, ADR3 => s_U2X_AM_FULL, O => FSM_GPIF_pr_state_FFd2_In_map8 ); FSM_GPIF_o_RDYX47 : X_LUT4 generic map( INIT => X"4444", LOC => "SLICE_X32Y10" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd3_7, ADR1 => FSM_GPIF_pr_state_FFd2_10, ADR2 => VCC, ADR3 => VCC, O => FSM_GPIF_o_RDYX_map19 ); FSM_GPIF_pr_state_FFd1_In : X_LUT4 generic map( INIT => X"0207", LOC => "SLICE_X37Y5" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd3_7, ADR1 => N90_0, ADR2 => FSM_GPIF_pr_state_FFd4_6, ADR3 => N89, O => FSM_GPIF_pr_state_FFd1_In_1306 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_3 : X_FF generic map( LOC => "SLICE_X28Y12", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_DXMUX_1146, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_CLKINV_1149, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_SRINV_1148, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_3 : X_FF generic map( LOC => "SLICE_X42Y3", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DYMUX_1151, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_CLKINV_1153, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_SRINV_1152, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00041 : X_LUT4 generic map( INIT => X"C33C", LOC => "SLICE_X42Y3" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(4), ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(5), ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0004 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_4 : X_FF generic map( LOC => "SLICE_X42Y3", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DXMUX_1150, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_CLKINV_1153, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_SRINV_1152, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_5 : X_FF generic map( LOC => "SLICE_X29Y12", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DYMUX_1155, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_CLKINV_1158, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_SRINV_1157, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00032 : X_LUT4 generic map( INIT => X"0FF0", LOC => "SLICE_X29Y12" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(4), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0003 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_4 : X_FF generic map( LOC => "SLICE_X29Y12", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_DXMUX_1154, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_CLKINV_1158, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_4_SRINV_1157, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_6 : X_FF generic map( LOC => "SLICE_X44Y2", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_DYMUX_1160, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_CLKINV_1163, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_SRINV_1162, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00032 : X_LUT4 generic map( INIT => X"0FF0", LOC => "SLICE_X44Y2" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(5), ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0003 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_5 : X_FF generic map( LOC => "SLICE_X44Y2", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_DXMUX_1159, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_CLKINV_1163, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_5_SRINV_1162, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00071 : X_LUT4 generic map( INIT => X"9669", LOC => "SLICE_X26Y2" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(5), ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(4), ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1_O, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0007 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_1 : X_FF generic map( LOC => "SLICE_X26Y2", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_DXMUX_1137, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_CLKINV_1138, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_FFX_RSTAND_1590, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(1) ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_FFX_RSTAND : X_BUF generic map( LOC => "SLICE_X26Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_FFX_RSTAND_1590 ); FSM_GPIF_pr_state_FFd2_In32 : X_LUT4 generic map( INIT => X"7770", LOC => "SLICE_X36Y10" ) port map ( ADR0 => i_WRU_IBUF_2, ADR1 => i_RDYU_IBUF_3, ADR2 => FSM_GPIF_pr_state_FFd2_In_map8_0, ADR3 => FSM_GPIF_pr_state_FFd2_In5_O, O => FSM_GPIF_pr_state_FFd2_In ); FSM_GPIF_pr_state_FFd2 : X_FF generic map( LOC => "SLICE_X36Y10", INIT => '0' ) port map ( I => FSM_GPIF_pr_state_FFd2_DXMUX_1139, CE => FSM_GPIF_pr_state_FFd2_CEINV_1141, CLK => FSM_GPIF_pr_state_FFd2_CLKINV_1140, SET => GND, RST => FSM_GPIF_pr_state_FFd2_FFX_RSTAND_1591, O => FSM_GPIF_pr_state_FFd2_10 ); FSM_GPIF_pr_state_FFd2_FFX_RSTAND : X_INV generic map( LOC => "SLICE_X36Y10", PATHPULSE => 757 ps ) port map ( I => i_nReset_IBUF_4, O => FSM_GPIF_pr_state_FFd2_FFX_RSTAND_1591 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_1 : X_FF generic map( LOC => "SLICE_X29Y13", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_DYMUX_1142, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_CLKINV_1143, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_FFY_RSTAND_1592, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(1) ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X29Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_FFY_RSTAND_1592 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_2 : X_FF generic map( LOC => "SLICE_X43Y5", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_2_DYMUX_1144, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_2_CLKINV_1145, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_2_FFY_RSTAND_1593, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(2) ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_2_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X43Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_2_FFY_RSTAND_1593 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_2 : X_FF generic map( LOC => "SLICE_X28Y12", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_DYMUX_1147, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_CLKINV_1149, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_3_SRINV_1148, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00041 : X_LUT4 generic map( INIT => X"9696", LOC => "SLICE_X28Y12" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(4), ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(3), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0004 ); FSM_GPIF_pr_state_FFd4 : X_FF generic map( LOC => "SLICE_X36Y9", INIT => '0' ) port map ( I => FSM_GPIF_pr_state_FFd4_DXMUX_1124, CE => FSM_GPIF_pr_state_FFd4_CEINV_1126, CLK => FSM_GPIF_pr_state_FFd4_CLKINV_1125, SET => GND, RST => FSM_GPIF_pr_state_FFd4_FFX_RSTAND_1594, O => FSM_GPIF_pr_state_FFd4_6 ); FSM_GPIF_pr_state_FFd4_FFX_RSTAND : X_INV generic map( LOC => "SLICE_X36Y9", PATHPULSE => 757 ps ) port map ( I => i_nReset_IBUF_4, O => FSM_GPIF_pr_state_FFd4_FFX_RSTAND_1594 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00071 : X_LUT4 generic map( INIT => X"9669", LOC => "SLICE_X42Y2" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(4), ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1_O, ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(5), ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0007 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_1 : X_FF generic map( LOC => "SLICE_X42Y2", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_DXMUX_1127, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_CLKINV_1128, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_FFX_RSTAND_1595, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(1) ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_FFX_RSTAND : X_BUF generic map( LOC => "SLICE_X42Y2", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_1_FFX_RSTAND_1595 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00071 : X_LUT4 generic map( INIT => X"9669", LOC => "SLICE_X28Y13" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(4), ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0002, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor000611_SW1_O, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0007 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_0 : X_FF generic map( LOC => "SLICE_X28Y13", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_0_DXMUX_1129, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_0_CLKINV_1130, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_0_FFX_RSTAND_1596, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(0) ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_0_FFX_RSTAND : X_BUF generic map( LOC => "SLICE_X28Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_0_FFX_RSTAND_1596 ); FSM_GPIF_Mcount_v_setup_eqn_0 : X_LUT4 generic map( INIT => X"5501", LOC => "SLICE_X36Y4" ) port map ( ADR0 => FSM_GPIF_v_setup(0), ADR1 => FSM_GPIF_v_setup(1), ADR2 => FSM_GPIF_v_setup(2), ADR3 => FSM_GPIF_Mcount_v_setup_eqn_3_map0, O => FSM_GPIF_Mcount_v_setup_eqn_0_1132 ); FSM_GPIF_v_setup_0 : X_FF generic map( LOC => "SLICE_X36Y4", INIT => '0' ) port map ( I => FSM_GPIF_v_setup_0_DXMUX_1131, CE => FSM_GPIF_v_setup_0_CEINV_1134, CLK => FSM_GPIF_v_setup_0_CLKINV_1133, SET => GND, RST => FSM_GPIF_v_setup_0_FFX_RSTAND_1597, O => FSM_GPIF_v_setup(0) ); FSM_GPIF_v_setup_0_FFX_RSTAND : X_INV generic map( LOC => "SLICE_X36Y4", PATHPULSE => 757 ps ) port map ( I => i_nReset_IBUF_4, O => FSM_GPIF_v_setup_0_FFX_RSTAND_1597 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00071 : X_LUT4 generic map( INIT => X"9669", LOC => "SLICE_X43Y6" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002, ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(3), ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor000611_SW1_O, ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0007 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_0 : X_FF generic map( LOC => "SLICE_X43Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_0_DXMUX_1135, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_0_CLKINV_1136, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_0_FFX_RSTAND_1598, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(0) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_0_FFX_RSTAND : X_BUF generic map( LOC => "SLICE_X43Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_0_FFX_RSTAND_1598 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0004_Result1 : X_LUT4 generic map( INIT => X"0FF0", LOC => "SLICE_X51Y3" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(5), ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0004 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4 : X_FF generic map( LOC => "SLICE_X51Y3", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_DXMUX_1256, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_CLKINV_1259, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_SRINV_1258, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4 : X_FF generic map( LOC => "SLICE_X27Y8", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_DYMUX_1261, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_CLKINV_1263, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_SRINV_1262, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0002_Result1 : X_LUT4 generic map( INIT => X"0FF0", LOC => "SLICE_X27Y8" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(5), ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(6), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0002 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5 : X_FF generic map( LOC => "SLICE_X27Y8", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_DXMUX_1260, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_CLKINV_1263, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5_SRINV_1262, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(5) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_5 : X_FF generic map( LOC => "SLICE_X52Y2", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_DYMUX_1265, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_CLKINV_1267, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_SRINV_1266, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(5) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0002_Result1 : X_LUT4 generic map( INIT => X"55AA", LOC => "SLICE_X52Y2" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(7), ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(6), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0002 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6 : X_FF generic map( LOC => "SLICE_X52Y2", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_DXMUX_1264, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_CLKINV_1267, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_SRINV_1266, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(6) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6 : X_FF generic map( LOC => "SLICE_X24Y11", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_DYMUX_1269, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_CLKINV_1271, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_7_SRINV_1270, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(6) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0000_Result1 : X_LUT4 generic map( INIT => X"0FF0", LOC => "SLICE_X24Y11" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(7), ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(8), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0000 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_0 : X_FF generic map( LOC => "SLICE_X25Y4", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_DYMUX_1245, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_CLKINV_1247, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_SRINV_1246, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0006_Result1 : X_LUT4 generic map( INIT => X"3C3C", LOC => "SLICE_X25Y4" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(2), ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(1), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0006 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1 : X_FF generic map( LOC => "SLICE_X25Y4", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_DXMUX_1244, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_CLKINV_1247, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1_SRINV_1246, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_1 : X_FF generic map( LOC => "SLICE_X50Y2", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_DYMUX_1249, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_CLKINV_1251, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_SRINV_1250, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0006_Result1 : X_LUT4 generic map( INIT => X"55AA", LOC => "SLICE_X50Y2" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(2), ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0006 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2 : X_FF generic map( LOC => "SLICE_X50Y2", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_DXMUX_1248, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_CLKINV_1251, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2_SRINV_1250, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_2 : X_FF generic map( LOC => "SLICE_X25Y8", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_DYMUX_1253, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_CLKINV_1255, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_SRINV_1254, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_Mxor_pntr_gc_xor0004_Result1 : X_LUT4 generic map( INIT => X"6666", LOC => "SLICE_X25Y8" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(4), ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(3), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_xor0004 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3 : X_FF generic map( LOC => "SLICE_X25Y8", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_DXMUX_1252, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_CLKINV_1255, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3_SRINV_1254, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_3 : X_FF generic map( LOC => "SLICE_X51Y3", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_DYMUX_1257, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_CLKINV_1259, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_SRINV_1258, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_6 : X_FF generic map( LOC => "SLICE_X30Y15", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_DYMUX_1165, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_CLKINV_1167, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_SRINV_1166, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(6) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00001 : X_LUT4 generic map( INIT => X"5A5A", LOC => "SLICE_X30Y15" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(8), ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(7), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0000 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_7 : X_FF generic map( LOC => "SLICE_X30Y15", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_DXMUX_1164, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_CLKINV_1167, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_7_SRINV_1166, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(7) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_7 : X_FF generic map( LOC => "SLICE_X44Y3", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_DYMUX_1169, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_CLKINV_1171, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_SRINV_1170, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(7) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor00001 : X_LUT4 generic map( INIT => X"0FF0", LOC => "SLICE_X44Y3" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(8), ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(9), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0000 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_8 : X_FF generic map( LOC => "SLICE_X44Y3", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_DXMUX_1168, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_CLKINV_1171, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_SRINV_1170, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(8) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_0 : X_FF generic map( LOC => "SLICE_X50Y10", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_DYMUX_1173, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_CLKINV_1175, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_SRINV_1174, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0006_Result1 : X_LUT4 generic map( INIT => X"0FF0", LOC => "SLICE_X50Y10" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(1), ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(2), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0006 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1 : X_FF generic map( LOC => "SLICE_X50Y10", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_DXMUX_1172, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_CLKINV_1175, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_SRINV_1174, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1 : X_FF generic map( LOC => "SLICE_X14Y4", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_DYMUX_1177, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_CLKINV_1179, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_SRINV_1178, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0006_Result1 : X_LUT4 generic map( INIT => X"0FF0", LOC => "SLICE_X14Y4" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(2), ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0006 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2 : X_FF generic map( LOC => "SLICE_X14Y4", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_DXMUX_1176, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_CLKINV_1179, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2_SRINV_1178, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_2 : X_FF generic map( LOC => "SLICE_X52Y10", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_DYMUX_1181, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_CLKINV_1183, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_SRINV_1182, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0004_Result1 : X_LUT4 generic map( INIT => X"33CC", LOC => "SLICE_X52Y10" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(4), ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(3), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0004 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3 : X_FF generic map( LOC => "SLICE_X52Y10", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_DXMUX_1180, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_CLKINV_1183, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_SRINV_1182, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3 : X_FF generic map( LOC => "SLICE_X14Y11", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_DYMUX_1185, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_CLKINV_1187, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_SRINV_1186, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0004_Result1 : X_LUT4 generic map( INIT => X"6666", LOC => "SLICE_X14Y11" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(4), ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(5), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0004 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4 : X_FF generic map( LOC => "SLICE_X14Y11", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_DXMUX_1184, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_CLKINV_1187, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4_SRINV_1186, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_4 : X_FF generic map( LOC => "SLICE_X52Y11", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_DYMUX_1189, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_CLKINV_1191, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_SRINV_1190, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0002_Result1 : X_LUT4 generic map( INIT => X"0FF0", LOC => "SLICE_X52Y11" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(6), ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(5), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0002 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5 : X_FF generic map( LOC => "SLICE_X52Y11", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_DXMUX_1188, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_CLKINV_1191, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_SRINV_1190, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5 : X_FF generic map( LOC => "SLICE_X15Y10", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_DYMUX_1193, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_CLKINV_1195, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_SRINV_1194, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0002_Result1 : X_LUT4 generic map( INIT => X"33CC", LOC => "SLICE_X15Y10" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(6), ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(7), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0002 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6 : X_FF generic map( LOC => "SLICE_X15Y10", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_DXMUX_1192, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_CLKINV_1195, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6_SRINV_1194, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_6 : X_FF generic map( LOC => "SLICE_X53Y8", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_DYMUX_1197, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_CLKINV_1199, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_SRINV_1198, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0000_Result1 : X_LUT4 generic map( INIT => X"5A5A", LOC => "SLICE_X53Y8" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(7), ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(8), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0000 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7 : X_FF generic map( LOC => "SLICE_X53Y8", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_DXMUX_1196, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_CLKINV_1199, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_SRINV_1198, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(7) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7 : X_FF generic map( LOC => "SLICE_X15Y8", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_DYMUX_1201, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_CLKINV_1203, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_SRINV_1202, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(7) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_Mxor_pntr_gc_xor0000_Result1 : X_LUT4 generic map( INIT => X"3C3C", LOC => "SLICE_X15Y8" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(8), ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(9), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_xor0000 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8 : X_FF generic map( LOC => "SLICE_X15Y8", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_DXMUX_1200, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_CLKINV_1203, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_SRINV_1202, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(8) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_almost_full_i : X_FF generic map( LOC => "SLICE_X28Y6", INIT => '0' ) port map ( I => s_X2U_AM_FULL_DYMUX_1204, CE => s_X2U_AM_FULL_CEINVNOT, CLK => s_X2U_AM_FULL_CLKINV_1205, SET => s_X2U_AM_FULL_FFY_SET, RST => GND, O => s_X2U_AM_FULL ); s_X2U_AM_FULL_FFY_SETOR : X_BUF generic map( LOC => "SLICE_X28Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => s_X2U_AM_FULL_FFY_SET ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_wpremod_RAM_WR_EN1 : X_LUT4 generic map( INIT => X"4400", LOC => "SLICE_X28Y6" ) port map ( ADR0 => F_OUT_full, ADR1 => Loopback_pr_stateLoop_FFd3_8, ADR2 => VCC, ADR3 => Loopback_pr_stateLoop_FFd2_9, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_almost_full_i_or00001 : X_LUT4 generic map( INIT => X"CECE", LOC => "SLICE_X30Y16" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af2, ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_comp_af1, ADR2 => F_IN_full, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_almost_full_i_or0000 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aflogic_almost_full_i : X_FF generic map( LOC => "SLICE_X30Y16", INIT => '0' ) port map ( I => s_U2X_AM_FULL_DYMUX_1206, CE => s_U2X_AM_FULL_CEINVNOT, CLK => s_U2X_AM_FULL_CLKINV_1207, SET => s_U2X_AM_FULL_FFY_SET, RST => GND, O => s_U2X_AM_FULL ); s_U2X_AM_FULL_FFY_SETOR : X_BUF generic map( LOC => "SLICE_X30Y16", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => s_U2X_AM_FULL_FFY_SET ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_1 : X_FF generic map( LOC => "SLICE_X42Y7", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_DYMUX_1208, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_CLKINV_1209, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_FFY_RSTAND_1599, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(1) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X42Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_1_FFY_RSTAND_1599 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_2 : X_FF generic map( LOC => "SLICE_X41Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_DYMUX_1211, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_CLKINV_1213, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_SRINV_1212, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00041 : X_LUT4 generic map( INIT => X"9966", LOC => "SLICE_X41Y6" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(3), ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(4), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0004 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_3 : X_FF generic map( LOC => "SLICE_X41Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_DXMUX_1210, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_CLKINV_1213, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_3_SRINV_1212, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_2 : X_FF generic map( LOC => "SLICE_X27Y2", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_2_DYMUX_1214, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_2_CLKINV_1215, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_2_FFY_RSTAND_1600, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(2) ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_2_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X27Y2", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_2_FFY_RSTAND_1600 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_3 : X_FF generic map( LOC => "SLICE_X27Y3", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DYMUX_1217, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_CLKINV_1219, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_SRINV_1218, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00041 : X_LUT4 generic map( INIT => X"A55A", LOC => "SLICE_X27Y3" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(5), ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(4), ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0004 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_4 : X_FF generic map( LOC => "SLICE_X27Y3", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DXMUX_1216, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_CLKINV_1219, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_SRINV_1218, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_5 : X_FF generic map( LOC => "SLICE_X40Y7", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DYMUX_1221, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_CLKINV_1224, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_SRINV_1223, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(5) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00032 : X_LUT4 generic map( INIT => X"3C3C", LOC => "SLICE_X40Y7" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(4), ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0003 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_4 : X_FF generic map( LOC => "SLICE_X40Y7", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_DXMUX_1220, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_CLKINV_1224, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_SRINV_1223, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_6 : X_FF generic map( LOC => "SLICE_X40Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_DYMUX_1226, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_CLKINV_1228, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_SRINV_1227, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00001 : X_LUT4 generic map( INIT => X"55AA", LOC => "SLICE_X40Y6" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(7), ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(8), O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0000 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_7 : X_FF generic map( LOC => "SLICE_X40Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_DXMUX_1225, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_CLKINV_1228, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_SRINV_1227, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(7) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_6 : X_FF generic map( LOC => "SLICE_X24Y5", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_DYMUX_1230, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_CLKINV_1233, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_SRINV_1232, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(6) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00032 : X_LUT4 generic map( INIT => X"5A5A", LOC => "SLICE_X24Y5" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(5), ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0003 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_5 : X_FF generic map( LOC => "SLICE_X24Y5", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_DXMUX_1229, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_CLKINV_1233, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_5_SRINV_1232, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_7 : X_FF generic map( LOC => "SLICE_X25Y3", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_DYMUX_1235, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_CLKINV_1237, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_SRINV_1236, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(7) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor00001 : X_LUT4 generic map( INIT => X"0FF0", LOC => "SLICE_X25Y3" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(9), ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(8), O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0000 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_8 : X_FF generic map( LOC => "SLICE_X25Y3", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_DXMUX_1234, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_CLKINV_1237, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_SRINV_1236, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(8) ); FSM_GPIF_v_setup_1 : X_FF generic map( LOC => "SLICE_X38Y7", INIT => '0' ) port map ( I => FSM_GPIF_v_setup_1_DYMUX_1238, CE => FSM_GPIF_v_setup_1_CEINV_1241, CLK => FSM_GPIF_v_setup_1_CLKINV_1240, SET => GND, RST => FSM_GPIF_v_setup_1_FFY_RSTAND_1601, O => FSM_GPIF_v_setup(1) ); FSM_GPIF_v_setup_1_FFY_RSTAND : X_INV generic map( LOC => "SLICE_X38Y7", PATHPULSE => 757 ps ) port map ( I => i_nReset_IBUF_4, O => FSM_GPIF_v_setup_1_FFY_RSTAND_1601 ); FSM_GPIF_Mcount_v_setup_eqn_2_SW0 : X_LUT4 generic map( INIT => X"33FF", LOC => "SLICE_X38Y7" ) port map ( ADR0 => VCC, ADR1 => FSM_GPIF_v_setup(1), ADR2 => VCC, ADR3 => FSM_GPIF_v_setup(0), O => N120 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_aelogic_almost_empty_i : X_FF generic map( LOC => "SLICE_X25Y5", INIT => '1' ) port map ( I => s_U2X_AM_EMPTY_DYMUX_1242, CE => s_U2X_AM_EMPTY_CEINVNOT, CLK => s_U2X_AM_EMPTY_CLKINV_1243, SET => s_U2X_AM_EMPTY_FFY_SET, RST => GND, O => s_U2X_AM_EMPTY ); s_U2X_AM_EMPTY_FFY_SETOR : X_BUF generic map( LOC => "SLICE_X25Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => s_U2X_AM_EMPTY_FFY_SET ); F_IN_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en1 : X_LUT4 generic map( INIT => X"F0FC", LOC => "SLICE_X25Y5" ) port map ( ADR0 => VCC, ADR1 => s_U2X_RD_EN, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0, ADR3 => s_U2X_EMPTY, O => F_IN_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en ); Loopback_o_X2U_DATA_16 : X_FF generic map( LOC => "SLICE_X5Y0", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_17_DYMUX_1328, CE => VCC, CLK => Loopback_o_X2U_DATA_17_CLKINV_1329, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(16) ); Loopback_o_X2U_DATA_17 : X_FF generic map( LOC => "SLICE_X5Y0", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_17_DXMUX_1327, CE => VCC, CLK => Loopback_o_X2U_DATA_17_CLKINV_1329, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(17) ); Loopback_o_X2U_DATA_24 : X_FF generic map( LOC => "SLICE_X5Y5", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_25_DYMUX_1331, CE => VCC, CLK => Loopback_o_X2U_DATA_25_CLKINV_1332, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(24) ); Loopback_o_X2U_DATA_25 : X_FF generic map( LOC => "SLICE_X5Y5", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_25_DXMUX_1330, CE => VCC, CLK => Loopback_o_X2U_DATA_25_CLKINV_1332, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(25) ); Loopback_o_X2U_DATA_18 : X_FF generic map( LOC => "SLICE_X4Y0", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_19_DYMUX_1334, CE => VCC, CLK => Loopback_o_X2U_DATA_19_CLKINV_1335, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(18) ); Loopback_o_X2U_DATA_19 : X_FF generic map( LOC => "SLICE_X4Y0", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_19_DXMUX_1333, CE => VCC, CLK => Loopback_o_X2U_DATA_19_CLKINV_1335, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(19) ); Loopback_o_X2U_DATA_26 : X_FF generic map( LOC => "SLICE_X4Y4", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_27_DYMUX_1337, CE => VCC, CLK => Loopback_o_X2U_DATA_27_CLKINV_1338, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(26) ); Loopback_o_X2U_DATA_27 : X_FF generic map( LOC => "SLICE_X4Y4", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_27_DXMUX_1336, CE => VCC, CLK => Loopback_o_X2U_DATA_27_CLKINV_1338, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(27) ); Loopback_o_X2U_DATA_28 : X_FF generic map( LOC => "SLICE_X5Y7", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_29_DYMUX_1340, CE => VCC, CLK => Loopback_o_X2U_DATA_29_CLKINV_1341, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(28) ); Loopback_o_X2U_DATA_29 : X_FF generic map( LOC => "SLICE_X5Y7", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_29_DXMUX_1339, CE => VCC, CLK => Loopback_o_X2U_DATA_29_CLKINV_1341, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(29) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_8 : X_FF generic map( LOC => "SLICE_X30Y17", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_DYMUX_1342, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_CLKINV_1343, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_FFY_RSTAND_1602, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w(8) ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X30Y17", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_FFY_RSTAND_1602 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_9 : X_FF generic map( LOC => "SLICE_X45Y5", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_9_DYMUX_1344, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_9_CLKINV_1345, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_9_FFY_RSTAND_1603, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w(9) ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_9_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X45Y5", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_w_9_FFY_RSTAND_1603 ); FSM_GPIF_pr_state_FFd1 : X_FF generic map( LOC => "SLICE_X37Y5", INIT => '0' ) port map ( I => FSM_GPIF_pr_state_FFd1_DXMUX_1305, CE => FSM_GPIF_pr_state_FFd1_CEINV_1308, CLK => FSM_GPIF_pr_state_FFd1_CLKINV_1307, SET => GND, RST => FSM_GPIF_pr_state_FFd1_FFX_RSTAND_1604, O => FSM_GPIF_pr_state_FFd1_5 ); FSM_GPIF_pr_state_FFd1_FFX_RSTAND : X_INV generic map( LOC => "SLICE_X37Y5", PATHPULSE => 757 ps ) port map ( I => i_nReset_IBUF_4, O => FSM_GPIF_pr_state_FFd1_FFX_RSTAND_1604 ); FSM_GPIF_s_bus_trans_dir_inv1 : X_LUT4 generic map( INIT => X"0F8F", LOC => "SLICE_X38Y0" ) port map ( ADR0 => i_WRU_IBUF_2, ADR1 => i_RDYU_IBUF_3, ADR2 => FSM_GPIF_pr_state_FFd1_5, ADR3 => FSM_GPIF_pr_state_FFd4_6, O => FSM_GPIF_s_bus_trans_dir_inv ); Loopback_o_X2U_DATA_10 : X_FF generic map( LOC => "SLICE_X5Y4", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_11_DYMUX_1310, CE => VCC, CLK => Loopback_o_X2U_DATA_11_CLKINV_1311, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(10) ); Loopback_o_X2U_DATA_11 : X_FF generic map( LOC => "SLICE_X5Y4", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_11_DXMUX_1309, CE => VCC, CLK => Loopback_o_X2U_DATA_11_CLKINV_1311, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(11) ); Loopback_o_X2U_DATA_12 : X_FF generic map( LOC => "SLICE_X5Y6", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_13_DYMUX_1313, CE => VCC, CLK => Loopback_o_X2U_DATA_13_CLKINV_1314, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(12) ); Loopback_o_X2U_DATA_13 : X_FF generic map( LOC => "SLICE_X5Y6", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_13_DXMUX_1312, CE => VCC, CLK => Loopback_o_X2U_DATA_13_CLKINV_1314, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(13) ); Loopback_o_X2U_DATA_20 : X_FF generic map( LOC => "SLICE_X5Y2", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_21_DYMUX_1316, CE => VCC, CLK => Loopback_o_X2U_DATA_21_CLKINV_1317, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(20) ); Loopback_o_X2U_DATA_21 : X_FF generic map( LOC => "SLICE_X5Y2", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_21_DXMUX_1315, CE => VCC, CLK => Loopback_o_X2U_DATA_21_CLKINV_1317, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(21) ); Loopback_o_X2U_DATA_14 : X_FF generic map( LOC => "SLICE_X4Y6", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_15_DYMUX_1319, CE => VCC, CLK => Loopback_o_X2U_DATA_15_CLKINV_1320, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(14) ); Loopback_o_X2U_DATA_15 : X_FF generic map( LOC => "SLICE_X4Y6", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_15_DXMUX_1318, CE => VCC, CLK => Loopback_o_X2U_DATA_15_CLKINV_1320, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(15) ); Loopback_o_X2U_DATA_22 : X_FF generic map( LOC => "SLICE_X4Y2", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_23_DYMUX_1322, CE => VCC, CLK => Loopback_o_X2U_DATA_23_CLKINV_1323, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(22) ); Loopback_o_X2U_DATA_23 : X_FF generic map( LOC => "SLICE_X4Y2", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_23_DXMUX_1321, CE => VCC, CLK => Loopback_o_X2U_DATA_23_CLKINV_1323, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(23) ); Loopback_o_X2U_DATA_30 : X_FF generic map( LOC => "SLICE_X4Y7", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_31_DYMUX_1325, CE => VCC, CLK => Loopback_o_X2U_DATA_31_CLKINV_1326, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(30) ); Loopback_o_X2U_DATA_31 : X_FF generic map( LOC => "SLICE_X4Y7", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_31_DXMUX_1324, CE => VCC, CLK => Loopback_o_X2U_DATA_31_CLKINV_1326, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(31) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_RAM_FULL_i : X_FF generic map( LOC => "SLICE_X26Y17", INIT => '0' ) port map ( I => F_IN_full_DYMUX_1281, CE => VCC, CLK => F_IN_full_CLKINV_1282, SET => F_IN_full_FFY_SET, RST => GND, O => F_IN_full ); F_IN_full_FFY_SETOR : X_BUF generic map( LOC => "SLICE_X26Y17", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_full_FFY_SET ); FSM_GPIF_pr_state_Out41 : X_LUT4 generic map( INIT => X"00A0", LOC => "SLICE_X37Y11" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd2_10, ADR1 => VCC, ADR2 => FSM_GPIF_pr_state_FFd4_6, ADR3 => FSM_GPIF_pr_state_FFd3_7, O => o_LEDrx_OBUF_1283 ); FSM_GPIF_o_RDYX19 : X_LUT4 generic map( INIT => X"3031", LOC => "SLICE_X37Y10" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd1_5, ADR1 => s_U2X_AM_FULL, ADR2 => FSM_GPIF_pr_state_FFd2_10, ADR3 => FSM_GPIF_pr_state_FFd3_7, O => FSM_GPIF_o_RDYX_map9 ); Loopback_o_X2U_DATA_0 : X_FF generic map( LOC => "SLICE_X4Y1", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_1_DYMUX_1285, CE => VCC, CLK => Loopback_o_X2U_DATA_1_CLKINV_1286, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(0) ); Loopback_o_X2U_DATA_1 : X_FF generic map( LOC => "SLICE_X4Y1", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_1_DXMUX_1284, CE => VCC, CLK => Loopback_o_X2U_DATA_1_CLKINV_1286, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(1) ); Loopback_o_X2U_DATA_2 : X_FF generic map( LOC => "SLICE_X5Y1", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_3_DYMUX_1288, CE => VCC, CLK => Loopback_o_X2U_DATA_3_CLKINV_1289, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(2) ); Loopback_o_X2U_DATA_3 : X_FF generic map( LOC => "SLICE_X5Y1", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_3_DXMUX_1287, CE => VCC, CLK => Loopback_o_X2U_DATA_3_CLKINV_1289, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(3) ); Loopback_o_X2U_DATA_4 : X_FF generic map( LOC => "SLICE_X4Y3", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_5_DYMUX_1291, CE => VCC, CLK => Loopback_o_X2U_DATA_5_CLKINV_1292, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(4) ); Loopback_o_X2U_DATA_5 : X_FF generic map( LOC => "SLICE_X4Y3", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_5_DXMUX_1290, CE => VCC, CLK => Loopback_o_X2U_DATA_5_CLKINV_1292, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(5) ); Loopback_o_X2U_DATA_6 : X_FF generic map( LOC => "SLICE_X5Y3", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_7_DYMUX_1294, CE => VCC, CLK => Loopback_o_X2U_DATA_7_CLKINV_1295, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(6) ); Loopback_o_X2U_DATA_7 : X_FF generic map( LOC => "SLICE_X5Y3", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_7_DXMUX_1293, CE => VCC, CLK => Loopback_o_X2U_DATA_7_CLKINV_1295, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(7) ); Loopback_o_X2U_DATA_8 : X_FF generic map( LOC => "SLICE_X4Y5", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_9_DYMUX_1297, CE => VCC, CLK => Loopback_o_X2U_DATA_9_CLKINV_1298, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(8) ); Loopback_o_X2U_DATA_9 : X_FF generic map( LOC => "SLICE_X4Y5", INIT => '0' ) port map ( I => Loopback_o_X2U_DATA_9_DXMUX_1296, CE => VCC, CLK => Loopback_o_X2U_DATA_9_CLKINV_1298, SET => GND, RST => GND, O => Loopback_o_X2U_DATA(9) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2 : X_FF generic map( LOC => "SLICE_X51Y2", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_DXMUX_1404, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_CLKINV_1407, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_SRINV_1406, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_int_0 : X_FF generic map( LOC => "SLICE_X34Y11", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_DYMUX_1408, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_CLKINV_1409, SET => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_FFY_SET, RST => GND, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_FFY_SETOR : X_BUF generic map( LOC => "SLICE_X34Y11", PATHPULSE => 757 ps ) port map ( I => s_FIFOrst_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_FFY_SET ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2 : X_FF generic map( LOC => "SLICE_X26Y11", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_DYMUX_1411, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_CLKINV_1413, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_SRINV_1412, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3 : X_FF generic map( LOC => "SLICE_X26Y11", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_DXMUX_1410, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_CLKINV_1413, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3_SRINV_1412, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_int_0 : X_FF generic map( LOC => "SLICE_X27Y9", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_DYMUX_1414, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_CLKINV_1415, SET => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_FFY_SET, RST => GND, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_FFY_SETOR : X_BUF generic map( LOC => "SLICE_X27Y9", PATHPULSE => 757 ps ) port map ( I => s_FIFOrst_0, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_FFY_SET ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_3 : X_FF generic map( LOC => "SLICE_X50Y3", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_DYMUX_1417, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_CLKINV_1419, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_SRINV_1418, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4 : X_FF generic map( LOC => "SLICE_X50Y3", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_DXMUX_1416, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_CLKINV_1419, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_SRINV_1418, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4 : X_FF generic map( LOC => "SLICE_X26Y10", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_DYMUX_1421, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_CLKINV_1423, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_SRINV_1422, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5 : X_FF generic map( LOC => "SLICE_X26Y10", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_DXMUX_1420, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_CLKINV_1423, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5_SRINV_1422, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(5) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8 : X_FF generic map( LOC => "SLICE_X52Y12", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_DYMUX_1396, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_CLKINV_1397, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_FFY_RSTAND_1605, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(8) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X52Y12", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_8_FFY_RSTAND_1605 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_9 : X_FF generic map( LOC => "SLICE_X16Y8", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_9_DYMUX_1398, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_9_CLKINV_1399, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_9_FFY_RSTAND_1606, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc(9) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_9_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X16Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_9_FFY_RSTAND_1606 ); FSM_GPIF_o_WRX_SW0 : X_LUT4 generic map( INIT => X"FDDD", LOC => "SLICE_X39Y4" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd3_7, ADR1 => FSM_GPIF_pr_state_FFd2_10, ADR2 => i_WRU_IBUF_2, ADR3 => i_RDYU_IBUF_3, O => N30 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_0 : X_FF generic map( LOC => "SLICE_X26Y7", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_DYMUX_1401, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_CLKINV_1403, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_SRINV_1402, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1 : X_FF generic map( LOC => "SLICE_X26Y7", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_DXMUX_1400, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_CLKINV_1403, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1_SRINV_1402, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_1 : X_FF generic map( LOC => "SLICE_X51Y2", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_DYMUX_1405, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_CLKINV_1407, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_2_SRINV_1406, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6 : X_FF generic map( LOC => "SLICE_X52Y9", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_DYMUX_1379, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_CLKINV_1381, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_SRINV_1380, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7 : X_FF generic map( LOC => "SLICE_X52Y9", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_DXMUX_1378, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_CLKINV_1381, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_SRINV_1380, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(7) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7 : X_FF generic map( LOC => "SLICE_X23Y8", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_DYMUX_1383, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_CLKINV_1385, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_SRINV_1384, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(7) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8 : X_FF generic map( LOC => "SLICE_X23Y8", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_DXMUX_1382, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_CLKINV_1385, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_SRINV_1384, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(8) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8 : X_FF generic map( LOC => "SLICE_X52Y13", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_DYMUX_1386, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_CLKINV_1387, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_FFY_RSTAND_1607, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(8) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X52Y13", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_8_FFY_RSTAND_1607 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_9 : X_FF generic map( LOC => "SLICE_X22Y9", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_9_DYMUX_1388, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_9_CLKINV_1389, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_9_FFY_RSTAND_1608, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(9) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_9_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X22Y9", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_9_FFY_RSTAND_1608 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg : X_FF generic map( LOC => "SLICE_X32Y8", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_DYMUX_1390, CE => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CEINV_1392, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CLKINV_1391, SET => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_FFY_SET, RST => GND, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_11 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_FFY_SETOR : X_BUF generic map( LOC => "SLICE_X32Y8", PATHPULSE => 757 ps ) port map ( I => s_FIFOrst_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_FFY_SET ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg : X_FF generic map( LOC => "SLICE_X22Y13", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_DYMUX_1393, CE => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CEINV_1395, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_CLKINV_1394, SET => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_FFY_SET, RST => GND, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_12 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_FFY_SETOR : X_BUF generic map( LOC => "SLICE_X22Y13", PATHPULSE => 757 ps ) port map ( I => s_FIFOrst_0, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_FFY_SET ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2 : X_FF generic map( LOC => "SLICE_X52Y7", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_DYMUX_1363, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_CLKINV_1365, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_SRINV_1364, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3 : X_FF generic map( LOC => "SLICE_X52Y7", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_DXMUX_1362, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_CLKINV_1365, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_SRINV_1364, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3 : X_FF generic map( LOC => "SLICE_X18Y10", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_DYMUX_1367, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_CLKINV_1369, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_SRINV_1368, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4 : X_FF generic map( LOC => "SLICE_X18Y10", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_DXMUX_1366, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_CLKINV_1369, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4_SRINV_1368, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_4 : X_FF generic map( LOC => "SLICE_X52Y8", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_DYMUX_1371, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_CLKINV_1373, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_SRINV_1372, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5 : X_FF generic map( LOC => "SLICE_X52Y8", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_DXMUX_1370, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_CLKINV_1373, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_SRINV_1372, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5 : X_FF generic map( LOC => "SLICE_X22Y11", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_DYMUX_1375, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_CLKINV_1377, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_SRINV_1376, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6 : X_FF generic map( LOC => "SLICE_X22Y11", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_DXMUX_1374, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_CLKINV_1377, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_6_SRINV_1376, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG_i1 : X_LUT4 generic map( INIT => X"FF40", LOC => "SLICE_X30Y6" ) port map ( ADR0 => F_OUT_full, ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full2, ADR2 => s_X2U_WR_EN, ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_comp_full1, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_RAM_FULL_i : X_FF generic map( LOC => "SLICE_X30Y6", INIT => '0' ) port map ( I => F_OUT_full_DXMUX_1346, CE => VCC, CLK => F_OUT_full_CLKINV_1347, SET => F_OUT_full_FFX_SET, RST => GND, O => F_OUT_full ); F_OUT_full_FFX_SETOR : X_BUF generic map( LOC => "SLICE_X30Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_full_FFX_SET ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg : X_FF generic map( LOC => "SLICE_X39Y9", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_DYMUX_1348, CE => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CEINV_1350, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CLKINV_1349, SET => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_FFY_SET, RST => GND, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_13 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_FFY_SETOR : X_BUF generic map( LOC => "SLICE_X39Y9", PATHPULSE => 757 ps ) port map ( I => s_FIFOrst_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_FFY_SET ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg : X_FF generic map( LOC => "SLICE_X26Y9", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_DYMUX_1351, CE => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CEINV_1353, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_CLKINV_1352, SET => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_FFY_SET, RST => GND, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_14 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_FFY_SETOR : X_BUF generic map( LOC => "SLICE_X26Y9", PATHPULSE => 757 ps ) port map ( I => s_FIFOrst_0, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_FFY_SET ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_0 : X_FF generic map( LOC => "SLICE_X50Y4", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_DYMUX_1355, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_CLKINV_1357, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_SRINV_1356, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1 : X_FF generic map( LOC => "SLICE_X50Y4", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_DXMUX_1354, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_CLKINV_1357, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_SRINV_1356, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1 : X_FF generic map( LOC => "SLICE_X23Y5", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_DYMUX_1359, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_CLKINV_1361, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_SRINV_1360, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2 : X_FF generic map( LOC => "SLICE_X23Y5", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_DXMUX_1358, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_CLKINV_1361, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_2_SRINV_1360, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_5 : X_FF generic map( LOC => "SLICE_X52Y3", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_DYMUX_1425, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_CLKINV_1427, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_SRINV_1426, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(5) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6 : X_FF generic map( LOC => "SLICE_X52Y3", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_DXMUX_1424, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_CLKINV_1427, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_SRINV_1426, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(6) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6 : X_FF generic map( LOC => "SLICE_X24Y13", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_DYMUX_1429, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_CLKINV_1431, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_SRINV_1430, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(6) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7 : X_FF generic map( LOC => "SLICE_X24Y13", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_DXMUX_1428, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_CLKINV_1431, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7_SRINV_1430, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(7) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_7 : X_FF generic map( LOC => "SLICE_X52Y6", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_DYMUX_1433, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_CLKINV_1435, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_SRINV_1434, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(7) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8 : X_FF generic map( LOC => "SLICE_X52Y6", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_DXMUX_1432, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_CLKINV_1435, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_SRINV_1434, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(8) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8 : X_FF generic map( LOC => "SLICE_X25Y12", XON => FALSE, INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_DYMUX_1436, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_CLKINV_1437, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_FFY_RSTAND_1609, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(8) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X25Y12", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_FFY_RSTAND_1609 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9 : X_FF generic map( LOC => "SLICE_X49Y6", XON => FALSE, INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9_DYMUX_1438, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9_CLKINV_1439, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9_FFY_RSTAND_1610, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x(9) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X49Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_9_FFY_RSTAND_1610 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_int_0_1 : X_FF generic map( LOC => "SLICE_X30Y8", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_DYMUX_1440, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_CLKINV_1441, SET => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_FFY_SET, RST => GND, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0 ); F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_FFY_SETOR : X_BUF generic map( LOC => "SLICE_X30Y8", PATHPULSE => 757 ps ) port map ( I => s_FIFOrst_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_FFY_SET ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_int_0_1 : X_FF generic map( LOC => "SLICE_X26Y8", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_DYMUX_1442, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_CLKINV_1443, SET => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_FFY_SET, RST => GND, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0 ); F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_FFY_SETOR : X_BUF generic map( LOC => "SLICE_X26Y8", PATHPULSE => 757 ps ) port map ( I => s_FIFOrst_0, O => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_0_FFY_SET ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_0 : X_FF generic map( LOC => "SLICE_X47Y5", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_DYMUX_1445, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_CLKINV_1447, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_SRINV_1446, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(0) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1 : X_FF generic map( LOC => "SLICE_X47Y5", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_DXMUX_1444, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_CLKINV_1447, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_SRINV_1446, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1 : X_FF generic map( LOC => "SLICE_X22Y5", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_DYMUX_1449, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_CLKINV_1451, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_SRINV_1450, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(1) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2 : X_FF generic map( LOC => "SLICE_X22Y5", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_DXMUX_1448, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_CLKINV_1451, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2_SRINV_1450, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_2 : X_FF generic map( LOC => "SLICE_X53Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_DYMUX_1453, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_CLKINV_1455, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_SRINV_1454, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(2) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3 : X_FF generic map( LOC => "SLICE_X53Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_DXMUX_1452, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_CLKINV_1455, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_SRINV_1454, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3 : X_FF generic map( LOC => "SLICE_X23Y6", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_DYMUX_1457, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_CLKINV_1459, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_SRINV_1458, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(3) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4 : X_FF generic map( LOC => "SLICE_X23Y6", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_DXMUX_1456, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_CLKINV_1459, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4_SRINV_1458, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_4 : X_FF generic map( LOC => "SLICE_X47Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_DYMUX_1461, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_CLKINV_1463, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_SRINV_1462, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(4) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5 : X_FF generic map( LOC => "SLICE_X47Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_DXMUX_1460, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_CLKINV_1463, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_SRINV_1462, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5 : X_FF generic map( LOC => "SLICE_X22Y7", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_DYMUX_1465, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_CLKINV_1467, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_SRINV_1466, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(5) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6 : X_FF generic map( LOC => "SLICE_X22Y7", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_DXMUX_1464, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_CLKINV_1467, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6_SRINV_1466, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_6 : X_FF generic map( LOC => "SLICE_X45Y7", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_DYMUX_1469, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_CLKINV_1471, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_SRINV_1470, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(6) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7 : X_FF generic map( LOC => "SLICE_X45Y7", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_DXMUX_1468, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_CLKINV_1471, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_SRINV_1470, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(7) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7 : X_FF generic map( LOC => "SLICE_X22Y6", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_DYMUX_1473, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_CLKINV_1475, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_SRINV_1474, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(7) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8 : X_FF generic map( LOC => "SLICE_X22Y6", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_DXMUX_1472, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_CLKINV_1475, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_SRINV_1474, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(8) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8 : X_FF generic map( LOC => "SLICE_X50Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_DYMUX_1476, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_CLKINV_1477, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_FFY_RSTAND_1611, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(8) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X50Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_8_FFY_RSTAND_1611 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_9 : X_FF generic map( LOC => "SLICE_X22Y8", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_9_DYMUX_1478, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_9_CLKINV_1479, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_9_FFY_RSTAND_1612, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2(9) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_9_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X22Y8", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_9_FFY_RSTAND_1612 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_8 : X_FF generic map( LOC => "SLICE_X45Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_DYMUX_1480, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_CLKINV_1481, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_FFY_RSTAND_1613, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r(8) ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X45Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_r_8_FFY_RSTAND_1613 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_9 : X_FF generic map( LOC => "SLICE_X29Y5", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_9_DYMUX_1482, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_9_CLKINV_1483, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_9_FFY_RSTAND_1614, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r(9) ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_9_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X29Y5", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_r_9_FFY_RSTAND_1614 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_EMPTY_NONREG_i1 : X_LUT4 generic map( INIT => X"FF20", LOC => "SLICE_X27Y7" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out, ADR1 => s_U2X_EMPTY, ADR2 => s_U2X_RD_EN, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_EMPTY_NONREG ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_RAM_EMPTY_i : X_FF generic map( LOC => "SLICE_X27Y7", INIT => '1' ) port map ( I => s_U2X_EMPTY_DXMUX_1484, CE => VCC, CLK => s_U2X_EMPTY_CLKINV_1485, SET => s_U2X_EMPTY_FFX_SET, RST => GND, O => s_U2X_EMPTY ); s_U2X_EMPTY_FFX_SETOR : X_BUF generic map( LOC => "SLICE_X27Y7", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => s_U2X_EMPTY_FFX_SET ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8 : X_FF generic map( LOC => "SLICE_X25Y11", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_DYMUX_1486, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_CLKINV_1487, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_FFY_RSTAND_1615, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(8) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X25Y11", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_FFY_RSTAND_1615 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_9 : X_FF generic map( LOC => "SLICE_X48Y7", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_9_DYMUX_1488, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_9_CLKINV_1489, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_9_FFY_RSTAND_1616, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc(9) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_9_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X48Y7", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_9_FFY_RSTAND_1616 ); FSM_GPIF_o_WRX : X_LUT4 generic map( INIT => X"89CD", LOC => "SLICE_X39Y1" ) port map ( ADR0 => FSM_GPIF_pr_state_FFd4_6, ADR1 => FSM_GPIF_pr_state_FFd1_5, ADR2 => N30_0, ADR3 => N31, O => o_WRX_OBUF_1490 ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_0 : X_FF generic map( LOC => "SLICE_X28Y8", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_DYMUX_1492, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_CLKINV_1494, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_SRINV_1493, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(0) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1 : X_FF generic map( LOC => "SLICE_X28Y8", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_DXMUX_1491, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_CLKINV_1494, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1_SRINV_1493, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_1 : X_FF generic map( LOC => "SLICE_X49Y3", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_DYMUX_1496, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_CLKINV_1498, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_SRINV_1497, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(1) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2 : X_FF generic map( LOC => "SLICE_X49Y3", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_DXMUX_1495, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_CLKINV_1498, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2_SRINV_1497, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_2 : X_FF generic map( LOC => "SLICE_X29Y10", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_DYMUX_1500, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_CLKINV_1502, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_SRINV_1501, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(2) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3 : X_FF generic map( LOC => "SLICE_X29Y10", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_DXMUX_1499, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_CLKINV_1502, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3_SRINV_1501, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_3 : X_FF generic map( LOC => "SLICE_X48Y2", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_DYMUX_1504, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_CLKINV_1506, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_SRINV_1505, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(3) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4 : X_FF generic map( LOC => "SLICE_X48Y2", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_DXMUX_1503, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_CLKINV_1506, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_SRINV_1505, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4 : X_FF generic map( LOC => "SLICE_X27Y10", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_DYMUX_1508, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_CLKINV_1510, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_SRINV_1509, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(4) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5 : X_FF generic map( LOC => "SLICE_X27Y10", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_DXMUX_1507, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_CLKINV_1510, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5_SRINV_1509, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(5) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_5 : X_FF generic map( LOC => "SLICE_X48Y3", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_DYMUX_1512, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_CLKINV_1514, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_SRINV_1513, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(5) ); FSM_GPIF_Mcount_v_setup_eqn_2 : X_LUT4 generic map( INIT => X"A584", LOC => "SLICE_X39Y6" ) port map ( ADR0 => FSM_GPIF_v_setup(2), ADR1 => N4, ADR2 => N120_0, ADR3 => N23, O => FSM_GPIF_Mcount_v_setup_eqn_2_1528 ); FSM_GPIF_v_setup_2 : X_FF generic map( LOC => "SLICE_X39Y6", INIT => '0' ) port map ( I => FSM_GPIF_v_setup_2_DXMUX_1527, CE => FSM_GPIF_v_setup_2_CEINV_1530, CLK => FSM_GPIF_v_setup_2_CLKINV_1529, SET => GND, RST => FSM_GPIF_v_setup_2_FFX_RSTAND_1617, O => FSM_GPIF_v_setup(2) ); FSM_GPIF_v_setup_2_FFX_RSTAND : X_INV generic map( LOC => "SLICE_X39Y6", PATHPULSE => 757 ps ) port map ( I => i_nReset_IBUF_4, O => FSM_GPIF_v_setup_2_FFX_RSTAND_1617 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6 : X_FF generic map( LOC => "SLICE_X48Y3", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_DXMUX_1511, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_CLKINV_1514, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_SRINV_1513, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(6) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6 : X_FF generic map( LOC => "SLICE_X27Y12", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_DYMUX_1516, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_CLKINV_1518, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_SRINV_1517, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(6) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7 : X_FF generic map( LOC => "SLICE_X27Y12", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_DXMUX_1515, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_CLKINV_1518, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7_SRINV_1517, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(7) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_7 : X_FF generic map( LOC => "SLICE_X46Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_DYMUX_1520, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_CLKINV_1522, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_SRINV_1521, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(7) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8 : X_FF generic map( LOC => "SLICE_X46Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_DXMUX_1519, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_CLKINV_1522, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_SRINV_1521, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(8) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8 : X_FF generic map( LOC => "SLICE_X27Y13", INIT => '0' ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_DYMUX_1523, CE => VCC, CLK => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_CLKINV_1524, SET => GND, RST => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_FFY_RSTAND_1618, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(8) ); F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X27Y13", PATHPULSE => 757 ps ) port map ( I => F_IN_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_1, O => F_IN_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_FFY_RSTAND_1618 ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9 : X_FF generic map( LOC => "SLICE_X48Y6", INIT => '0' ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9_DYMUX_1525, CE => VCC, CLK => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9_CLKINV_1526, SET => GND, RST => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9_FFY_RSTAND_1619, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2(9) ); F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X48Y6", PATHPULSE => 757 ps ) port map ( I => F_OUT_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_0, O => F_OUT_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_9_FFY_RSTAND_1619 ); GLOBAL_LOGIC1_VCC : X_ONE port map ( O => GLOBAL_LOGIC1 ); GLOBAL_LOGIC0_GND : X_ZERO port map ( O => GLOBAL_LOGIC0 ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_G_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X53Y10" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(1), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_G ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_F_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X53Y11" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(2), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_F ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X53Y11" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(3), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_G ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_F_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X53Y12" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(4), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_F ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_G_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X53Y12" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(5), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_G ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_F_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X53Y13" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(6), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_F ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X53Y13" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(7), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_G ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X44Y4" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(1), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_G ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_F_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X44Y5" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(2), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_F ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_G_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X44Y5" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(3), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_G ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_F_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X44Y6" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(4), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_F ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X44Y6" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(5), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_G ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_F_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X44Y7" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(6), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_F ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_G_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X44Y7" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(7), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_G ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_G_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X40Y0" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(1), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_G ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_F_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X40Y1" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(2), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_F ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X40Y1" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(3), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_G ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_F_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X40Y2" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(4), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_F ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_G_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X40Y2" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(5), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_G ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_F_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X40Y3" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(6), O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_F ); F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X40Y3" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(7), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_G ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_G_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X38Y2" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(1), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_G ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_F_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X38Y3" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(2), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_F ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X38Y3" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(3), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_G ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_F_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X38Y4" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(4), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_F ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_G_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X38Y4" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(5), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_G ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_F_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X38Y5" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(6), O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_F ); F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_G_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X38Y5" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(7), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_G ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_G_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X35Y8" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(1), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_G ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_F_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X35Y9" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(2), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_F ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_G_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X35Y9" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(3), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_G ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_F_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X35Y10" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(4), O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_F ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_G_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X35Y10" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(5), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_G ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_F_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X35Y11" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(6), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_F ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X35Y11" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(7), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_G ); F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_F_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X35Y12" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(8), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_F ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_G_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X34Y4" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(1), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_G ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_F_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X34Y5" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(2), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_F ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X34Y5" ) port map ( ADR0 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(3), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_G ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_F_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X34Y6" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(4), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_F ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_G_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X34Y6" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(5), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_G ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_F_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X34Y7" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(6), ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_F ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_G_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X34Y7" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(7), O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_G ); F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_F_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X34Y8" ) port map ( ADR0 => VCC, ADR1 => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(8), ADR2 => VCC, ADR3 => VCC, O => F_OUT_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_F ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X10Y2" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(1), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_G ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_F_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X10Y3" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(2), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_F ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_G_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X10Y3" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(3), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_G ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_F_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X10Y4" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(4), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_F ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_G_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X10Y4" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(5), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_G ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_F_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X10Y5" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(6), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_F ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_G_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X10Y5" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(7), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_G ); F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_F_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X10Y6" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR(8), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_8_F ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_G_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X24Y14" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(1), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_G ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_F_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X24Y15" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(2), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_F ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X24Y15" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(3), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_G ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_F_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X24Y16" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(4), O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_F ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_G_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X24Y16" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(5), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_G ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_F_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X24Y17" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(6), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_F ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_G_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X24Y17" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(7), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_G ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_F_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X24Y18" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w(8), O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_8_F ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_G_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X26Y12" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(1), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_G ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_F_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X26Y13" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(2), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_F ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X26Y13" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(3), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_G ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_F_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X26Y14" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(4), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_F ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X26Y14" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(5), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_G ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_F_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X26Y15" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(6), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_F ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_G_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X26Y15" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(7), O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_G ); F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_F_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X26Y16" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w(8), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_8_F ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_G_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X31Y12" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(1), O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_G ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_F_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X31Y13" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(2), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_F ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X31Y13" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(3), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_G ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_F_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X31Y14" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(4), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_F ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_G_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X31Y14" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(5), O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_G ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_F_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X31Y15" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(6), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_F ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X31Y15" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(7), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_G ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_F_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X31Y16" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(8), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus3_bld_wr_cntr_plus3_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_8_F ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X24Y6" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(1), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_G ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_F_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X24Y7" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(2), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_F ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_G_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X24Y7" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(3), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_G ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_F_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X24Y8" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(4), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_F ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_G_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X24Y8" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(5), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_G ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_F_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X24Y9" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(6), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_F ); F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_G_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X24Y9" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR(7), O => F_IN_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_G ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_G_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X31Y4" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(1), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_G ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_F_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X31Y5" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(2), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_F ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_G_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X31Y5" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(3), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_G ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_F_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X31Y6" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(4), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_F ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_G_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X31Y6" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(5), O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_G ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_F_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X31Y7" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(6), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_F ); F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_G_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X31Y7" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r(7), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_G ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_G_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X29Y0" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(1), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_0_G ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_F_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X29Y1" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(2), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_F ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_G_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X29Y1" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(3), O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_2_G ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_F_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X29Y2" ) port map ( ADR0 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(4), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_F ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_G_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X29Y2" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(5), ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_4_G ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_F_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X29Y3" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(6), O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_F ); F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_G_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X29Y3" ) port map ( ADR0 => VCC, ADR1 => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count(7), ADR2 => VCC, ADR3 => VCC, O => F_IN_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus2_bld_rd_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_count_6_G ); b_dbus_10_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD331", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_10_T ); b_dbus_10_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD331", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(10), O => b_dbus_10_O ); b_dbus_11_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD370", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_11_T ); b_dbus_11_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD370", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(11), O => b_dbus_11_O ); b_dbus_12_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD324", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_12_T ); b_dbus_12_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD324", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(12), O => b_dbus_12_O ); b_dbus_13_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD334", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_13_T ); b_dbus_13_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD334", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(13), O => b_dbus_13_O ); b_dbus_14_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD337", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_14_T ); b_dbus_14_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD337", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(14), O => b_dbus_14_O ); b_dbus_15_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD338", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_15_T ); b_dbus_15_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD338", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(15), O => b_dbus_15_O ); o_WRX_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD320", PATHPULSE => 757 ps ) port map ( I => o_WRX_OBUF_1490, O => o_WRX_O ); o_RDYX_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD321", PATHPULSE => 757 ps ) port map ( I => o_RDYX_OBUF_F5MUX_1115, O => o_RDYX_O ); o_LEDrx_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD14", PATHPULSE => 757 ps ) port map ( I => o_LEDrx_OBUF_1283, O => o_LEDrx_O ); o_LEDtx_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD21", PATHPULSE => 757 ps ) port map ( I => o_LEDtx_OBUF_1303, O => o_LEDtx_O ); b_dbus_0_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD336", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_0_T ); b_dbus_0_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD336", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(0), O => b_dbus_0_O ); b_dbus_1_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD335", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_1_T ); b_dbus_1_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD335", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(1), O => b_dbus_1_O ); b_dbus_2_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD328", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_2_T ); b_dbus_2_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD328", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(2), O => b_dbus_2_O ); b_dbus_3_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD327", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_3_T ); b_dbus_3_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD327", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(3), O => b_dbus_3_O ); b_dbus_4_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD318", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_4_T ); b_dbus_4_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD318", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(4), O => b_dbus_4_O ); b_dbus_5_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD317", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_5_T ); b_dbus_5_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD317", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(5), O => b_dbus_5_O ); b_dbus_6_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD311", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_6_T ); b_dbus_6_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD311", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(6), O => b_dbus_6_O ); b_dbus_7_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD310", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_7_T ); b_dbus_7_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD310", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(7), O => b_dbus_7_O ); b_dbus_8_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD371", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_8_T ); b_dbus_8_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD371", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(8), O => b_dbus_8_O ); b_dbus_9_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD330", PATHPULSE => 757 ps ) port map ( I => FSM_GPIF_s_bus_trans_dir_inv_0, O => b_dbus_9_T ); b_dbus_9_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD330", PATHPULSE => 757 ps ) port map ( I => s_dbus_out(9), O => b_dbus_9_O ); o_LEDrun_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD18", PATHPULSE => 757 ps ) port map ( I => o_LEDrun_OBUF_1304, O => o_LEDrun_O ); NlwBlock_USB_TMC_IP_VCC : X_ONE port map ( O => VCC ); NlwBlock_USB_TMC_IP_GND : X_ZERO port map ( O => GND ); NlwBlockROC : X_ROC generic map (ROC_WIDTH => 100 ns) port map (O => GSR); NlwBlockTOC : X_TOC port map (O => GTS); end Structure;
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