Subversion Repositories gecko3

Release 9.1.03i - netgen J.33
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -ar Structure -tm USB_TMC_IP -w -dir
netgen/synthesis -ofmt vhdl -sim USB_TMC_IP.ngc USB_TMC_IP_synthesis.vhd  

Reading design 'USB_TMC_IP.ngc' ...
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist
'/home/habea2/Geccko3com/gecko3com_v04/netgen/synthesis/USB_TMC_IP_synthesis.vhd
' ...
INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIM
   simulation primitives and has to be used with UNISIM library for correct
   compilation and simulation. 
Number of warnings: 0
Number of info messages: 1
Total memory usage is 40116 kilobytes