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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [netgen/] [synthesis/] [USB_TMC_IP_synthesis.nlf] - Rev 33
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Release 9.1.03i - netgen J.33Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.Command Line: netgen -intstyle ise -ar Structure -tm USB_TMC_IP -w -dirnetgen/synthesis -ofmt vhdl -sim USB_TMC_IP.ngc USB_TMC_IP_synthesis.vhdReading design 'USB_TMC_IP.ngc' ...Flattening design ...Processing design ...Preping design's networks ...Preping design's macros ...Writing VHDL netlist'/home/habea2/Geccko3com/gecko3com_v04/netgen/synthesis/USB_TMC_IP_synthesis.vhd' ...INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIMsimulation primitives and has to be used with UNISIM library for correctcompilation and simulation.Number of warnings: 0Number of info messages: 1Total memory usage is 40116 kilobytes
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