Subversion Repositories gecko3

<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
        <Folder label="VERILOG Component Instantiation" treetype="folder">
                <Template label="fifo_U2X_2C_1024B" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
fifo_U2X_2C_1024B YourInstanceName (
    .din(din), // Bus [15 : 0] 
    .rd_clk(rd_clk),
    .rd_en(rd_en),
    .rst(rst),
    .wr_clk(wr_clk),
    .wr_en(wr_en),
    .almost_empty(almost_empty),
    .almost_full(almost_full),
    .dout(dout), // Bus [31 : 0] 
    .empty(empty),
    .full(full));

 
                </Template>
                <Template label="fifo_X2U_2C_1024B" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
fifo_X2U_2C_1024B YourInstanceName (
    .din(din), // Bus [31 : 0] 
    .rd_clk(rd_clk),
    .rd_en(rd_en),
    .rst(rst),
    .wr_clk(wr_clk),
    .wr_en(wr_en),
    .almost_empty(almost_empty),
    .almost_full(almost_full),
    .dout(dout), // Bus [15 : 0] 
    .empty(empty),
    .full(full));

 
                </Template>
        </Folder>
        <Folder label="VHDL Component Instantiation" treetype="folder">
                <Template label="fifo_U2X_2C_1024B" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component fifo_U2X_2C_1024B
    port (
    din: IN std_logic_VECTOR(15 downto 0);
    rd_clk: IN std_logic;
    rd_en: IN std_logic;
    rst: IN std_logic;
    wr_clk: IN std_logic;
    wr_en: IN std_logic;
    almost_empty: OUT std_logic;
    almost_full: OUT std_logic;
    dout: OUT std_logic_VECTOR(31 downto 0);
    empty: OUT std_logic;
    full: OUT std_logic);
end component;


 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : fifo_U2X_2C_1024B
        port map (
            din =&gt; din,
            rd_clk =&gt; rd_clk,
            rd_en =&gt; rd_en,
            rst =&gt; rst,
            wr_clk =&gt; wr_clk,
            wr_en =&gt; wr_en,
            almost_empty =&gt; almost_empty,
            almost_full =&gt; almost_full,
            dout =&gt; dout,
            empty =&gt; empty,
            full =&gt; full);
 
                </Template>
                <Template label="fifo_X2U_2C_1024B" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component fifo_X2U_2C_1024B
    port (
    din: IN std_logic_VECTOR(31 downto 0);
    rd_clk: IN std_logic;
    rd_en: IN std_logic;
    rst: IN std_logic;
    wr_clk: IN std_logic;
    wr_en: IN std_logic;
    almost_empty: OUT std_logic;
    almost_full: OUT std_logic;
    dout: OUT std_logic_VECTOR(15 downto 0);
    empty: OUT std_logic;
    full: OUT std_logic);
end component;


 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : fifo_X2U_2C_1024B
        port map (
            din =&gt; din,
            rd_clk =&gt; rd_clk,
            rd_en =&gt; rd_en,
            rst =&gt; rst,
            wr_clk =&gt; wr_clk,
            wr_en =&gt; wr_en,
            almost_empty =&gt; almost_empty,
            almost_full =&gt; almost_full,
            dout =&gt; dout,
            empty =&gt; empty,
            full =&gt; full);
 
                </Template>
        </Folder>
</RootFolder>