Subversion Repositories gecko3

# //  ModelSim SE 6.5a Mar 27 2009 Linux 2.6.28-11-generic
# //
# //  Copyright 1991-2009 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do {USB_TMC_IP_tb.fdo} 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1110 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1120 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1510 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 990 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1 us  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1390 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1830 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1840 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1110 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1120 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1510 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
restart
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
run
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1110 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1120 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1510 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
run
# ** Note: <<< End of simulation >>>
#    Time: 2030 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 2040 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 2430 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 3030 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 3040 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 3430 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 3950 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 3960 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1110 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1120 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1510 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1130 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1140 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1530 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1190 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1200 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1110 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1120 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1510 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# ** Error: gpif_com.vhd(272): (vcom-1136) Unknown identifier "v_isfirstbitonthebus".
# ** Error: gpif_com.vhd(272): Target type (error) in variable assignment is different from expression type std.standard.boolean.
# ** Error: gpif_com.vhd(272): (vcom-1136) Unknown identifier "v_isfirstbitonthebus".
# ** Error: gpif_com.vhd(319): VHDL Compiler exiting
# ** Error: /opt/mentorGraphics/modeltech/linux/vcom failed.
# Error in macro ./USB_TMC_IP_tb.fdo line 6
# /opt/mentorGraphics/modeltech/linux/vcom failed.
#     while executing
# "vcom -explicit  -93 "gpif_com.vhd""
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1110 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1120 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1510 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Warning: WRX and RDYX are high on the same time
#    Time: 650 ns  Iteration: 4  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# ** Error: gpif_com.vhd(272): (vcom-1136) Unknown identifier "v_isfirstbitonthebus".
# ** Error: gpif_com.vhd(272): Target type (error) in variable assignment is different from expression type std.standard.boolean.
# ** Error: gpif_com.vhd(272): (vcom-1136) Unknown identifier "v_isfirstbitonthebus".
# ** Error: gpif_com.vhd(320): VHDL Compiler exiting
# ** Error: /opt/mentorGraphics/modeltech/linux/vcom failed.
# Error in macro ./USB_TMC_IP_tb.fdo line 6
# /opt/mentorGraphics/modeltech/linux/vcom failed.
#     while executing
# "vcom -explicit  -93 "gpif_com.vhd""
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1070 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1080 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1470 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1990 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 2 us  Iteration: 0  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1070 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1080 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1470 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1990 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 2 us  Iteration: 0  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1130 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1140 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1530 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1070 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1080 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1470 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1990 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 2 us  Iteration: 0  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1130 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1140 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1530 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1070 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1080 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1470 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1990 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 2 us  Iteration: 0  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1130 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1140 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1530 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1070 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1080 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1470 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1990 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 2 us  Iteration: 0  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1070 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1080 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1470 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1990 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 2 us  Iteration: 0  Instance: /usb_tmc_ip_tb
do {USB_TMC_IP_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling package usb_tmc_ip_defs
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity gpif_com
# -- Compiling architecture com_core of gpif_com
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_x2u_2c_1024b
# -- Compiling architecture fifo_x2u_2c_1024b_a of fifo_x2u_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity fifo_u2x_2c_1024b
# -- Compiling architecture fifo_u2x_2c_1024b_a of fifo_u2x_2c_1024b
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package textio
# -- Loading package iputils_conv
# -- Loading package iputils_misc
# -- Loading entity fifo_generator_v3_3_bhv_as
# -- Loading entity fifo_generator_v3_3_bhv_ss
# -- Loading entity fifo_generator_v3_3
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling package usb_tmc_cmp
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Compiling entity usb_tmc_ip_loopback
# -- Compiling architecture loopback of usb_tmc_ip_loopback
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip
# -- Compiling architecture top_core of usb_tmc_ip
# Model Technology ModelSim SE vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package vcomponents
# -- Loading package std_logic_unsigned
# -- Loading package usb_tmc_ip_defs
# -- Loading package usb_tmc_cmp
# -- Compiling entity usb_tmc_ip_tb
# -- Compiling architecture simulation of usb_tmc_ip_tb
# vsim -lib work -t 1ns USB_TMC_IP_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading unisim.vcomponents
# Loading ieee.std_logic_unsigned(body)
# Loading work.usb_tmc_ip_defs
# Loading work.usb_tmc_cmp
# Loading work.usb_tmc_ip_tb(simulation)#1
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading std.textio(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.usb_tmc_ip(top_core)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#1
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)#2
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)#2
# Loading work.gpif_com(com_core)#1
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Note: system ready to start
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_out/u0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb/dut/f_in/u0
# ** Note: system reset
#    Time: 0 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 10 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: system reset
#    Time: 20 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 590 ns  Iteration: 1  Instance: /usb_tmc_ip_tb
# ** Note: <<< End of simulation >>>
#    Time: 1170 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: Simulation started
#    Time: 1180 ns  Iteration: 0  Instance: /usb_tmc_ip_tb
# ** Note: DATA written
#    Time: 1570 ns  Iteration: 1  Instance: /usb_tmc_ip_tb