Subversion Repositories gecko3

############################################################
#  
#  Gecko3 SoC HW/SW Development Board
#   ___    ___   _   _
#  (  _`\ (  __)( ) ( )   
#  | (_) )| (   | |_| |   Bern University of Applied Sciences
#  |  _ <'|  _) |  _  |   School of Engineering and
#  | (_) )| |   | | | |   Information Technology
#  (____/'(_)   (_) (_)
#
#
#  Author:  Christoph Zimmermann
#  Date of creation: 22.08.2007
#  Description:
#       constraint file for the first version of the GECKO3main
#       only onboard peripherie is located here 
#
############################################################

## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps;
Net sys_rst_pin TIG;

Net fpga_0_Micron_DDR_1_CLK_FB_pin TNM_NET = fpga_0_Micron_DDR_1_CLK_FB_pin;
TIMESPEC TS_fpga_0_Micron_DDR_1_CLK_FB_pin = PERIOD fpga_0_Micron_DDR_1_CLK_FB_pin 12000 ps;
#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "sys_clk_pin"  LOC = "af14" ; 
NET "sys_rst_pin"  LOC = "ae19" ; 


NET "fpga_0_Ethernet_10_100_PHY_col_pin"  LOC = "af5" ; 
NET "fpga_0_Ethernet_10_100_PHY_crs_pin"  LOC = "af7" ; 
NET "fpga_0_Ethernet_10_100_PHY_dv_pin"  LOC = "ad5" ; 
NET "fpga_0_Ethernet_10_100_PHY_rst_n_pin"  LOC = "af13" ; 
NET "fpga_0_Ethernet_10_100_PHY_rx_clk_pin"  LOC = "ae7" ; 
NET "fpga_0_Ethernet_10_100_PHY_rx_data_pin<0>"  LOC = "ad6" ; 
NET "fpga_0_Ethernet_10_100_PHY_rx_data_pin<1>"  LOC = "af8" ; 
NET "fpga_0_Ethernet_10_100_PHY_rx_data_pin<2>"  LOC = "ae4" ; 
NET "fpga_0_Ethernet_10_100_PHY_rx_data_pin<3>"  LOC = "ae8" ; 
NET "fpga_0_Ethernet_10_100_PHY_rx_er_pin"  LOC = "ad4" ; 
NET "fpga_0_Ethernet_10_100_PHY_tx_clk_pin"  LOC = "ab9" ; 
NET "fpga_0_Ethernet_10_100_PHY_tx_data_pin<0>"  LOC = "ab11" ; 
NET "fpga_0_Ethernet_10_100_PHY_tx_data_pin<1>"  LOC = "ac10" ; 
NET "fpga_0_Ethernet_10_100_PHY_tx_data_pin<2>"  LOC = "ac11" ; 
NET "fpga_0_Ethernet_10_100_PHY_tx_data_pin<3>"  LOC = "ad10" ; 
NET "fpga_0_Ethernet_10_100_PHY_tx_en_pin"  LOC = "ab10" ;
NET "fpga_0_Ethernet_10_100_PHY_pwr_down_pin"  LOC = "ad12" ;


NET "fpga_0_Intel_StrataFlash_Mem_BYTEn_pin"  LOC = "h16" ;
NET "fpga_0_Intel_StrataFlash_Mem_CEN_pin<0>"  LOC = "e15" ;
NET "fpga_0_Intel_StrataFlash_Mem_OEN_pin"  LOC = "b21" ; 
NET "fpga_0_Intel_StrataFlash_Mem_WEN_pin"  LOC = "b3" ;
NET "fpga_0_Intel_StrataFlash_Mem_RPN_pin"  LOC = "f15" ;

NET "fpga_0_Intel_StrataFlash_Mem_A_pin<7>"  LOC = "g16" ; #this pin is in the schematic Flash_A23!
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<8>"  LOC = "b12" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<9>"  LOC = "a12" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<10>"  LOC = "c10" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<11>"  LOC = "d10" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<12>"  LOC = "h11" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<13>"  LOC = "h12" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<14>"  LOC = "d11" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<15>"  LOC = "e14" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<16>"  LOC = "e11" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<17>"  LOC = "f14" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<18>"  LOC = "f11" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<19>"  LOC = "f12" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<20>"  LOC = "f16" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<21>"  LOC = "g11" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<22>"  LOC = "d17" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<23>"  LOC = "g12" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<24>"  LOC = "h13" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<25>"  LOC = "g13" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<26>"  LOC = "g14" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<27>"  LOC = "h14" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<28>"  LOC = "g15" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<29>"  LOC = "h15" ; 
NET "fpga_0_Intel_StrataFlash_Mem_A_pin<30>"  LOC = "g17" ; #this pin is in the schematic Flash_A0!
# start Data Bus Flash 0
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<0>"  LOC = "d25" ; #this pin is in the schematic Flash_D0_15!
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<1>"  LOC = "e24" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<2>"  LOC = "e23" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<3>"  LOC = "f21" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<4>"  LOC = "a21" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<5>"  LOC = "d20" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<6>"  LOC = "f20" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<7>"  LOC = "g18" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<8>"  LOC = "b20" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<9>"  LOC = "h24" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<10>"  LOC = "h23" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<11>"  LOC = "e21" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<12>"  LOC = "e20" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<13>"  LOC = "a20" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<14>"  LOC = "g19" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<15>"  LOC = "f18" ; #this pin is in the schematic Flash_D0_0!
# start Data Bus Flash 1
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<16>"  LOC = "a3" ; #this pin is in the schematic Flash_D1_15!
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<17>"  LOC = "a4" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<18>"  LOC = "a5" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<19>"  LOC = "a6" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<20>"  LOC = "a7" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<21>"  LOC = "a8" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<22>"  LOC = "e5" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<23>"  LOC = "c5" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<24>"  LOC = "b4" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<25>"  LOC = "b5" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<26>"  LOC = "b6" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<27>"  LOC = "b7" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<28>"  LOC = "b8" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<29>"  LOC = "c4" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<30>"  LOC = "d5" ;
NET "fpga_0_Intel_StrataFlash_Mem_DQ_pin<31>"  LOC = "e6" ; #this pin is in the schematic Flash_D1_0! 


#DDR SDRAM 0
#here we change the bit order from big-endian (OPB like)
#to little-endian (as it is requested by the ddr ram)
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<0>"  LOC = "v3" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic A0_13!
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<1>"  LOC = "w6" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<2>"  LOC = "w7" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<3>"  LOC = "t6" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<4>"  LOC = "ad1" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<5>"  LOC = "ad2" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<6>"  LOC = "ac1" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<7>"  LOC = "ab3" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<8>"  LOC = "ab4" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<9>"  LOC = "t8" | IOSTANDARD = SSTL2_II ;
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<10>"  LOC = "r8" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<11>"  LOC = "p7" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<12>"  LOC = "r7" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_Addr_pin<13>"  LOC = "p6" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic A0_0!

NET "fpga_0_Micron_DDR_0_DDR_DM_pin<0>"  LOC = "v4" | IOSTANDARD = SSTL2_II ; #UDM0
NET "fpga_0_Micron_DDR_0_DDR_DM_pin<1>"  LOC = "v2" | IOSTANDARD = SSTL2_II ; #LDM0

NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<0>"  LOC = "p5" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic D0_15! 
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<1>"  LOC = "p4" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<2>"  LOC = "r6" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<3>"  LOC = "r5" | IOSTANDARD = SSTL2_II ;
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<4>"  LOC = "t4" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<5>"  LOC = "t5" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<6>"  LOC = "u3" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<7>"  LOC = "u5" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<8>"  LOC = "u1" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<9>"  LOC = "u2" | IOSTANDARD = SSTL2_II ;
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<10>"  LOC = "t1" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<11>"  LOC = "p2" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<12>"  LOC = "r3" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<13>"  LOC = "t2" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<14>"  LOC = "p8" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_DQ_pin<15>"  LOC = "p3" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic D0_0! 

NET "fpga_0_Micron_DDR_0_DDR_DQS_pin<0>"  LOC = "w4" | IOSTANDARD = SSTL2_II ; #UDQS0
NET "fpga_0_Micron_DDR_0_DDR_DQS_pin<1>"  LOC = "r1" | IOSTANDARD = SSTL2_II ; #LDQS0

NET "fpga_0_Micron_DDR_0_DDR_BankAddr_pin<0>"  LOC = "u6" | IOSTANDARD = SSTL2_II ; #BA0_1
NET "fpga_0_Micron_DDR_0_DDR_BankAddr_pin<1>"  LOC = "v5" | IOSTANDARD = SSTL2_II ; #BA0_0

NET "fpga_0_Micron_DDR_0_DDR_CASn_pin"  LOC = "u7" | IOSTANDARD = SSTL2_II ;
NET "fpga_0_Micron_DDR_0_DDR_RASn_pin"  LOC = "v6" | IOSTANDARD = SSTL2_II ; 

NET "fpga_0_Micron_DDR_0_DDR_WEn_pin"  LOC = "t7" | IOSTANDARD = SSTL2_II ;
NET "fpga_0_Micron_DDR_0_DDR_CSn_pin<0>"  LOC = "v7" | IOSTANDARD = SSTL2_II ;

NET "fpga_0_Micron_DDR_0_DDR_CKE_pin<0>"  LOC = "w5" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_Clk_pin<0>"  LOC = "w1" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_0_DDR_Clkn_pin<0>"  LOC = "w2" | IOSTANDARD = SSTL2_II ;

NET "fpga_0_Micron_DDR_0_CLK_FB_pin"  LOC = "ae14" ;

#DDR SDRAM 1
#here we change the bit order from big-endian (OPB like)
#to little-endian (as it is requested by the ddr ram)
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<0>"  LOC = "k5" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic A1_13!
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<1>"  LOC = "n3" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<2>"  LOC = "n2" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<3>"  LOC = "n5" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<4>"  LOC = "m5" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<5>"  LOC = "n7" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<6>"  LOC = "n6" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<7>"  LOC = "n8" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<8>"  LOC = "m1" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<9>"  LOC = "l1" | IOSTANDARD = SSTL2_II ;
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<10>"  LOC = "m2" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<11>"  LOC = "k1" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<12>"  LOC = "m3" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_Addr_pin<13>"  LOC = "l2" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic A1_0!

NET "fpga_0_Micron_DDR_1_DDR_DM_pin<0>"  LOC = "k2" | IOSTANDARD = SSTL2_II ; #UDM1
NET "fpga_0_Micron_DDR_1_DDR_DM_pin<1>"  LOC = "l5" | IOSTANDARD = SSTL2_II ; #LDM1

NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<0>"  LOC = "e4" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic D1_15! 
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<1>"  LOC = "e3" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<2>"  LOC = "d2" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<3>"  LOC = "h4" | IOSTANDARD = SSTL2_II ;
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<4>"  LOC = "h3" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<5>"  LOC = "g2" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<6>"  LOC = "g1" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<7>"  LOC = "j3" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<8>"  LOC = "m6" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<9>"  LOC = "m7" | IOSTANDARD = SSTL2_II ;
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<10>"  LOC = "j5" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<11>"  LOC = "j6" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<12>"  LOC = "k6" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<13>"  LOC = "j7" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<14>"  LOC = "k7" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_DQ_pin<15>"  LOC = "l6" | IOSTANDARD = SSTL2_II ; #this pin is in the schematic D1_0! 

NET "fpga_0_Micron_DDR_1_DDR_DQS_pin<0>"  LOC = "h2" | IOSTANDARD = SSTL2_II ; #UDQS1
NET "fpga_0_Micron_DDR_1_DDR_DQS_pin<1>"  LOC = "l7" | IOSTANDARD = SSTL2_II ; #LDQS1

NET "fpga_0_Micron_DDR_1_DDR_BankAddr_pin<0>"  LOC = "j2" | IOSTANDARD = SSTL2_II ; #BA1_1
NET "fpga_0_Micron_DDR_1_DDR_BankAddr_pin<1>"  LOC = "k3" | IOSTANDARD = SSTL2_II ; #BA1_0

NET "fpga_0_Micron_DDR_1_DDR_CASn_pin"  LOC = "k4" | IOSTANDARD = SSTL2_II ;
NET "fpga_0_Micron_DDR_1_DDR_RASn_pin"  LOC = "j4" | IOSTANDARD = SSTL2_II ; 

NET "fpga_0_Micron_DDR_1_DDR_WEn_pin"  LOC = "l4" | IOSTANDARD = SSTL2_II ;
NET "fpga_0_Micron_DDR_1_DDR_CSn_pin<0>"  LOC = "m8" | IOSTANDARD = SSTL2_II ;

NET "fpga_0_Micron_DDR_1_DDR_CKE_pin<0>"  LOC = "n4" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_Clk_pin<0>"  LOC = "f5" | IOSTANDARD = SSTL2_II ; 
NET "fpga_0_Micron_DDR_1_DDR_Clkn_pin<0>"  LOC = "f6" | IOSTANDARD = SSTL2_II ;

NET "fpga_0_Micron_DDR_1_CLK_FB_pin"  LOC = "c14" ; 


#SPI bus, connectet to the M25P32 serial flash memory
NET "fpga_0_Generic_SPI_MISO_pin"  LOC = "aa11"  | SLEW = SLOW ; 
NET "fpga_0_Generic_SPI_MOSI_pin"  LOC = "aa9"  | SLEW = SLOW ; 
NET "fpga_0_Generic_SPI_SCK_pin"  LOC = "aa10"  | SLEW = SLOW ;
NET "fpga_0_Generic_SPI_CS_pin<0>"  LOC = "y8"  | SLEW = SLOW ;
 

#LEDs 
NET "fpga_0_LEDS_GPIO_d_out_pin<0>"  LOC = "c13"  | SLEW = SLOW ;   #this is LED7 in the schematic!
NET "fpga_0_LEDS_GPIO_d_out_pin<1>"  LOC = "d13"  | SLEW = SLOW ; 
NET "fpga_0_LEDS_GPIO_d_out_pin<2>"  LOC = "e13"  | SLEW = SLOW ; 
NET "fpga_0_LEDS_GPIO_d_out_pin<3>"  LOC = "c12"  | SLEW = SLOW ; 
NET "fpga_0_LEDS_GPIO_d_out_pin<4>"  LOC = "e10"  | SLEW = SLOW ; 
NET "fpga_0_LEDS_GPIO_d_out_pin<5>"  LOC = "f10"  | SLEW = SLOW ; 
NET "fpga_0_LEDS_GPIO_d_out_pin<6>"  LOC = "g9"  | SLEW = SLOW ; 
NET "fpga_0_LEDS_GPIO_d_out_pin<7>"  LOC = "f9"  | SLEW = SLOW ;   #this is LED0 in the schematic!


#Switches and Buttons
NET "fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<0>"  LOC = "d6" ;  #this is switch3 in the schematic!
NET "fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<1>"  LOC = "c6" ; 
NET "fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<2>"  LOC = "f7" ; 
NET "fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<3>"  LOC = "d7" ;  #this is switch0 in the schematic!
NET "fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<4>"  LOC = "e12" ; #this is button2 in the schematic!
NET "fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<5>"  LOC = "g10" ; 
NET "fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<6>"  LOC = "e7" ;  #this is button0 in the schematic!


#rs232 uart 
NET "fpga_0_RS232_RX_pin"  LOC = "ac7" ; 
NET "fpga_0_RS232_TX_pin"  LOC = "ac6" ; 


#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints
CONFIG PROHIBIT = G7;
CONFIG PROHIBIT = G6;
CONFIG PROHIBIT = E2;
CONFIG PROHIBIT = E1;
CONFIG PROHIBIT = F4;
CONFIG PROHIBIT = F3;
CONFIG PROHIBIT = G5;
CONFIG PROHIBIT = G4;
CONFIG PROHIBIT = F2;
CONFIG PROHIBIT = F1;
CONFIG PROHIBIT = H7;
CONFIG PROHIBIT = H6;
CONFIG PROHIBIT = Y1;
CONFIG PROHIBIT = Y2;
CONFIG PROHIBIT = AA1;
CONFIG PROHIBIT = AA2;
CONFIG PROHIBIT = Y4;
CONFIG PROHIBIT = Y5;
CONFIG PROHIBIT = AA3;
CONFIG PROHIBIT = AA4;
CONFIG PROHIBIT = Y6;
CONFIG PROHIBIT = Y7;
CONFIG PROHIBIT = AB1;
CONFIG PROHIBIT = AB2;
CONFIG PROHIBIT = E25;
CONFIG PROHIBIT = E26;
CONFIG PROHIBIT = G20;
CONFIG PROHIBIT = G21;
CONFIG PROHIBIT = F23;
CONFIG PROHIBIT = F24;
CONFIG PROHIBIT = G22;
CONFIG PROHIBIT = G23;
CONFIG PROHIBIT = F25;
CONFIG PROHIBIT = F26;
CONFIG PROHIBIT = G25;
CONFIG PROHIBIT = G26;
CONFIG PROHIBIT = W21;
CONFIG PROHIBIT = W20;
CONFIG PROHIBIT = AA26;
CONFIG PROHIBIT = AA25;
CONFIG PROHIBIT = Y23;
CONFIG PROHIBIT = Y22;
CONFIG PROHIBIT = AA24;
CONFIG PROHIBIT = AA23;
CONFIG PROHIBIT = AB26;
CONFIG PROHIBIT = AB25;
CONFIG PROHIBIT = Y21;
CONFIG PROHIBIT = Y20;
CONFIG PROHIBIT = G8;
CONFIG PROHIBIT = F8;
CONFIG PROHIBIT = E8;
CONFIG PROHIBIT = D8;
CONFIG PROHIBIT = C8;
CONFIG PROHIBIT = E9;
CONFIG PROHIBIT = D9;
CONFIG PROHIBIT = C9;
CONFIG PROHIBIT = B9;
CONFIG PROHIBIT = B10;
CONFIG PROHIBIT = A10;
CONFIG PROHIBIT = B11;
CONFIG PROHIBIT = A11;
CONFIG PROHIBIT = A16;
CONFIG PROHIBIT = B16;
CONFIG PROHIBIT = A17;
CONFIG PROHIBIT = B17;
CONFIG PROHIBIT = B18;
CONFIG PROHIBIT = C18;
CONFIG PROHIBIT = D18;
CONFIG PROHIBIT = C19;
CONFIG PROHIBIT = D19;
CONFIG PROHIBIT = E19;
CONFIG PROHIBIT = F19;
CONFIG PROHIBIT = AA8;
CONFIG PROHIBIT = AB8;
CONFIG PROHIBIT = AC8;
CONFIG PROHIBIT = AD8;
CONFIG PROHIBIT = AC9;
CONFIG PROHIBIT = AD9;
CONFIG PROHIBIT = AE9;
CONFIG PROHIBIT = AE10;
CONFIG PROHIBIT = AF10;
CONFIG PROHIBIT = AE11;
CONFIG PROHIBIT = AF11;
CONFIG PROHIBIT = AF16;
CONFIG PROHIBIT = AE16;
CONFIG PROHIBIT = AF17;
CONFIG PROHIBIT = AE17;
CONFIG PROHIBIT = AE18;
CONFIG PROHIBIT = AD18;
CONFIG PROHIBIT = AC18;
CONFIG PROHIBIT = AB18;
CONFIG PROHIBIT = AD19;
CONFIG PROHIBIT = AC19;
CONFIG PROHIBIT = AB19;
CONFIG PROHIBIT = AA19;
CONFIG PROHIBIT = Y19;

#PACE: End of Constraints generated by PACE