Subversion Repositories genesys_ddr2

  genesys_ddr2: DDR2 memory controller for Digilent Genesys board
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What is this stuff?
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This is DDR2 memory controller for Digilent Genesys Board with wishbone slave interface and synthesizable test bench.

This IP is made-of several design files structured in the following directories:
- rtl: the user interface for the DDR2, the wishbone interface, external PLL clock generator, reset button debouncer as well as global reset generator
- rtl\ipcore_dir\MemCtrl: the DDR2 memory controller files generated by Xilinx MIG tool
- par: ucf file used for testing the synthesisable bench. The ucf file contains the memory pin placement as well as a reset pin connected to button from  LOC = "G7" 
- bench: synthesisable test files - top level module (test_DDR2_wb.v) and simple wishbone master mock that generates burst transactions for write followed by a read from the same address



DDR2 IP core
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DDR2_Mem.v - top level DDR2 memory wishbone compatible if module
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        --- ddr2_user_if_top.v - user interface top module: receives write/read commands from bus interface module 
                                                generates FIFO wr commands for address and data 
                                                
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                --- ddr2_adr_data_gen.v : latches commands data byte enable rd/wr data to/from FIFOS
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        --- clkGenPLL.v - generates clk signals for memory controller: clk0_125MHz, clk0Phase90, clk0Div2, clk200MHz as well as clkTFT10MHz and clkTFT10_180 for VMODTFT
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        --- DDR2_mem_wb_if.v - wishbone slave interface: generates rd/wr command requests for user interface (ddr2_user_if_top.v) module
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        --- debounceRst.v - global reset generator & reset button debouncer
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        --- rtl\ipcore_dir\MemCtrl  - files generated using Xilinx MIG Version: 3.6.1. Parameters: Bust length: 4, Data size: 64.



Synthesizable bench
====================
test_DDR2_wb.v - top level module FPGA proven
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        --- DDR2_Mem.v -top level DDR2 memory wishbone compatible if module
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        --- wishbone_master_mock - master wishbone interface connected to the memory slave interface; it generates a write burst followed by a read burst transaction


Tools used
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Xilinx ISE 14.4, Chipscope courtesy of Xilinx through Xilinx University Program.


Bench test
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FPGA proven toplevel module - top level module: test_DDR2_wb.v verified using Chipscope.


Known issues
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Attempt to move the PLL instance one level up in the hierarchy to test_DDR2_wb (test_DDR2_wb.v) resulted in the FPGA design not working.



genesys_ddr2 and OpenCores
==========================

This project is licensed under the GNU Public License version 3. 


About the same idea as with GNU project except we want free and open source
IP (intellectual property) cores. We design open source, synthesizable
cores. 

For more information visit us at http://www.opencores.org.