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[/] [genesys_ddr2/] [trunk/] [par/] [test_DDR2_wb.ucf] - Rev 2
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################################################################################ Xilinx, Inc. 2006 www.xilinx.com## Sat Nov 24 16:04:29 2012## Generated by MIG Version 3.6.1################################################################################ File name : mem_controller.ucf#### Details : Constraints file## FPGA family: virtex5## FPGA: xc5vlx50t-ff1136## Speedgrade: -3## Design Entry: VERILOG## Design: with Test bench## DCM Used: Disable## Two Bytes per Bank:Disable## No.Of Controllers: 1########################################################################################################################################################### Clock constraints ##############################################################################NET "clk0" TNM_NET = "SYS_clk0";#TIMESPEC "TS_SYS_clk0" = PERIOD "SYS_clk0" 8 ns HIGH 50 %;##NET "clk90" TNM_NET = "SYS_clk90";#TIMESPEC "TS_SYS_clk90" = PERIOD "SYS_clk90" "TS_SYS_clk0" PHASE 2 ns HIGH 50 %;##NET "clkdiv0" TNM_NET = "SYS_clkdiv0";#TIMESPEC "TS_SYS_clkdiv0" = PERIOD "SYS_clkdiv0" "TS_SYS_clk0" * 2 HIGH 50 %;##NET "clk200" TNM_NET = "SYS_clk200";#TIMESPEC "TS_SYS_clk200" = PERIOD "SYS_clk200" 5 ns HIGH 50 %;######################################################################### Controller 0# Memory Device: DDR2_SDRAM->SODIMMs->MT4HTF3264HY-667# Data Width: 64# Frequency: 125# Time Period: 8000# Data Mask: 1######################################################################################################################################################### I/O STANDARDS################################################################################NET "ddr2_dq[*]" IOSTANDARD = SSTL18_II_DCI;NET "ddr2_a[*]" IOSTANDARD = SSTL18_II;NET "ddr2_ba[*]" IOSTANDARD = SSTL18_II;NET "ddr2_ras_n" IOSTANDARD = SSTL18_II;NET "ddr2_cas_n" IOSTANDARD = SSTL18_II;NET "ddr2_we_n" IOSTANDARD = SSTL18_II;NET "ddr2_cs_n[*]" IOSTANDARD = SSTL18_II;NET "ddr2_odt[*]" IOSTANDARD = SSTL18_II;NET "ddr2_cke[*]" IOSTANDARD = SSTL18_II;NET "ddr2_dm[*]" IOSTANDARD = SSTL18_II_DCI;#NET "sys_rst_n" IOSTANDARD = LVCMOS18;#NET "phy_init_done" IOSTANDARD = LVCMOS18;#NET "error" IOSTANDARD = LVCMOS18;NET "ddr2_dqs[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;NET "ddr2_dqs_n[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;NET "ddr2_ck[*]" IOSTANDARD = DIFF_SSTL18_II;NET "ddr2_ck_n[*]" IOSTANDARD = DIFF_SSTL18_II;################################################################################# Location Constraints################################################################################NET "sysClk" LOC = "AG18" ; #Bank 12NET "sysRst" LOC = "G7" ; #Bank 22#NET "sw[0]" LOC = "L19" ; #Bank 22#NET "sw[1]" LOC = "L18" ; #Bank 22#NET "sw[2]" LOC = "K18" ; #Bank 22#NET "sw[3]" LOC = "H18" ; #Bank 22#NET "sw[4]" LOC = "H17" ; #Bank 22#NET "sw[5]" LOC = "k17" ; #Bank 22#NET "sw[6]" LOC = "G16" ; #Bank 22#NET "sw[7]" LOC = "G15" ; #Bank 22#NET "leds[0]" LOC = "AG8" ; #Bank 22#NET "leds[1]" LOC = "AH8" ; #Bank 22#NET "leds[2]" LOC = "AH9" ; #Bank 22#NET "leds[3]" LOC = "AG10" ; #Bank 22#NET "leds[4]" LOC = "AH10" ; #Bank 22#NET "leds[5]" LOC = "AG11" ; #Bank 22#NET "leds[6]" LOC = "AF11" ; #Bank 22#NET "leds[7]" LOC = "AE11" ; #Bank 22NET "ddr2_dq[0]" LOC = "AF30" ; #Bank 17NET "ddr2_dq[1]" LOC = "AK31" ; #Bank 17NET "ddr2_dq[2]" LOC = "AF31" ; #Bank 17NET "ddr2_dq[3]" LOC = "AD30" ; #Bank 17NET "ddr2_dq[4]" LOC = "AJ30" ; #Bank 17NET "ddr2_dq[5]" LOC = "AF29" ; #Bank 17NET "ddr2_dq[6]" LOC = "AD29" ; #Bank 17NET "ddr2_dq[7]" LOC = "AE29" ; #Bank 17NET "ddr2_dq[8]" LOC = "AH27" ; #Bank 21NET "ddr2_dq[9]" LOC = "AF28" ; #Bank 21NET "ddr2_dq[10]" LOC = "AH28" ; #Bank 21NET "ddr2_dq[11]" LOC = "AA28" ; #Bank 21NET "ddr2_dq[12]" LOC = "AG25" ; #Bank 21NET "ddr2_dq[13]" LOC = "AJ26" ; #Bank 21NET "ddr2_dq[14]" LOC = "AG28" ; #Bank 21NET "ddr2_dq[15]" LOC = "AB28" ; #Bank 21NET "ddr2_dq[16]" LOC = "AC28" ; #Bank 21NET "ddr2_dq[17]" LOC = "AB25" ; #Bank 21NET "ddr2_dq[18]" LOC = "AC27" ; #Bank 21NET "ddr2_dq[19]" LOC = "AA26" ; #Bank 21NET "ddr2_dq[20]" LOC = "AB26" ; #Bank 21NET "ddr2_dq[21]" LOC = "AA24" ; #Bank 21NET "ddr2_dq[22]" LOC = "AB27" ; #Bank 21NET "ddr2_dq[23]" LOC = "AA25" ; #Bank 21NET "ddr2_dq[24]" LOC = "AC29" ; #Bank 17NET "ddr2_dq[25]" LOC = "AB30" ; #Bank 17NET "ddr2_dq[26]" LOC = "W31" ; #Bank 17NET "ddr2_dq[27]" LOC = "V30" ; #Bank 17NET "ddr2_dq[28]" LOC = "AC30" ; #Bank 17NET "ddr2_dq[29]" LOC = "W29" ; #Bank 17NET "ddr2_dq[30]" LOC = "V27" ; #Bank 17NET "ddr2_dq[31]" LOC = "W27" ; #Bank 17NET "ddr2_dq[32]" LOC = "V29" ; #Bank 17NET "ddr2_dq[33]" LOC = "Y27" ; #Bank 17NET "ddr2_dq[34]" LOC = "Y26" ; #Bank 17NET "ddr2_dq[35]" LOC = "W24" ; #Bank 17NET "ddr2_dq[36]" LOC = "V28" ; #Bank 17NET "ddr2_dq[37]" LOC = "W25" ; #Bank 17NET "ddr2_dq[38]" LOC = "W26" ; #Bank 17NET "ddr2_dq[39]" LOC = "V24" ; #Bank 17NET "ddr2_dq[40]" LOC = "R24" ; #Bank 19NET "ddr2_dq[41]" LOC = "P25" ; #Bank 19NET "ddr2_dq[42]" LOC = "N24" ; #Bank 19NET "ddr2_dq[43]" LOC = "P26" ; #Bank 19NET "ddr2_dq[44]" LOC = "T24" ; #Bank 19NET "ddr2_dq[45]" LOC = "N25" ; #Bank 19NET "ddr2_dq[46]" LOC = "P27" ; #Bank 19NET "ddr2_dq[47]" LOC = "N28" ; #Bank 19NET "ddr2_dq[48]" LOC = "M28" ; #Bank 19NET "ddr2_dq[49]" LOC = "L28" ; #Bank 19NET "ddr2_dq[50]" LOC = "F25" ; #Bank 19NET "ddr2_dq[51]" LOC = "H25" ; #Bank 19NET "ddr2_dq[52]" LOC = "K27" ; #Bank 19NET "ddr2_dq[53]" LOC = "K28" ; #Bank 19NET "ddr2_dq[54]" LOC = "H24" ; #Bank 19NET "ddr2_dq[55]" LOC = "G26" ; #Bank 19NET "ddr2_dq[56]" LOC = "G25" ; #Bank 19NET "ddr2_dq[57]" LOC = "M26" ; #Bank 19NET "ddr2_dq[58]" LOC = "J24" ; #Bank 19NET "ddr2_dq[59]" LOC = "L26" ; #Bank 19NET "ddr2_dq[60]" LOC = "J27" ; #Bank 19NET "ddr2_dq[61]" LOC = "M25" ; #Bank 19NET "ddr2_dq[62]" LOC = "L25" ; #Bank 19NET "ddr2_dq[63]" LOC = "L24" ; #Bank 19NET "ddr2_a[12]" LOC = "T31" ; #Bank 15NET "ddr2_a[11]" LOC = "R29" ; #Bank 15NET "ddr2_a[10]" LOC = "J31" ; #Bank 15NET "ddr2_a[9]" LOC = "R28" ; #Bank 15NET "ddr2_a[8]" LOC = "M31" ; #Bank 15NET "ddr2_a[7]" LOC = "P30" ; #Bank 15NET "ddr2_a[6]" LOC = "P31" ; #Bank 15NET "ddr2_a[5]" LOC = "L31" ; #Bank 15NET "ddr2_a[4]" LOC = "K31" ; #Bank 15NET "ddr2_a[3]" LOC = "P29" ; #Bank 15NET "ddr2_a[2]" LOC = "N29" ; #Bank 15NET "ddr2_a[1]" LOC = "M30" ; #Bank 15NET "ddr2_a[0]" LOC = "L30" ; #Bank 15NET "ddr2_ba[1]" LOC = "J30" ; #Bank 15NET "ddr2_ba[0]" LOC = "G31" ; #Bank 15NET "ddr2_ras_n" LOC = "H30" ; #Bank 15NET "ddr2_cas_n" LOC = "E31" ; #Bank 15NET "ddr2_we_n" LOC = "K29" ; #Bank 15NET "ddr2_cs_n[0]" LOC = "L29" ; #Bank 15NET "ddr2_odt[0]" LOC = "F31" ; #Bank 15NET "ddr2_cke[0]" LOC = "T28" ; #Bank 15NET "ddr2_dm[0]" LOC = "AJ31" ; #Bank 17NET "ddr2_dm[1]" LOC = "AE28" ; #Bank 21NET "ddr2_dm[2]" LOC = "Y24" ; #Bank 21NET "ddr2_dm[3]" LOC = "Y31" ; #Bank 17NET "ddr2_dm[4]" LOC = "V25" ; #Bank 17NET "ddr2_dm[5]" LOC = "P24" ; #Bank 19NET "ddr2_dm[6]" LOC = "F26" ; #Bank 19NET "ddr2_dm[7]" LOC = "J25" ; #Bank 19NET "ddr2_dqs[0]" LOC = "AA29" ; #Bank 17NET "ddr2_dqs_n[0]" LOC = "AA30" ; #Bank 17NET "ddr2_dqs[1]" LOC = "AK28" ; #Bank 21NET "ddr2_dqs_n[1]" LOC = "AK27" ; #Bank 21NET "ddr2_dqs[2]" LOC = "AK26" ; #Bank 21NET "ddr2_dqs_n[2]" LOC = "AJ27" ; #Bank 21NET "ddr2_dqs[3]" LOC = "AB31" ; #Bank 17NET "ddr2_dqs_n[3]" LOC = "AA31" ; #Bank 17NET "ddr2_dqs[4]" LOC = "Y28" ; #Bank 17NET "ddr2_dqs_n[4]" LOC = "Y29" ; #Bank 17NET "ddr2_dqs[5]" LOC = "E26" ; #Bank 19NET "ddr2_dqs_n[5]" LOC = "E27" ; #Bank 19NET "ddr2_dqs[6]" LOC = "H28" ; #Bank 19NET "ddr2_dqs_n[6]" LOC = "G28" ; #Bank 19NET "ddr2_dqs[7]" LOC = "G27" ; #Bank 19NET "ddr2_dqs_n[7]" LOC = "H27" ; #Bank 19NET "ddr2_ck[0]" LOC = "AK29" ; #Bank 21NET "ddr2_ck_n[0]" LOC = "AJ29" ; #Bank 21NET "ddr2_ck[1]" LOC = "E28" ; #Bank 19NET "ddr2_ck_n[1]" LOC = "F28" ; #Bank 19#####################LEDS#NET "error" LOC = "AG8";#NET "error_cmp" LOC = "AH8";################################################################################ Define multicycle paths - these paths may take longer because additional# time allowed for logic to settle in calibration/initialization FSM################################################################################## MIG 2.1: Eliminate Timegroup definitions for CLK0, and CLK90. Instead trace## multicycle paths from originating flip-flop to ANY destination## flip-flop (or in some cases, it can also be a BRAM)## MUX Select for either rising/falling CLK0 for 2nd stage read capture#INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";#TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO FFS#"TS_SYS_clk0" * 4;## MUX select for read data - optional delay on data to account for byte skews#INST "*/u_usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";#TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO FFS#"TS_SYS_clk0" * 4;## Calibration/Initialization complete status flag (for PHY logic only) - can## be used to drive both flip-flops and BRAMs#INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";#TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO FFS#"TS_SYS_clk0" * 4;## The RAM path is only used in cases where Write Latency (Additive Latency +## (CAS Latency - 1) + (1 in case of RDIMM)) is 2 or below. So these constraints are## valid for CAS Latency = 3, Additive Latency = 0 and selected part is not RDIMM.## If Write Latency is higher than 3, then a warning will appear in PAR,## and the constraint can be ignored as this path does not exist. RAM constraint## can be safely removed if the warning is not to be displayed.#TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO RAMS#"TS_SYS_clk0" * 4;## Select (address) bits for SRL32 shift registers used in stage3/stage4## calibration#INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";#TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO FFS "TS_SYS_clk0" * 4;##INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";#TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO FFS "TS_SYS_clk0" * 4;##INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly"# TNM = "TNM_CAL_RDEN_DLY";#TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO FFS#"TS_SYS_clk0" * 4;##################################################################################The following constraint is added to prevent (false) hold time violations on##the data path from stage1 to stage2 capture flops. Stage1 flops are clocked by##the delayed DQS and stage2 flops are clocked by the clk0 clock. Placing a TIG##on the DQ IDDR capture flop instance to achieve this is acceptable because timing##is guaranteed through the use of separate Predictable IP constraints. These##violations are reported when anunconstrained path report is run.#################################################################################INST "*/gen_dq[*].u_iob_dq/gen*.u_iddr_dq" TIG ;################################################################################## DQS Read Post amble Glitch Squelch circuit related constraints################################################################################################################################################################### LOC placement of DQS-squelch related IDDR and IDELAY elements## Each circuit can be located at any of the following locations:## 1. Unused "N"-side of DQS differential pair I/O## 2. DM data mask (output only, input side is free for use)## 3. Any output-only site###################################################################################################################################################################The following constraint is added to avoid the HOLD violations in the trace report##when run for unconstrained paths.These two FF groups will be clocked by two different## clocks and hence there should be no timing analysis performed on this path.#################################################################################INST "*/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[*].u_en_dqs_ff" TNM = EN_DQS_FF;#TIMESPEC TS_FROM_EN_DQS_FF_TO_DQ_CE_FF = FROM EN_DQS_FF TO TNM_DQ_CE_IDDR 3.85 ns DATAPATHONLY;##INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y56";#INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y56";#INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y18";#INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y18";#INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y22";#INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y22";#INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y60";#INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y60";#INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y62";#INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y62";#INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y216";#INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y216";#INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y220";#INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y220";#INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y222";#INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y222";################################################################################### LOC and timing constraints for flop driving DQS CE enable signal## from fabric logic. Even though the absolute delay on this path is## calibrated out (when synchronizing this output to DQS), the delay## should still be kept as low as possible to reduce post-calibration## voltage/temp variations - these are roughly proportional to the## absolute delay of the path.## The following code has been commented for V5 as the predictable IP will take## care of placement of these flops by meeting the MAXDELAY requirement.## These constraints will be removed in the next release.##################################################################################INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff" LOC = SLICE_X0Y28;#INST "*/u_phy_calib/gen_gate[1].u_en_dqs_ff" LOC = SLICE_X0Y9;#INST "*/u_phy_calib/gen_gate[2].u_en_dqs_ff" LOC = SLICE_X0Y11;#INST "*/u_phy_calib/gen_gate[3].u_en_dqs_ff" LOC = SLICE_X0Y30;#INST "*/u_phy_calib/gen_gate[4].u_en_dqs_ff" LOC = SLICE_X0Y31;#INST "*/u_phy_calib/gen_gate[5].u_en_dqs_ff" LOC = SLICE_X0Y108;#INST "*/u_phy_calib/gen_gate[6].u_en_dqs_ff" LOC = SLICE_X0Y110;#INST "*/u_phy_calib/gen_gate[7].u_en_dqs_ff" LOC = SLICE_X0Y111;### Control for DQS gate - from fabric flop. Prevent "runaway" delay -## two parts to this path: (1) from fabric flop to IDELAY, (2) from## IDELAY to asynchronous reset of IDDR that drives the DQ CE's## This can be relaxed by the user for lower frequencies:## 300MHz = 850ps, 267MHz = 900ps. At 200MHz = 950ps.## In general PAR should be able to route this## within 900ps over all speed grades.#NET "*/u_phy_io/en_dqs[*]" MAXDELAY = 600 ps;#NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 800 ps;################################################################################### "Half-cycle" path constraint from IOB flip-flop to CE pin for all DQ IDDR's## for DQS Read Post amble Glitch Squelch circuit################################################################################### Max delay from output of IOB flip-flop to CE input of DQ IDDRs =## tRPST + some slack where slack account for rise-time of DQS on board.## For now assume slack = 0.400ns (based on initial SPICE simulations,## assumes use of ODT), so time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz#INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";#INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";#TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 3.6 ns;##