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<h1>struct Architecture Reference</h1><!-- doxytag: class="fir_filter_stage::struct" --><!-- doxytag: inherits="multiplier_gen,delay_gen,adder_gen" --><div class="dynheader">
Inheritance diagram for struct:</div>
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<img src="classfir__filter__stage_1_1struct.png" usemap="#struct_map" alt=""/>
<map id="struct_map" name="struct_map">
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<area href="classdelay__gen.html" alt="delay_gen" shape="rect" coords="103,56,196,80"/>
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<p><a href="classfir__filter__stage_1_1struct-members.html">List of all members.</a></p>
<table border="0" cellpadding="0" cellspacing="0">
<br/>
<br/>
<tr><td colspan="2"><h2>Components</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6f9e1a961a64ab0041ac0707ee40c821"></a><!-- doxytag: member="fir_filter_stage::struct::multiplier_gen" ref="a6f9e1a961a64ab0041ac0707ee40c821" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#a6f9e1a961a64ab0041ac0707ee40c821">multiplier_gen</a> </td><td class="memItemRight" valign="bottom"><b></b> <em><a class="el" href="classmultiplier__gen.html"><Entity multiplier_gen> </a></em></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab3cadb9f82a00f0361b33c19dff6ae52"></a><!-- doxytag: member="fir_filter_stage::struct::adder_gen" ref="ab3cadb9f82a00f0361b33c19dff6ae52" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#ab3cadb9f82a00f0361b33c19dff6ae52">adder_gen</a> </td><td class="memItemRight" valign="bottom"><b></b> <em><a class="el" href="classadder__gen.html"><Entity adder_gen> </a></em></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a924bfda8c3c384807bfb8ae15d7953ba"></a><!-- doxytag: member="fir_filter_stage::struct::delay_gen" ref="a924bfda8c3c384807bfb8ae15d7953ba" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#a924bfda8c3c384807bfb8ae15d7953ba">delay_gen</a> </td><td class="memItemRight" valign="bottom"><b></b> <em><a class="el" href="classdelay__gen.html"><Entity delay_gen> </a></em></td></tr>
<tr><td colspan="2"><h2>Constants</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a330ffb2824b41caf8498abff7e518e47"></a><!-- doxytag: member="fir_filter_stage::struct::coeff" ref="a330ffb2824b41caf8498abff7e518e47" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#a330ffb2824b41caf8498abff7e518e47">coeff</a> </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">int_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">:</span><span class="vhdlchar">=</span><span class="vhdlchar"> </span><b><a class="el" href="classfir__pkg.html#a486aad2342db0548481997fb31149609">fir_coeff_thirdstage</a></b> <span class="vhdlchar"> </span></b></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Filter coefficients defined in the <a class="el" href="fir__pkg_8vhd.html">fir_pkg.vhd</a>. <br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="adaa2b6c5cbc1def261e9acc0c3c7007c"></a><!-- doxytag: member="fir_filter_stage::struct::width_in" ref="adaa2b6c5cbc1def261e9acc0c3c7007c" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#adaa2b6c5cbc1def261e9acc0c3c7007c">width_in</a> </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">natural</span><span class="vhdlchar"> </span><span class="vhdlchar">:</span><span class="vhdlchar">=</span><span class="vhdlchar"> </span><b><a class="el" href="classfir__filter__stage.html#ab508794e1ce35c2946d28703f4ebca9f">fir_in</a></b> <span class="vhdlchar"> </span><span class="vhdlchar">'</span><span class="vhdlchar"> </span><span class="vhdlchar">length</span><span class="vhdlchar"> </span></b></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Input bit-width. <br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a165792aa281447ef621e7ddd34725db6"></a><!-- doxytag: member="fir_filter_stage::struct::width_out" ref="a165792aa281447ef621e7ddd34725db6" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#a165792aa281447ef621e7ddd34725db6">width_out</a> </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">natural</span><span class="vhdlchar"> </span><span class="vhdlchar">:</span><span class="vhdlchar">=</span><span class="vhdlchar"> </span><b><a class="el" href="classfir__filter__stage.html#ae7fe87ee8521c3fce91172c78537df25">fir_out</a></b> <span class="vhdlchar"> </span><span class="vhdlchar">'</span><span class="vhdlchar"> </span><span class="vhdlchar">length</span><span class="vhdlchar"> </span></b></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Output bit-width. <br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a339f911ca5cb1a8748960755c77bc225"></a><!-- doxytag: member="fir_filter_stage::struct::width_const" ref="a339f911ca5cb1a8748960755c77bc225" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#a339f911ca5cb1a8748960755c77bc225">width_const</a> </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">positive</span><span class="vhdlchar"> </span><span class="vhdlchar">:</span><span class="vhdlchar">=</span><span class="vhdlchar"> </span><b><a class="el" href="classfir__pkg.html#a9412e753e9f662ae363ff33d552c55ce">quantization</a></b> <span class="vhdlchar"> </span></b></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Quantization bit-width defined in the <a class="el" href="fir__pkg_8vhd.html">fir_pkg.vhd</a>. <br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae89b33d7dfd2fe34210bd34e95eff9e4"></a><!-- doxytag: member="fir_filter_stage::struct::order" ref="ae89b33d7dfd2fe34210bd34e95eff9e4" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#ae89b33d7dfd2fe34210bd34e95eff9e4">order</a> </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">natural</span><span class="vhdlchar"> </span><span class="vhdlchar">:</span><span class="vhdlchar">=</span><span class="vhdlchar"> </span><b><a class="el" href="classfir__filter__stage_1_1struct.html#a330ffb2824b41caf8498abff7e518e47">coeff</a></b> <span class="vhdlchar"> </span><span class="vhdlchar">'</span><span class="vhdlchar"> </span><span class="vhdlchar">length</span><span class="vhdlchar"> </span></b></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Filter length. <br/></td></tr>
<tr><td colspan="2"><h2>Signals</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4205437c41382c6434ab00bb83e1a3f7"></a><!-- doxytag: member="fir_filter_stage::struct::multi_add" ref="a4205437c41382c6434ab00bb83e1a3f7" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#a4205437c41382c6434ab00bb83e1a3f7">multi_add</a> </td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><b><a class="el" href="classfir__filter__stage_1_1struct.html#ae89b33d7dfd2fe34210bd34e95eff9e4">order</a></b> <span class="vhdlchar">-</span><span class="vhdldigit">1</span><span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span><span class="vhdlchar">*</span><b><a class="el" href="classfir__filter__stage_1_1struct.html#a165792aa281447ef621e7ddd34725db6">width_out</a></b> <span class="vhdlchar">-</span><span class="vhdldigit">1</span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdldigit">0</span><span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Internal signal holding multiplier's outputs and adder's inputs. <br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a862700b81c83534570de1c1c8febd189"></a><!-- doxytag: member="fir_filter_stage::struct::add_delay" ref="a862700b81c83534570de1c1c8febd189" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#a862700b81c83534570de1c1c8febd189">add_delay</a> </td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><b><a class="el" href="classfir__filter__stage_1_1struct.html#ae89b33d7dfd2fe34210bd34e95eff9e4">order</a></b> <span class="vhdlchar">-</span><span class="vhdldigit">2</span><span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span><span class="vhdlchar">*</span><b><a class="el" href="classfir__filter__stage_1_1struct.html#a165792aa281447ef621e7ddd34725db6">width_out</a></b> <span class="vhdlchar">-</span><span class="vhdldigit">1</span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdldigit">0</span><span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Internal signal holding adder's outputs and delay's inputs. <br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af0bb5234fc4334060df784c2d6bcd6eb"></a><!-- doxytag: member="fir_filter_stage::struct::delay_add" ref="af0bb5234fc4334060df784c2d6bcd6eb" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#af0bb5234fc4334060df784c2d6bcd6eb">delay_add</a> </td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><b><a class="el" href="classfir__filter__stage_1_1struct.html#ae89b33d7dfd2fe34210bd34e95eff9e4">order</a></b> <span class="vhdlchar">-</span><span class="vhdldigit">1</span><span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span><span class="vhdlchar">*</span><b><a class="el" href="classfir__filter__stage_1_1struct.html#a165792aa281447ef621e7ddd34725db6">width_out</a></b> <span class="vhdlchar">-</span><span class="vhdldigit">1</span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdldigit">0</span><span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Internal signal holding delay's output and adder's inputs. <br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6fb55cb2f3a509091c7a3a04d9fe844f"></a><!-- doxytag: member="fir_filter_stage::struct::multi_delay" ref="a6fb55cb2f3a509091c7a3a04d9fe844f" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#a6fb55cb2f3a509091c7a3a04d9fe844f">multi_delay</a> </td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><b><a class="el" href="classfir__filter__stage_1_1struct.html#a165792aa281447ef621e7ddd34725db6">width_out</a></b> <span class="vhdlchar">-</span><span class="vhdldigit">1</span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdldigit">0</span><span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">internal signal for the left most multiplier since it is connected directly to delay <br/></td></tr>
<tr><td colspan="2"><h2>Component Instantiations</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abd4c2cf4810e81ae22a38305fd433e1a"></a><!-- doxytag: member="fir_filter_stage::struct::MULTI" ref="abd4c2cf4810e81ae22a38305fd433e1a" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#abd4c2cf4810e81ae22a38305fd433e1a">MULTI</a> </td><td class="memItemRight" valign="bottom"><b>multiplier_gen</b> <em><a class="el" href="classmultiplier__gen.html"><Entity multiplier_gen></a></em></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Generate the filter multipliers set. <br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5ec8e2ec5fae2030c1304157beece49f"></a><!-- doxytag: member="fir_filter_stage::struct::MULTIs" ref="a5ec8e2ec5fae2030c1304157beece49f" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#a5ec8e2ec5fae2030c1304157beece49f">MULTIs</a> </td><td class="memItemRight" valign="bottom"><b>multiplier_gen</b> <em><a class="el" href="classmultiplier__gen.html"><Entity multiplier_gen></a></em></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab73297ef7e9ada93294ea90b438e5c38"></a><!-- doxytag: member="fir_filter_stage::struct::LastDELAY" ref="ab73297ef7e9ada93294ea90b438e5c38" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#ab73297ef7e9ada93294ea90b438e5c38">LastDELAY</a> </td><td class="memItemRight" valign="bottom"><b>delay_gen</b> <em><a class="el" href="classdelay__gen.html"><Entity delay_gen></a></em></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Generate the filter delay set. <br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a608b6f687e967f2a2f299ff0e0054186"></a><!-- doxytag: member="fir_filter_stage::struct::DELAYs" ref="a608b6f687e967f2a2f299ff0e0054186" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#a608b6f687e967f2a2f299ff0e0054186">DELAYs</a> </td><td class="memItemRight" valign="bottom"><b>delay_gen</b> <em><a class="el" href="classdelay__gen.html"><Entity delay_gen></a></em></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0b2df459bab2f96d35693f23aa035b85"></a><!-- doxytag: member="fir_filter_stage::struct::ADDER0" ref="a0b2df459bab2f96d35693f23aa035b85" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#a0b2df459bab2f96d35693f23aa035b85">ADDER0</a> </td><td class="memItemRight" valign="bottom"><b>adder_gen</b> <em><a class="el" href="classadder__gen.html"><Entity adder_gen></a></em></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6f5117e2d020b31913e8fe1f794fe13d"></a><!-- doxytag: member="fir_filter_stage::struct::ADDERs" ref="a6f5117e2d020b31913e8fe1f794fe13d" args="" -->
<a class="el" href="classfir__filter__stage_1_1struct.html#a6f5117e2d020b31913e8fe1f794fe13d">ADDERs</a> </td><td class="memItemRight" valign="bottom"><b>adder_gen</b> <em><a class="el" href="classadder__gen.html"><Entity adder_gen></a></em></td></tr>
</table>
<hr/>The documentation for this class was generated from the following file:<ul>
<li>src/<a class="el" href="fir__filter__stage_8vhd.html">fir_filter_stage.vhd</a></li>
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