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<h1>fir_filter_stage_DF Entity Reference</h1> </div>
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<!-- doxytag: class="fir_filter_stage_DF" --><!-- doxytag: inherits="fir_filter_stage_DF::struct" --><div class="dynheader">
Inheritance diagram for fir_filter_stage_DF:</div>
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<img src="classfir__filter__stage__DF.png" usemap="#fir_filter_stage_DF_map" alt=""/>
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<area href="classmultiplier__gen.html" alt="multiplier_gen" shape="rect" coords="0,56,117,80"/>
<area href="classdelay__gen.html" alt="delay_gen" shape="rect" coords="127,56,244,80"/>
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<p><a href="classfir__filter__stage__DF-members.html">List of all members.</a></p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="nested-classes"></a>
Architectures</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classfir__filter__stage__DF_1_1struct.html">struct</a> </td><td class="memItemRight" valign="bottom"><b>Architecture </b></td></tr>
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Libraries</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classfir__filter__stage__DF.html#acbe0bfecfa56fa4103ea80a491bfdbc8">ieee</a> </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td colspan="2"><h2><a name="pub-attribs"></a>
Packages</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a75f07bd8bde6f849270ce9de65573a4f"></a><!-- doxytag: member="fir_filter_stage_DF::std_logic_1164" ref="a75f07bd8bde6f849270ce9de65573a4f" args="" -->
<a class="el" href="classfir__filter__stage__DF.html#a75f07bd8bde6f849270ce9de65573a4f">std_logic_1164</a> </td><td class="memItemRight" valign="bottom"> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afa3f6e309d54fde7de3148deddb32c77"></a><!-- doxytag: member="fir_filter_stage_DF::std_logic_arith" ref="afa3f6e309d54fde7de3148deddb32c77" args="" -->
<a class="el" href="classfir__filter__stage__DF.html#afa3f6e309d54fde7de3148deddb32c77">std_logic_arith</a> </td><td class="memItemRight" valign="bottom"> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5cb95d6cc481013a3f10b88926230077"></a><!-- doxytag: member="fir_filter_stage_DF::std_logic_unsigned" ref="a5cb95d6cc481013a3f10b88926230077" args="" -->
<a class="el" href="classfir__filter__stage__DF.html#a5cb95d6cc481013a3f10b88926230077">std_logic_unsigned</a> </td><td class="memItemRight" valign="bottom"> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8fcee58e05e809c9790c3821c9735d3c"></a><!-- doxytag: member="fir_filter_stage_DF::fir_pkg" ref="a8fcee58e05e809c9790c3821c9735d3c" args="" -->
<a class="el" href="classfir__filter__stage__DF.html#a8fcee58e05e809c9790c3821c9735d3c">fir_pkg</a> </td><td class="memItemRight" valign="bottom"> <b>Package</b><em><a class="el" href="classfir__pkg.html"> <fir_pkg></a></td></tr>
<tr><td colspan="2"><h2><a name="pub-attribs"></a>
Ports</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a89651e2933897b977b23c53fec93c9e0"></a><!-- doxytag: member="fir_filter_stage_DF::fir_clk" ref="a89651e2933897b977b23c53fec93c9e0" args="std_logic;" -->
<a class="el" href="classfir__filter__stage__DF.html#a89651e2933897b977b23c53fec93c9e0">fir_clk</a> </td><td class="memItemRight" valign="bottom"> <b>in</b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Rising edge clock. <br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab88437b89f2e0b1588b987872e23698f"></a><!-- doxytag: member="fir_filter_stage_DF::fir_clr" ref="ab88437b89f2e0b1588b987872e23698f" args="std_logic;" -->
<a class="el" href="classfir__filter__stage__DF.html#ab88437b89f2e0b1588b987872e23698f">fir_clr</a> </td><td class="memItemRight" valign="bottom"> <b>in</b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Active high asynchronous reset. <br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab508794e1ce35c2946d28703f4ebca9f"></a><!-- doxytag: member="fir_filter_stage_DF::fir_in" ref="ab508794e1ce35c2946d28703f4ebca9f" args="std_logic_vector(0 downto 0);" -->
<a class="el" href="classfir__filter__stage__DF.html#ab508794e1ce35c2946d28703f4ebca9f">fir_in</a> </td><td class="memItemRight" valign="bottom"> <b>in</b> <b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdldigit">0</span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdldigit">0</span><span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Unsigned single/multi-bit input. <br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae7fe87ee8521c3fce91172c78537df25"></a><!-- doxytag: member="fir_filter_stage_DF::fir_out" ref="ae7fe87ee8521c3fce91172c78537df25" args="std_logic_vector(14 downto 0);" -->
<a class="el" href="classfir__filter__stage__DF.html#ae7fe87ee8521c3fce91172c78537df25">fir_out</a> </td><td class="memItemRight" valign="bottom"> <b>out</b> <b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdldigit">14</span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdldigit">0</span><span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Signed multi-bit output. <br/></td></tr>
</table>
<hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="acbe0bfecfa56fa4103ea80a491bfdbc8"></a><!-- doxytag: member="fir_filter_stage_DF::ieee" ref="acbe0bfecfa56fa4103ea80a491bfdbc8" args="" -->
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<td class="memname"><a class="el" href="classfir__filter__stage__DF.html#acbe0bfecfa56fa4103ea80a491bfdbc8">ieee</a> <b><span class="vhdlkeyword">library</span><span class="vhdlchar"> </span></b> <code> [Library]</code></td>
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<div align="center">
<img src="firDF.png" alt="firDF.png"/>
<p><strong>Direct-form FIR Filter Structure</strong></p></div>
<dl class="author"><dt><b>Author:</b></dt><dd>Ahmed Shahein <a href="mailto:ahmed.shahein@ieee.org">ahmed.shahein@ieee.org</a> </dd></dl>
<dl class="date"><dt><b>Date:</b></dt><dd>04.2012 </dd></dl>
<p>Reimplemented from <a class="el" href="classadder__gen.html">adder_gen</a>.</p>
</div>
</div>
<hr/>The documentation for this class was generated from the following file:<ul>
<li>src/<a class="el" href="fir__filter__stage__DF_8vhd.html">fir_filter_stage_DF.vhd</a></li>
</ul>
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