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<h1>src/fir_filter_stage.vhd File Reference</h1>
<p>This is the top-level design for a transposed-form FIR digital filter. <br/>
It instantiate the three major components for constructing a digital filter such as; <br/>
adder (<a class="el" href="classadder__gen.html">adder_gen</a>), multiplier (<a class="el" href="classmultiplier__gen.html">multiplier_gen</a>), and delay (<a class="el" href="classdelay__gen.html">delay_gen</a>). <br/>
The top-level is a structural description in a generic/scalable form. <br/>
The filter coefficients and the quantization bit width should be edited/pasted <br/>
into the <a class="el" href="fir__pkg_8vhd.html">fir_pkg.vhd</a>. The filter coefficients should be given in integer format. <br/>
Design specs: <br/>
Unsigned single/multi-bit input (fir_in) <br/>
Signed multi-bit output (fir_out) <br/>
Active high asynchronous reset (fir_clr) <br/>
Rising edge clock (fir_clk) <br/>
.
<a href="#_details">More...</a></p>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classfir__filter__stage.html">fir_filter_stage</a> </td><td class="memItemRight" valign="bottom"><b>Entity </b></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classfir__filter__stage_1_1struct.html">struct</a> </td><td class="memItemRight" valign="bottom"><b>Architecture </b></td></tr>
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<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>This is the top-level design for a transposed-form FIR digital filter. <br/>
It instantiate the three major components for constructing a digital filter such as; <br/>
adder (<a class="el" href="classadder__gen.html">adder_gen</a>), multiplier (<a class="el" href="classmultiplier__gen.html">multiplier_gen</a>), and delay (<a class="el" href="classdelay__gen.html">delay_gen</a>). <br/>
The top-level is a structural description in a generic/scalable form. <br/>
The filter coefficients and the quantization bit width should be edited/pasted <br/>
into the <a class="el" href="fir__pkg_8vhd.html">fir_pkg.vhd</a>. The filter coefficients should be given in integer format. <br/>
Design specs: <br/>
Unsigned single/multi-bit input (fir_in) <br/>
Signed multi-bit output (fir_out) <br/>
Active high asynchronous reset (fir_clr) <br/>
Rising edge clock (fir_clk) <br/>
. </p>
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