OpenCores
URL https://opencores.org/ocsvn/gnextrapolator/gnextrapolator/trunk

Subversion Repositories gnextrapolator

[/] [gnextrapolator/] [trunk/] [QuartusII/] [db/] [gnextrapolator.fit.qmsg] - Rev 5

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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 14 00:27:38 2012 " "Info: Processing started: Tue Aug 14 00:27:38 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator " "Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "gnextrapolator EP2S15F484C4 " "Info: Selected device EP2S15F484C4 for design \"gnextrapolator\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." {  } {  } 0 0 "Feature %1!s! is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2S15F484I4 " "Info: Device EP2S15F484I4 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~DATA0~ E13 " "Info: Pin ~DATA0~ is reserved at location E13" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { ~DATA0~ } } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 1021 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "107 107 " "Critical Warning: No exact pin location assignment(s) for 107 pins of 107 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[0\] " "Info: Pin fxx_o\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 146 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[1\] " "Info: Pin fxx_o\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 144 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[2\] " "Info: Pin fxx_o\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 142 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[3\] " "Info: Pin fxx_o\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 140 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[4\] " "Info: Pin fxx_o\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 138 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[5\] " "Info: Pin fxx_o\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 136 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[6\] " "Info: Pin fxx_o\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 134 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[7\] " "Info: Pin fxx_o\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 132 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[8\] " "Info: Pin fxx_o\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 130 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[9\] " "Info: Pin fxx_o\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 128 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[10\] " "Info: Pin fxx_o\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 126 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[11\] " "Info: Pin fxx_o\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 124 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[12\] " "Info: Pin fxx_o\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 122 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[13\] " "Info: Pin fxx_o\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 120 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[14\] " "Info: Pin fxx_o\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 118 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[15\] " "Info: Pin fxx_o\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 116 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[0\] " "Info: Pin fxx1_o\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 178 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[1\] " "Info: Pin fxx1_o\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 176 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[2\] " "Info: Pin fxx1_o\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 174 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[3\] " "Info: Pin fxx1_o\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 172 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[4\] " "Info: Pin fxx1_o\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 170 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[5\] " "Info: Pin fxx1_o\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 168 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[6\] " "Info: Pin fxx1_o\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 166 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[7\] " "Info: Pin fxx1_o\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 164 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[8\] " "Info: Pin fxx1_o\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 162 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[9\] " "Info: Pin fxx1_o\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 160 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[10\] " "Info: Pin fxx1_o\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 158 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[11\] " "Info: Pin fxx1_o\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 156 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[12\] " "Info: Pin fxx1_o\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 154 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[13\] " "Info: Pin fxx1_o\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 152 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[14\] " "Info: Pin fxx1_o\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 150 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[15\] " "Info: Pin fxx1_o\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 148 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[0\] " "Info: Pin fxx2_o\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 210 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[1\] " "Info: Pin fxx2_o\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 208 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[2\] " "Info: Pin fxx2_o\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 206 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[3\] " "Info: Pin fxx2_o\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 204 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[4\] " "Info: Pin fxx2_o\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 202 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[5\] " "Info: Pin fxx2_o\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 200 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[6\] " "Info: Pin fxx2_o\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 198 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[7\] " "Info: Pin fxx2_o\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 196 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[8\] " "Info: Pin fxx2_o\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 194 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[9\] " "Info: Pin fxx2_o\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 192 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[10\] " "Info: Pin fxx2_o\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 190 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[11\] " "Info: Pin fxx2_o\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 188 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[12\] " "Info: Pin fxx2_o\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 186 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[13\] " "Info: Pin fxx2_o\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 184 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[14\] " "Info: Pin fxx2_o\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 182 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[15\] " "Info: Pin fxx2_o\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 180 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[0\] " "Info: Pin fxx3_o\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 242 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[1\] " "Info: Pin fxx3_o\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 240 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[2\] " "Info: Pin fxx3_o\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 238 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[3\] " "Info: Pin fxx3_o\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 236 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[4\] " "Info: Pin fxx3_o\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 234 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[5\] " "Info: Pin fxx3_o\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 232 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[6\] " "Info: Pin fxx3_o\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 230 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[7\] " "Info: Pin fxx3_o\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 228 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[8\] " "Info: Pin fxx3_o\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 226 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[9\] " "Info: Pin fxx3_o\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 224 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[10\] " "Info: Pin fxx3_o\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 222 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[11\] " "Info: Pin fxx3_o\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 220 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[12\] " "Info: Pin fxx3_o\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 218 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[13\] " "Info: Pin fxx3_o\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 216 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[14\] " "Info: Pin fxx3_o\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 214 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[15\] " "Info: Pin fxx3_o\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 212 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[0\] " "Info: Pin fxx4_o\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 274 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[1\] " "Info: Pin fxx4_o\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 272 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[2\] " "Info: Pin fxx4_o\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 270 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[3\] " "Info: Pin fxx4_o\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 268 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[4\] " "Info: Pin fxx4_o\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 266 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[5\] " "Info: Pin fxx4_o\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 264 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[6\] " "Info: Pin fxx4_o\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 262 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[7\] " "Info: Pin fxx4_o\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 260 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[8\] " "Info: Pin fxx4_o\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 258 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[9\] " "Info: Pin fxx4_o\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 256 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[10\] " "Info: Pin fxx4_o\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 254 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[11\] " "Info: Pin fxx4_o\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 252 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[12\] " "Info: Pin fxx4_o\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 250 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[13\] " "Info: Pin fxx4_o\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 248 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[14\] " "Info: Pin fxx4_o\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 246 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[15\] " "Info: Pin fxx4_o\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 244 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[0\] " "Info: Pin resul_o\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 306 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[1\] " "Info: Pin resul_o\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 304 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[2\] " "Info: Pin resul_o\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 302 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[3\] " "Info: Pin resul_o\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 300 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[4\] " "Info: Pin resul_o\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 298 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[5\] " "Info: Pin resul_o\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 296 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[6\] " "Info: Pin resul_o\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 294 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[7\] " "Info: Pin resul_o\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 292 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[8\] " "Info: Pin resul_o\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 290 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[9\] " "Info: Pin resul_o\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 288 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[10\] " "Info: Pin resul_o\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 286 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[11\] " "Info: Pin resul_o\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 284 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[12\] " "Info: Pin resul_o\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 282 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[13\] " "Info: Pin resul_o\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 280 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[14\] " "Info: Pin resul_o\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 278 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[15\] " "Info: Pin resul_o\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 276 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "extrapolar_i " "Info: Pin extrapolar_i not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { extrapolar_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 54 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { extrapolar_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 328 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk_i " "Info: Pin clk_i not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { clk_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 327 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rst_i " "Info: Pin rst_i not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { rst_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 51 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 326 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[5\] " "Info: Pin distancia_i\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 313 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[3\] " "Info: Pin distancia_i\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 311 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[4\] " "Info: Pin distancia_i\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 312 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[2\] " "Info: Pin distancia_i\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 310 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[0\] " "Info: Pin distancia_i\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 308 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[1\] " "Info: Pin distancia_i\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 309 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[6\] " "Info: Pin distancia_i\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 314 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[7\] " "Info: Pin distancia_i\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 315 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1}  } {  } 1 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 0 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Timing-driven compilation is using the Classic Timing Analyzer" {  } {  } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_i (placed in PIN N20 (CLK3p, Input)) " "Info: Automatically promoted node clk_i (placed in PIN N20 (CLK3p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { clk_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 327 3016 4149 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_i (placed in PIN M21 (CLK1p, Input)) " "Info: Automatically promoted node rst_i (placed in PIN M21 (CLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "resultado\[0\] " "Info: Destination node resultado\[0\]" {  } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resultado[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 110 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[15\]~reg0 " "Info: Destination node fxx_o\[15\]~reg0" {  } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[15]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 117 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[14\]~reg0 " "Info: Destination node fxx_o\[14\]~reg0" {  } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[14]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 119 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[13\]~reg0 " "Info: Destination node fxx_o\[13\]~reg0" {  } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[13]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 121 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[12\]~reg0 " "Info: Destination node fxx_o\[12\]~reg0" {  } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[12]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 123 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[11\]~reg0 " "Info: Destination node fxx_o\[11\]~reg0" {  } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[11]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 125 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[10\]~reg0 " "Info: Destination node fxx_o\[10\]~reg0" {  } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[10]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 127 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[9\]~reg0 " "Info: Destination node fxx_o\[9\]~reg0" {  } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[9]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 129 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[8\]~reg0 " "Info: Destination node fxx_o\[8\]~reg0" {  } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[8]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 131 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[7\]~reg0 " "Info: Destination node fxx_o\[7\]~reg0" {  } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[7]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 133 3016 4149 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" {  } {  } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { rst_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 51 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 326 3016 4149 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1}  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "105 unused 3.3V 9 96 0 " "Info: Number of I/O pins in group: 105 (unused VREF, 3.3V VCCIO, 9 input, 96 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 39 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  39 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 43 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  43 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 49 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  49 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 35 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  35 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 44 " "Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  44 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 40 " "Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 34 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  34 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 0 6 " "Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use undetermined 0 6 " "Info: I/O bank number 10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Info: Fitter preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "10.924 ns memory register " "Info: Estimated most critical path is memory to register delay of 10.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7~porta_address_reg4 1 MEM M512_X24_Y8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X24_Y8; Fanout = 1; MEM Node = 'altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7~porta_address_reg4'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 174 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.061 ns) 2.061 ns altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7 2 MEM M512_X24_Y8 6 " "Info: 2: + IC(0.000 ns) + CELL(2.061 ns) = 2.061 ns; Loc. = M512_X24_Y8; Fanout = 6; MEM Node = 'altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.061 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7~porta_address_reg4 altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 } "NODE_NAME" } } { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 174 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.313 ns) 3.195 ns fx~23 3 COMB LAB_X27_Y5 2 " "Info: 3: + IC(0.821 ns) + CELL(0.313 ns) = 3.195 ns; Loc. = LAB_X27_Y5; Fanout = 2; COMB Node = 'fx~23'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.134 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 fx~23 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.480 ns) 4.554 ns Add2~37 4 COMB LAB_X23_Y8 6 " "Info: 4: + IC(0.879 ns) + CELL(0.480 ns) = 4.554 ns; Loc. = LAB_X23_Y8; Fanout = 6; COMB Node = 'Add2~37'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.359 ns" { fx~23 Add2~37 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.480 ns) 5.614 ns Add3~33 5 COMB LAB_X22_Y7 7 " "Info: 5: + IC(0.580 ns) + CELL(0.480 ns) = 5.614 ns; Loc. = LAB_X22_Y7; Fanout = 7; COMB Node = 'Add3~33'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.060 ns" { Add2~37 Add3~33 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.426 ns) 6.873 ns Add4~37 6 COMB LAB_X22_Y6 7 " "Info: 6: + IC(0.833 ns) + CELL(0.426 ns) = 6.873 ns; Loc. = LAB_X22_Y6; Fanout = 7; COMB Node = 'Add4~37'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.259 ns" { Add3~33 Add4~37 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.775 ns) + CELL(0.480 ns) 8.128 ns Add8~29 7 COMB LAB_X25_Y6 2 " "Info: 7: + IC(0.775 ns) + CELL(0.480 ns) = 8.128 ns; Loc. = LAB_X25_Y6; Fanout = 2; COMB Node = 'Add8~29'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.255 ns" { Add4~37 Add8~29 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.403 ns) 9.111 ns Add9~30 8 COMB LAB_X26_Y5 2 " "Info: 8: + IC(0.580 ns) + CELL(0.403 ns) = 9.111 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~30'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.983 ns" { Add8~29 Add9~30 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.102 ns) + CELL(0.041 ns) 9.254 ns Add9~34 9 COMB LAB_X26_Y5 2 " "Info: 9: + IC(0.102 ns) + CELL(0.041 ns) = 9.254 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~34'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { Add9~30 Add9~34 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.295 ns Add9~38 10 COMB LAB_X26_Y5 2 " "Info: 10: + IC(0.000 ns) + CELL(0.041 ns) = 9.295 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~38'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~34 Add9~38 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.336 ns Add9~42 11 COMB LAB_X26_Y5 2 " "Info: 11: + IC(0.000 ns) + CELL(0.041 ns) = 9.336 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~42'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~38 Add9~42 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.377 ns Add9~46 12 COMB LAB_X26_Y5 2 " "Info: 12: + IC(0.000 ns) + CELL(0.041 ns) = 9.377 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~46'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~42 Add9~46 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.418 ns Add9~50 13 COMB LAB_X26_Y5 2 " "Info: 13: + IC(0.000 ns) + CELL(0.041 ns) = 9.418 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~50'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~46 Add9~50 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.459 ns Add9~54 14 COMB LAB_X26_Y5 2 " "Info: 14: + IC(0.000 ns) + CELL(0.041 ns) = 9.459 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~54'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~50 Add9~54 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.500 ns Add9~58 15 COMB LAB_X26_Y5 1 " "Info: 15: + IC(0.000 ns) + CELL(0.041 ns) = 9.500 ns; Loc. = LAB_X26_Y5; Fanout = 1; COMB Node = 'Add9~58'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~54 Add9~58 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 9.644 ns Add9~61 16 COMB LAB_X26_Y5 2 " "Info: 16: + IC(0.000 ns) + CELL(0.144 ns) = 9.644 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~61'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add9~58 Add9~61 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.102 ns) + CELL(0.178 ns) 10.924 ns resultado\[15\] 17 REG LAB_X23_Y7 4 " "Info: 17: + IC(1.102 ns) + CELL(0.178 ns) = 10.924 ns; Loc. = LAB_X23_Y7; Fanout = 4; REG Node = 'resultado\[15\]'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.280 ns" { Add9~61 resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.252 ns ( 48.08 % ) " "Info: Total cell delay = 5.252 ns ( 48.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.672 ns ( 51.92 % ) " "Info: Total interconnect delay = 5.672 ns ( 51.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.924 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7~porta_address_reg4 altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 fx~23 Add2~37 Add3~33 Add4~37 Add8~29 Add9~30 Add9~34 Add9~38 Add9~42 Add9~46 Add9~50 Add9~54 Add9~58 Add9~61 resultado[15] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X13_Y0 X26_Y13 " "Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X13_Y0 to location X26_Y13" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "96 " "Warning: Found 96 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[0\] 0 " "Info: Pin \"fxx_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[1\] 0 " "Info: Pin \"fxx_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[2\] 0 " "Info: Pin \"fxx_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[3\] 0 " "Info: Pin \"fxx_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[4\] 0 " "Info: Pin \"fxx_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[5\] 0 " "Info: Pin \"fxx_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[6\] 0 " "Info: Pin \"fxx_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[7\] 0 " "Info: Pin \"fxx_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[8\] 0 " "Info: Pin \"fxx_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[9\] 0 " "Info: Pin \"fxx_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[10\] 0 " "Info: Pin \"fxx_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[11\] 0 " "Info: Pin \"fxx_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[12\] 0 " "Info: Pin \"fxx_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[13\] 0 " "Info: Pin \"fxx_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[14\] 0 " "Info: Pin \"fxx_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[15\] 0 " "Info: Pin \"fxx_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[0\] 0 " "Info: Pin \"fxx1_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[1\] 0 " "Info: Pin \"fxx1_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[2\] 0 " "Info: Pin \"fxx1_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[3\] 0 " "Info: Pin \"fxx1_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[4\] 0 " "Info: Pin \"fxx1_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[5\] 0 " "Info: Pin \"fxx1_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[6\] 0 " "Info: Pin \"fxx1_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[7\] 0 " "Info: Pin \"fxx1_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[8\] 0 " "Info: Pin \"fxx1_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[9\] 0 " "Info: Pin \"fxx1_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[10\] 0 " "Info: Pin \"fxx1_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[11\] 0 " "Info: Pin \"fxx1_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[12\] 0 " "Info: Pin \"fxx1_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[13\] 0 " "Info: Pin \"fxx1_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[14\] 0 " "Info: Pin \"fxx1_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[15\] 0 " "Info: Pin \"fxx1_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[0\] 0 " "Info: Pin \"fxx2_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[1\] 0 " "Info: Pin \"fxx2_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[2\] 0 " "Info: Pin \"fxx2_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[3\] 0 " "Info: Pin \"fxx2_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[4\] 0 " "Info: Pin \"fxx2_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[5\] 0 " "Info: Pin \"fxx2_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[6\] 0 " "Info: Pin \"fxx2_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[7\] 0 " "Info: Pin \"fxx2_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[8\] 0 " "Info: Pin \"fxx2_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[9\] 0 " "Info: Pin \"fxx2_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[10\] 0 " "Info: Pin \"fxx2_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[11\] 0 " "Info: Pin \"fxx2_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[12\] 0 " "Info: Pin \"fxx2_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[13\] 0 " "Info: Pin \"fxx2_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[14\] 0 " "Info: Pin \"fxx2_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[15\] 0 " "Info: Pin \"fxx2_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[0\] 0 " "Info: Pin \"fxx3_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[1\] 0 " "Info: Pin \"fxx3_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[2\] 0 " "Info: Pin \"fxx3_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[3\] 0 " "Info: Pin \"fxx3_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[4\] 0 " "Info: Pin \"fxx3_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[5\] 0 " "Info: Pin \"fxx3_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[6\] 0 " "Info: Pin \"fxx3_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[7\] 0 " "Info: Pin \"fxx3_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[8\] 0 " "Info: Pin \"fxx3_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[9\] 0 " "Info: Pin \"fxx3_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[10\] 0 " "Info: Pin \"fxx3_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[11\] 0 " "Info: Pin \"fxx3_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[12\] 0 " "Info: Pin \"fxx3_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[13\] 0 " "Info: Pin \"fxx3_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[14\] 0 " "Info: Pin \"fxx3_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[15\] 0 " "Info: Pin \"fxx3_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[0\] 0 " "Info: Pin \"fxx4_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[1\] 0 " "Info: Pin \"fxx4_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[2\] 0 " "Info: Pin \"fxx4_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[3\] 0 " "Info: Pin \"fxx4_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[4\] 0 " "Info: Pin \"fxx4_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[5\] 0 " "Info: Pin \"fxx4_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[6\] 0 " "Info: Pin \"fxx4_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[7\] 0 " "Info: Pin \"fxx4_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[8\] 0 " "Info: Pin \"fxx4_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[9\] 0 " "Info: Pin \"fxx4_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[10\] 0 " "Info: Pin \"fxx4_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[11\] 0 " "Info: Pin \"fxx4_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[12\] 0 " "Info: Pin \"fxx4_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[13\] 0 " "Info: Pin \"fxx4_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[14\] 0 " "Info: Pin \"fxx4_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[15\] 0 " "Info: Pin \"fxx4_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[0\] 0 " "Info: Pin \"resul_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[1\] 0 " "Info: Pin \"resul_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[2\] 0 " "Info: Pin \"resul_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[3\] 0 " "Info: Pin \"resul_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[4\] 0 " "Info: Pin \"resul_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[5\] 0 " "Info: Pin \"resul_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[6\] 0 " "Info: Pin \"resul_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[7\] 0 " "Info: Pin \"resul_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[8\] 0 " "Info: Pin \"resul_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[9\] 0 " "Info: Pin \"resul_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[10\] 0 " "Info: Pin \"resul_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[11\] 0 " "Info: Pin \"resul_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[12\] 0 " "Info: Pin \"resul_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[13\] 0 " "Info: Pin \"resul_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[14\] 0 " "Info: Pin \"resul_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[15\] 0 " "Info: Pin \"resul_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "233 " "Info: Peak virtual memory: 233 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 14 00:28:05 2012 " "Info: Processing ended: Tue Aug 14 00:28:05 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:27 " "Info: Elapsed time: 00:00:27" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Info: Total CPU time (on all processors): 00:00:27" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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