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[/] [gnextrapolator/] [trunk/] [QuartusII/] [gnextrapolator.fit.rpt] - Rev 5
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Fitter report for gnextrapolatorTue Aug 14 00:28:05 2012Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Fitter Summary3. Fitter Settings4. I/O Assignment Warnings5. Incremental Compilation Preservation Summary6. Incremental Compilation Partition Settings7. Incremental Compilation Placement Preservation8. Pin-Out File9. Fitter Resource Usage Summary10. Input Pins11. Output Pins12. I/O Bank Usage13. All Package Pins14. Output Pin Default Load For Reported TCO15. Fitter Resource Utilization by Entity16. Delay Chain Summary17. Pad To Core Delay Chain Fanout18. Control Signals19. Global & Other Fast Signals20. Non-Global High Fan-Out Signals21. Fitter RAM Summary22. Interconnect Usage Summary23. LAB Logic Elements24. LAB-wide Signals25. LAB Signals Sourced26. LAB Signals Sourced Out27. LAB Distinct Inputs28. I/O Rules Summary29. I/O Rules Details30. I/O Rules Matrix31. Fitter Device Options32. Operating Settings and Conditions33. Estimated Delay Added for Hold Timing34. Fitter Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2010 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+------------------------------------------------------------------------------+; Fitter Summary ;+-------------------------------+----------------------------------------------+; Fitter Status ; Successful - Tue Aug 14 00:28:04 2012 ;; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;; Revision Name ; gnextrapolator ;; Top-level Entity Name ; gnextrapolator ;; Family ; Stratix II ;; Device ; EP2S15F484C4 ;; Timing Models ; Final ;; Logic utilization ; 2 % ;; Combinational ALUTs ; 169 / 12,480 ( 1 % ) ;; Dedicated logic registers ; 190 / 12,480 ( 2 % ) ;; Total registers ; 190 ;; Total pins ; 107 / 343 ( 31 % ) ;; Total virtual pins ; 0 ;; Total block memory bits ; 512 / 419,328 ( < 1 % ) ;; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;; Total PLLs ; 0 / 6 ( 0 % ) ;; Total DLLs ; 0 / 2 ( 0 % ) ;+-------------------------------+----------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Settings ;+----------------------------------------------------------------------------+--------------------------------+--------------------------------+; Option ; Setting ; Default Value ;+----------------------------------------------------------------------------+--------------------------------+--------------------------------+; Device ; EP2S15F484C4 ; ;; Minimum Core Junction Temperature ; 0 ; ;; Maximum Core Junction Temperature ; 85 ; ;; Fit Attempts to Skip ; 0 ; 0.0 ;; Use smart compilation ; Off ; Off ;; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;; Enable compact report table ; Off ; Off ;; Use TimeQuest Timing Analyzer ; Off ; Off ;; Router Timing Optimization Level ; Normal ; Normal ;; Placement Effort Multiplier ; 1.0 ; 1.0 ;; Router Effort Multiplier ; 1.0 ; 1.0 ;; Always Enable Input Buffers ; Off ; Off ;; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;; Optimize Multi-Corner Timing ; Off ; Off ;; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;; Optimize Timing ; Normal compilation ; Normal compilation ;; Optimize Timing for ECOs ; Off ; Off ;; Regenerate full fit report during ECO compiles ; Off ; Off ;; Optimize IOC Register Placement for Timing ; On ; On ;; Limit to One Fitting Attempt ; Off ; Off ;; Final Placement Optimizations ; Automatically ; Automatically ;; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;; Fitter Initial Placement Seed ; 1 ; 1 ;; PCI I/O ; Off ; Off ;; Weak Pull-Up Resistor ; Off ; Off ;; Enable Bus-Hold Circuitry ; Off ; Off ;; Auto Global Memory Control Signals ; Off ; Off ;; Auto Packed Registers ; Auto ; Auto ;; Auto Delay Chains ; On ; On ;; Auto Merge PLLs ; On ; On ;; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;; Perform Register Duplication for Performance ; Off ; Off ;; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;; Perform Register Retiming for Performance ; Off ; Off ;; Perform Asynchronous Signal Pipelining ; Off ; Off ;; Fitter Effort ; Auto Fit ; Auto Fit ;; Physical Synthesis Effort Level ; Normal ; Normal ;; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;; Auto Register Duplication ; Auto ; Auto ;; Auto Global Clock ; On ; On ;; Auto Global Register Control Signals ; On ; On ;; Stop After Congestion Map Generation ; Off ; Off ;; Save Intermediate Fitting Results ; Off ; Off ;; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;; Use Best Effort Settings for Compilation ; Off ; Off ;+----------------------------------------------------------------------------+--------------------------------+--------------------------------++------------------------------------------------+; I/O Assignment Warnings ;+----------------+-------------------------------+; Pin Name ; Reason ;+----------------+-------------------------------+; fxx_o[0] ; Incomplete set of assignments ;; fxx_o[1] ; Incomplete set of assignments ;; fxx_o[2] ; Incomplete set of assignments ;; fxx_o[3] ; Incomplete set of assignments ;; fxx_o[4] ; Incomplete set of assignments ;; fxx_o[5] ; Incomplete set of assignments ;; fxx_o[6] ; Incomplete set of assignments ;; fxx_o[7] ; Incomplete set of assignments ;; fxx_o[8] ; Incomplete set of assignments ;; fxx_o[9] ; Incomplete set of assignments ;; fxx_o[10] ; Incomplete set of assignments ;; fxx_o[11] ; Incomplete set of assignments ;; fxx_o[12] ; Incomplete set of assignments ;; fxx_o[13] ; Incomplete set of assignments ;; fxx_o[14] ; Incomplete set of assignments ;; fxx_o[15] ; Incomplete set of assignments ;; fxx1_o[0] ; Incomplete set of assignments ;; fxx1_o[1] ; Incomplete set of assignments ;; fxx1_o[2] ; Incomplete set of assignments ;; fxx1_o[3] ; Incomplete set of assignments ;; fxx1_o[4] ; Incomplete set of assignments ;; fxx1_o[5] ; Incomplete set of assignments ;; fxx1_o[6] ; Incomplete set of assignments ;; fxx1_o[7] ; Incomplete set of assignments ;; fxx1_o[8] ; Incomplete set of assignments ;; fxx1_o[9] ; Incomplete set of assignments ;; fxx1_o[10] ; Incomplete set of assignments ;; fxx1_o[11] ; Incomplete set of assignments ;; fxx1_o[12] ; Incomplete set of assignments ;; fxx1_o[13] ; Incomplete set of assignments ;; fxx1_o[14] ; Incomplete set of assignments ;; fxx1_o[15] ; Incomplete set of assignments ;; fxx2_o[0] ; Incomplete set of assignments ;; fxx2_o[1] ; Incomplete set of assignments ;; fxx2_o[2] ; Incomplete set of assignments ;; fxx2_o[3] ; Incomplete set of assignments ;; fxx2_o[4] ; Incomplete set of assignments ;; fxx2_o[5] ; Incomplete set of assignments ;; fxx2_o[6] ; Incomplete set of assignments ;; fxx2_o[7] ; Incomplete set of assignments ;; fxx2_o[8] ; Incomplete set of assignments ;; fxx2_o[9] ; Incomplete set of assignments ;; fxx2_o[10] ; Incomplete set of assignments ;; fxx2_o[11] ; Incomplete set of assignments ;; fxx2_o[12] ; Incomplete set of assignments ;; fxx2_o[13] ; Incomplete set of assignments ;; fxx2_o[14] ; Incomplete set of assignments ;; fxx2_o[15] ; Incomplete set of assignments ;; fxx3_o[0] ; Incomplete set of assignments ;; fxx3_o[1] ; Incomplete set of assignments ;; fxx3_o[2] ; Incomplete set of assignments ;; fxx3_o[3] ; Incomplete set of assignments ;; fxx3_o[4] ; Incomplete set of assignments ;; fxx3_o[5] ; Incomplete set of assignments ;; fxx3_o[6] ; Incomplete set of assignments ;; fxx3_o[7] ; Incomplete set of assignments ;; fxx3_o[8] ; Incomplete set of assignments ;; fxx3_o[9] ; Incomplete set of assignments ;; fxx3_o[10] ; Incomplete set of assignments ;; fxx3_o[11] ; Incomplete set of assignments ;; fxx3_o[12] ; Incomplete set of assignments ;; fxx3_o[13] ; Incomplete set of assignments ;; fxx3_o[14] ; Incomplete set of assignments ;; fxx3_o[15] ; Incomplete set of assignments ;; fxx4_o[0] ; Incomplete set of assignments ;; fxx4_o[1] ; Incomplete set of assignments ;; fxx4_o[2] ; Incomplete set of assignments ;; fxx4_o[3] ; Incomplete set of assignments ;; fxx4_o[4] ; Incomplete set of assignments ;; fxx4_o[5] ; Incomplete set of assignments ;; fxx4_o[6] ; Incomplete set of assignments ;; fxx4_o[7] ; Incomplete set of assignments ;; fxx4_o[8] ; Incomplete set of assignments ;; fxx4_o[9] ; Incomplete set of assignments ;; fxx4_o[10] ; Incomplete set of assignments ;; fxx4_o[11] ; Incomplete set of assignments ;; fxx4_o[12] ; Incomplete set of assignments ;; fxx4_o[13] ; Incomplete set of assignments ;; fxx4_o[14] ; Incomplete set of assignments ;; fxx4_o[15] ; Incomplete set of assignments ;; resul_o[0] ; Incomplete set of assignments ;; resul_o[1] ; Incomplete set of assignments ;; resul_o[2] ; Incomplete set of assignments ;; resul_o[3] ; Incomplete set of assignments ;; resul_o[4] ; Incomplete set of assignments ;; resul_o[5] ; Incomplete set of assignments ;; resul_o[6] ; Incomplete set of assignments ;; resul_o[7] ; Incomplete set of assignments ;; resul_o[8] ; Incomplete set of assignments ;; resul_o[9] ; Incomplete set of assignments ;; resul_o[10] ; Incomplete set of assignments ;; resul_o[11] ; Incomplete set of assignments ;; resul_o[12] ; Incomplete set of assignments ;; resul_o[13] ; Incomplete set of assignments ;; resul_o[14] ; Incomplete set of assignments ;; resul_o[15] ; Incomplete set of assignments ;; extrapolar_i ; Incomplete set of assignments ;; clk_i ; Incomplete set of assignments ;; rst_i ; Incomplete set of assignments ;; distancia_i[5] ; Incomplete set of assignments ;; distancia_i[3] ; Incomplete set of assignments ;; distancia_i[4] ; Incomplete set of assignments ;; distancia_i[2] ; Incomplete set of assignments ;; distancia_i[0] ; Incomplete set of assignments ;; distancia_i[1] ; Incomplete set of assignments ;; distancia_i[6] ; Incomplete set of assignments ;; distancia_i[7] ; Incomplete set of assignments ;+----------------+-------------------------------++----------------------------------------------+; Incremental Compilation Preservation Summary ;+-------------------------+--------------------+; Type ; Value ;+-------------------------+--------------------+; Placement ; ;; -- Requested ; 0 / 485 ( 0.00 % ) ;; -- Achieved ; 0 / 485 ( 0.00 % ) ;; ; ;; Routing (by Connection) ; ;; -- Requested ; 0 / 0 ( 0.00 % ) ;; -- Achieved ; 0 / 0 ( 0.00 % ) ;+-------------------------+--------------------++--------------------------------------------------------------------------------------------------------------------------------------------------+; Incremental Compilation Partition Settings ;+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------++--------------------------------------------------------------------------------------------+; Incremental Compilation Placement Preservation ;+----------------+---------+-------------------+-------------------------+-------------------+; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;+----------------+---------+-------------------+-------------------------+-------------------+; Top ; 485 ; 0 ; N/A ; Source File ;+----------------+---------+-------------------+-------------------------+-------------------++--------------+; Pin-Out File ;+--------------+The pin-out file can be found in C:/Altera/qdesigns/gnextrapolator/gnextrapolator.pin.+-------------------------------------------------------------------------------------------------------------+; Fitter Resource Usage Summary ;+-----------------------------------------------------------------------------------+-------------------------+; Resource ; Usage ;+-----------------------------------------------------------------------------------+-------------------------+; Combinational ALUTs ; 169 / 12,480 ( 1 % ) ;; Dedicated logic registers ; 190 / 12,480 ( 2 % ) ;; ; ;; Combinational ALUT usage by number of inputs ; ;; -- 7 input functions ; 0 ;; -- 6 input functions ; 4 ;; -- 5 input functions ; 16 ;; -- 4 input functions ; 32 ;; -- <=3 input functions ; 117 ;; ; ;; Combinational ALUTs by mode ; ;; -- normal mode ; 39 ;; -- extended LUT mode ; 0 ;; -- arithmetic mode ; 114 ;; -- shared arithmetic mode ; 16 ;; ; ;; Logic utilization ; 232 / 12,480 ( 2 % ) ;; -- Difficulty Clustering Design ; Low ;; -- Combinational ALUT/register pairs used in final Placement ; 233 ;; -- Combinational with no register ; 43 ;; -- Register only ; 64 ;; -- Combinational with a register ; 126 ;; -- Estimated pairs recoverable by pairing ALUTs and registers as design grows ; -1 ;; -- Estimated Combinational ALUT/register pairs unavailable ; 0 ;; -- Unavailable due to unpartnered 7 LUTs ; 0 ;; -- Unavailable due to unpartnered 6 LUTs ; 0 ;; -- Unavailable due to unpartnered 5 LUTs ; 0 ;; -- Unavailable due to LAB-wide signal conflicts ; 0 ;; -- Unavailable due to LAB input limits ; 0 ;; ; ;; Total registers* ; 190 / 14,410 ( 1 % ) ;; -- Dedicated logic registers ; 190 / 12,480 ( 2 % ) ;; -- I/O registers ; 0 / 1,930 ( 0 % ) ;; ; ;; ALMs: partially or completely used ; 117 / 6,240 ( 2 % ) ;; ; ;; Total LABs: partially or completely used ; 16 / 780 ( 2 % ) ;; ; ;; User inserted logic elements ; 0 ;; Virtual pins ; 0 ;; I/O pins ; 107 / 343 ( 31 % ) ;; -- Clock pins ; 15 / 16 ( 94 % ) ;; Global signals ; 2 ;; M512s ; 1 / 104 ( < 1 % ) ;; M4Ks ; 0 / 78 ( 0 % ) ;; Total block memory bits ; 512 / 419,328 ( < 1 % ) ;; Total block memory implementation bits ; 576 / 419,328 ( < 1 % ) ;; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;; PLLs ; 0 / 6 ( 0 % ) ;; Global clocks ; 2 / 16 ( 13 % ) ;; Regional clocks ; 0 / 32 ( 0 % ) ;; SERDES transmitters ; 0 / 38 ( 0 % ) ;; SERDES receivers ; 0 / 42 ( 0 % ) ;; JTAGs ; 0 / 1 ( 0 % ) ;; ASMI blocks ; 0 / 1 ( 0 % ) ;; CRC blocks ; 0 / 1 ( 0 % ) ;; Remote update blocks ; 0 / 1 ( 0 % ) ;; Average interconnect usage (total/H/V) ; 1% / 0% / 1% ;; Peak interconnect usage (total/H/V) ; 3% / 2% / 3% ;; Maximum fan-out node ; clk_i~clkctrl ;; Maximum fan-out ; 191 ;; Highest non-global fan-out signal ; rst_i ;; Highest non-global fan-out ; 97 ;; Total fan-out ; 1304 ;; Average fan-out ; 2.63 ;+-----------------------------------------------------------------------------------+-------------------------+* Register count does not include registers inside block RAM or DSP blocks.+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Input Pins ;+----------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;+----------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+; clk_i ; N20 ; 1 ; 0 ; 10 ; 1 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; distancia_i[0] ; R9 ; 7 ; 34 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; distancia_i[1] ; P8 ; 6 ; 40 ; 7 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; distancia_i[2] ; N3 ; 6 ; 40 ; 10 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; distancia_i[3] ; AA8 ; 7 ; 26 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; distancia_i[4] ; E7 ; 4 ; 37 ; 27 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; distancia_i[5] ; B8 ; 4 ; 26 ; 27 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; distancia_i[6] ; M2 ; 5 ; 40 ; 16 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; distancia_i[7] ; K8 ; 5 ; 40 ; 18 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; extrapolar_i ; B9 ; 9 ; 26 ; 27 ; 2 ; 65 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; rst_i ; M21 ; 2 ; 0 ; 16 ; 2 ; 98 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;+----------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Output Pins ;+-------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;+-------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+; fxx1_o[0] ; L2 ; 5 ; 40 ; 16 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx1_o[10] ; Y10 ; 7 ; 22 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx1_o[11] ; K4 ; 5 ; 40 ; 18 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx1_o[12] ; K3 ; 5 ; 40 ; 18 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx1_o[13] ; T9 ; 7 ; 34 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx1_o[14] ; P6 ; 6 ; 40 ; 8 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx1_o[15] ; K5 ; 5 ; 40 ; 19 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx1_o[1] ; A7 ; 4 ; 29 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx1_o[2] ; L20 ; 2 ; 0 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx1_o[3] ; P5 ; 6 ; 40 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx1_o[4] ; C11 ; 4 ; 22 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx1_o[5] ; V2 ; 6 ; 40 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx1_o[6] ; P18 ; 1 ; 0 ; 8 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx1_o[7] ; R1 ; 6 ; 40 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx1_o[8] ; J3 ; 5 ; 40 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx1_o[9] ; W9 ; 10 ; 26 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[0] ; AB18 ; 8 ; 11 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[10] ; T6 ; 6 ; 40 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[11] ; V12 ; 8 ; 17 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[12] ; AB10 ; 10 ; 25 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[13] ; AA10 ; 10 ; 25 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[14] ; C9 ; 9 ; 26 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[15] ; C10 ; 9 ; 25 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[1] ; L3 ; 5 ; 40 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[2] ; N8 ; 6 ; 40 ; 9 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[3] ; W1 ; 6 ; 40 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[4] ; N7 ; 6 ; 40 ; 9 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[5] ; N2 ; 6 ; 40 ; 10 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[6] ; C13 ; 3 ; 18 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[7] ; L7 ; 5 ; 40 ; 17 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[8] ; P16 ; 1 ; 0 ; 7 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx2_o[9] ; B12 ; 4 ; 22 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[0] ; B13 ; 3 ; 18 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[10] ; AA9 ; 10 ; 25 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[11] ; R4 ; 6 ; 40 ; 6 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[12] ; C7 ; 4 ; 29 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[13] ; Y11 ; 7 ; 22 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[14] ; J5 ; 5 ; 40 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[15] ; J6 ; 5 ; 40 ; 20 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[1] ; U20 ; 1 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[2] ; A10 ; 9 ; 25 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[3] ; H1 ; 5 ; 40 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[4] ; Y12 ; 8 ; 18 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[5] ; D12 ; 3 ; 17 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[6] ; AA11 ; 7 ; 22 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[7] ; A13 ; 3 ; 18 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[8] ; R7 ; 6 ; 40 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx3_o[9] ; T3 ; 6 ; 40 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[0] ; R6 ; 6 ; 40 ; 6 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[10] ; T18 ; 1 ; 0 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[11] ; R8 ; 6 ; 40 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[12] ; T4 ; 6 ; 40 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[13] ; U22 ; 1 ; 0 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[14] ; U1 ; 6 ; 40 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[15] ; R19 ; 1 ; 0 ; 6 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[1] ; P2 ; 6 ; 40 ; 9 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[2] ; V9 ; 10 ; 26 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[3] ; Y9 ; 10 ; 25 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[4] ; V8 ; 7 ; 33 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[5] ; W10 ; 7 ; 22 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[6] ; AB13 ; 8 ; 18 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[7] ; U2 ; 6 ; 40 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[8] ; U5 ; 6 ; 40 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx4_o[9] ; T5 ; 6 ; 40 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[0] ; K7 ; 5 ; 40 ; 18 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[10] ; B10 ; 9 ; 25 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[11] ; B7 ; 4 ; 29 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[12] ; T21 ; 1 ; 0 ; 7 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[13] ; T2 ; 6 ; 40 ; 7 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[14] ; P3 ; 6 ; 40 ; 9 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[15] ; T10 ; 7 ; 30 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[1] ; P17 ; 1 ; 0 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[2] ; C12 ; 4 ; 22 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[3] ; D6 ; 4 ; 35 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[4] ; L8 ; 5 ; 40 ; 17 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[5] ; D10 ; 9 ; 25 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[6] ; H11 ; 3 ; 17 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[7] ; P7 ; 6 ; 40 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[8] ; A8 ; 4 ; 26 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; fxx_o[9] ; T1 ; 6 ; 40 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[0] ; AB8 ; 7 ; 26 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[10] ; R5 ; 6 ; 40 ; 6 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[11] ; B15 ; 3 ; 14 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[12] ; AB6 ; 7 ; 30 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[13] ; T20 ; 1 ; 0 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[14] ; T16 ; 8 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[15] ; U4 ; 6 ; 40 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[1] ; AA7 ; 7 ; 29 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[2] ; Y7 ; 7 ; 29 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[3] ; AB5 ; 7 ; 31 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[4] ; T19 ; 1 ; 0 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[5] ; R2 ; 6 ; 40 ; 8 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[6] ; U21 ; 1 ; 0 ; 6 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[7] ; T22 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[8] ; T17 ; 1 ; 0 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;; resul_o[9] ; Y8 ; 7 ; 29 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;+-------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------++------------------------------------------------------------+; I/O Bank Usage ;+----------+------------------+---------------+--------------+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;+----------+------------------+---------------+--------------+; 1 ; 14 / 40 ( 35 % ) ; 3.3V ; -- ;; 2 ; 2 / 44 ( 5 % ) ; 3.3V ; -- ;; 3 ; 7 / 50 ( 14 % ) ; 3.3V ; -- ;; 4 ; 10 / 35 ( 29 % ) ; 3.3V ; -- ;; 5 ; 14 / 44 ( 32 % ) ; 3.3V ; -- ;; 6 ; 29 / 40 ( 73 % ) ; 3.3V ; -- ;; 7 ; 15 / 34 ( 44 % ) ; 3.3V ; -- ;; 8 ; 5 / 43 ( 12 % ) ; 3.3V ; -- ;; 9 ; 6 / 6 ( 100 % ) ; 3.3V ; -- ;; 10 ; 6 / 6 ( 100 % ) ; 3.3V ; -- ;+----------+------------------+---------------+--------------++--------------------------------------------------------------------------------------------------------------------------------------------------------+; All Package Pins ;+----------+------------+----------+--------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;+----------+------------+----------+--------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; A2 ; ; ; TEMPDIODEp ; ; ; ; -- ; ; -- ; -- ;; A3 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; A4 ; 277 ; 4 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;; A5 ; 307 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; A6 ; 311 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; A7 ; 315 ; 4 ; fxx1_o[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; A8 ; 318 ; 4 ; fxx_o[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; A9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; A10 ; 323 ; 9 ; fxx3_o[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; A11 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; A12 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; A13 ; 329 ; 3 ; fxx3_o[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; A14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; A15 ; 343 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; A16 ; 347 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; A17 ; 351 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; A18 ; 350 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; A19 ; 375 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; A20 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; A21 ; 383 ; 3 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA1 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA3 ; 191 ; 7 ; ^nCEO ; ; ; ; -- ; ; -- ; -- ;; AA4 ; 181 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AA5 ; 163 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AA6 ; 159 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AA7 ; 155 ; 7 ; resul_o[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AA8 ; 151 ; 7 ; distancia_i[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AA9 ; 144 ; 10 ; fxx3_o[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AA10 ; 147 ; 10 ; fxx2_o[13] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AA11 ; 141 ; 7 ; fxx3_o[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AA12 ; 138 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AA13 ; 137 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AA14 ; ; 8 ; VREFB8 ; power ; ; ; -- ; ; -- ; -- ;; AA15 ; 127 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AA16 ; 123 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AA17 ; 119 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AA18 ; 115 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AA19 ; 85 ; 8 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;; AA20 ; 86 ; 8 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA22 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB2 ; 190 ; 7 ; ^nIO_PULLUP ; ; ; ; -- ; ; -- ; -- ;; AB3 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB5 ; 161 ; 7 ; resul_o[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AB6 ; 157 ; 7 ; resul_o[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AB7 ; 153 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AB8 ; 150 ; 7 ; resul_o[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AB9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB10 ; 145 ; 10 ; fxx2_o[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AB11 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB12 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB13 ; 139 ; 8 ; fxx4_o[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AB14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB15 ; 125 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AB16 ; 124 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AB17 ; 117 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AB18 ; 118 ; 8 ; fxx2_o[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AB19 ; 87 ; 8 ; #TRST ; input ; ; ; -- ; ; -- ; -- ;; AB20 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB21 ; 84 ; 8 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B1 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B3 ; 276 ; 4 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;; B4 ; 279 ; 4 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;; B5 ; 305 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; B6 ; 309 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; B7 ; 313 ; 4 ; fxx_o[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; B8 ; 317 ; 4 ; distancia_i[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; B9 ; 320 ; 9 ; extrapolar_i ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; B10 ; 321 ; 9 ; fxx_o[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; B11 ; 327 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; B12 ; 328 ; 4 ; fxx2_o[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; B13 ; 331 ; 3 ; fxx3_o[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; B14 ; ; 3 ; VREFB3 ; power ; ; ; -- ; ; -- ; -- ;; B15 ; 341 ; 3 ; resul_o[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; B16 ; 345 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; B17 ; 349 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; B18 ; 353 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; B19 ; 377 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; B20 ; 381 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B22 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; C1 ; 275 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; C2 ; 273 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; C3 ; ; ; TEMPDIODEn ; ; ; ; -- ; ; -- ; -- ;; C4 ; 285 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C5 ; 306 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C6 ; 308 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C7 ; 316 ; 4 ; fxx3_o[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C8 ; 314 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C9 ; 319 ; 9 ; fxx2_o[14] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C10 ; 324 ; 9 ; fxx2_o[15] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C11 ; 325 ; 4 ; fxx1_o[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C12 ; 326 ; 4 ; fxx_o[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C13 ; 330 ; 3 ; fxx2_o[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C14 ; 354 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C15 ; 342 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C16 ; 344 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C17 ; 352 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C18 ; 355 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C19 ; 369 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C20 ; 384 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;; C21 ; 2 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; C22 ; 0 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; D1 ; 271 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; D2 ; 269 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; D3 ; 287 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D4 ; 278 ; 4 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;; D5 ; 283 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D6 ; 293 ; 4 ; fxx_o[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; D7 ; ; 4 ; VREFB4 ; power ; ; ; -- ; ; -- ; -- ;; D8 ; 297 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D9 ; ; 4 ; VREFB4 ; power ; ; ; -- ; ; -- ; -- ;; D10 ; 322 ; 9 ; fxx_o[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; D11 ; 337 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D12 ; 333 ; 3 ; fxx3_o[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; D13 ; 332 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D14 ; 356 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D15 ; 361 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D16 ; ; 3 ; VREFB3 ; power ; ; ; -- ; ; -- ; -- ;; D17 ; 373 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D18 ; 379 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D19 ; 382 ; 3 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;; D20 ; 371 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D21 ; 6 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; D22 ; 4 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E1 ; 267 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E2 ; 265 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E3 ; 274 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E4 ; 272 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E5 ; 280 ; 4 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;; E6 ; 281 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E7 ; 289 ; 4 ; distancia_i[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; E8 ; 298 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E9 ; 301 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E10 ; 312 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E11 ; 335 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E12 ; 339 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E13 ; 338 ; 3 ; ~DATA0~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; E14 ; 357 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E15 ; 365 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E16 ; 374 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E17 ; 376 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E18 ; 380 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E19 ; 3 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E20 ; 1 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E21 ; 10 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E22 ; 8 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; F1 ; 263 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; F2 ; 261 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; F3 ; ; 5 ; VREFB5 ; power ; ; ; -- ; ; -- ; -- ;; F4 ; 270 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; F5 ; 268 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; F6 ; 288 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F7 ; 296 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F8 ; 294 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F9 ; 300 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F10 ; ; ; GNDA_PLL5 ; gnd ; ; ; -- ; ; -- ; -- ;; F11 ; ; ; GNDA_PLL5 ; gnd ; ; ; -- ; ; -- ; -- ;; F12 ; ; ; VCCA_PLL5 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; F13 ; 346 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F14 ; 358 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F15 ; 367 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F16 ; 362 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F17 ; 378 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F18 ; ; 2 ; VREFB2 ; power ; ; ; -- ; ; -- ; -- ;; F19 ; 11 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; F20 ; 9 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; F21 ; 14 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; F22 ; 12 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G1 ; 255 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G2 ; 253 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G3 ; 262 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G4 ; 260 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G5 ; 266 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G6 ; 264 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G7 ; 286 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G8 ; 291 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G9 ; 302 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G10 ; ; 9 ; VCC_PLL5_OUT ; power ; ; 3.3V ; -- ; ; -- ; -- ;; G11 ; ; ; VCCD_PLL5 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; G12 ; 336 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G13 ; 348 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G14 ; 359 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G15 ; 366 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G16 ; 370 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G17 ; 7 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G18 ; 5 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G19 ; 19 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G20 ; 17 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G21 ; 22 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G22 ; 20 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H1 ; 251 ; 5 ; fxx3_o[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; H2 ; 249 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H3 ; 259 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H4 ; 257 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H5 ; 254 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H6 ; 252 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H7 ; 284 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; H8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; H9 ; 304 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; H10 ; ; 4 ; VCCPD4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; H11 ; 334 ; 3 ; fxx_o[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; H12 ; 340 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; H13 ; ; 3 ; VCCPD3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; H14 ; 360 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; H16 ; 368 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; H17 ; 15 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H18 ; 13 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H19 ; 18 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H20 ; 16 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H21 ; 26 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H22 ; 24 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; J2 ; 247 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J3 ; 245 ; 5 ; fxx1_o[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; J4 ; ; 5 ; VREFB5 ; power ; ; ; -- ; ; -- ; -- ;; J5 ; 250 ; 5 ; fxx3_o[14] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; J6 ; 248 ; 5 ; fxx3_o[15] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; J7 ; 258 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J8 ; 256 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; J10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; J12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; J14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; J15 ; 364 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; J16 ; 23 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J17 ; 21 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J18 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J19 ; 25 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J20 ; 30 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J21 ; 28 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K1 ; 239 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; K2 ; 237 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; K3 ; 243 ; 5 ; fxx1_o[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; K4 ; 241 ; 5 ; fxx1_o[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; K5 ; 246 ; 5 ; fxx1_o[15] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; K6 ; 244 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; K7 ; 242 ; 5 ; fxx_o[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; K8 ; 240 ; 5 ; distancia_i[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; K9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K14 ; ; 2 ; VCCPD2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; K15 ; 35 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; K16 ; 33 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; K17 ; 31 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; K18 ; 29 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; K19 ; 34 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; K20 ; 32 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; K21 ; 38 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; K22 ; 36 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; L1 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; L2 ; 233 ; 5 ; fxx1_o[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; L3 ; 235 ; 5 ; fxx2_o[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; L4 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;; L5 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;; L6 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; L7 ; 238 ; 5 ; fxx2_o[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; L8 ; 236 ; 5 ; fxx_o[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; L9 ; ; 5 ; VCCPD5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; L14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L15 ; 39 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; L16 ; 37 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; L17 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; L18 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; L19 ; ; 2 ; VREFB2 ; power ; ; ; -- ; ; -- ; -- ;; L20 ; 40 ; 2 ; fxx1_o[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; L21 ; 42 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; L22 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; M1 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; M2 ; 232 ; 5 ; distancia_i[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; M3 ; 234 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; M4 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M6 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M16 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M17 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M18 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M19 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M20 ; 41 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; M21 ; 43 ; 2 ; rst_i ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; M22 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; N1 ; 231 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; N2 ; 229 ; 6 ; fxx2_o[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N3 ; 230 ; 6 ; distancia_i[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N4 ; 228 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; N5 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;; N6 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;; N7 ; 226 ; 6 ; fxx2_o[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N8 ; 224 ; 6 ; fxx2_o[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N9 ; ; 6 ; VCCPD6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; N14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N15 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; N16 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; N17 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; N18 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; N19 ; 47 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; N20 ; 45 ; 1 ; clk_i ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N21 ; 46 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; N22 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P2 ; 227 ; 6 ; fxx4_o[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P3 ; 225 ; 6 ; fxx_o[14] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P4 ; ; 6 ; VREFB6 ; power ; ; ; -- ; ; -- ; -- ;; P5 ; 222 ; 6 ; fxx1_o[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P6 ; 220 ; 6 ; fxx1_o[14] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P7 ; 218 ; 6 ; fxx_o[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P8 ; 216 ; 6 ; distancia_i[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; P10 ; ; 7 ; VCCPD7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; P11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; P13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; P15 ; ; 1 ; VCCPD1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; P16 ; 59 ; 1 ; fxx2_o[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P17 ; 57 ; 1 ; fxx_o[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P18 ; 55 ; 1 ; fxx1_o[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P19 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; P20 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; P21 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; P22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; R1 ; 223 ; 6 ; fxx1_o[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; R2 ; 221 ; 6 ; resul_o[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; R3 ; 215 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; R4 ; 213 ; 6 ; fxx3_o[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; R5 ; 214 ; 6 ; resul_o[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; R6 ; 212 ; 6 ; fxx4_o[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; R7 ; 202 ; 6 ; fxx3_o[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; R8 ; 200 ; 6 ; fxx4_o[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; R9 ; 168 ; 7 ; distancia_i[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; R10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; R11 ; ; 10 ; VCC_PLL6_OUT ; power ; ; 3.3V ; -- ; ; -- ; -- ;; R12 ; ; ; VCCA_PLL6 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; R13 ; ; 8 ; VCCPD8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; R14 ; 106 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; R15 ; 89 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; R16 ; 83 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; R17 ; 81 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; R18 ; 63 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; R19 ; 61 ; 1 ; fxx4_o[15] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; R20 ; ; 1 ; VREFB1 ; power ; ; ; -- ; ; -- ; -- ;; R21 ; 54 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; R22 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; T1 ; 219 ; 6 ; fxx_o[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; T2 ; 217 ; 6 ; fxx_o[13] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; T3 ; 207 ; 6 ; fxx3_o[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; T4 ; 205 ; 6 ; fxx4_o[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; T5 ; 210 ; 6 ; fxx4_o[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; T6 ; 208 ; 6 ; fxx2_o[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; T7 ; 186 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; T8 ; 172 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; T9 ; 170 ; 7 ; fxx1_o[13] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; T10 ; 156 ; 7 ; fxx_o[15] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; T11 ; ; ; GNDA_PLL6 ; gnd ; ; ; -- ; ; -- ; -- ;; T12 ; ; ; GNDA_PLL6 ; gnd ; ; ; -- ; ; -- ; -- ;; T13 ; 120 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; T14 ; 108 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; T15 ; 98 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; T16 ; 92 ; 8 ; resul_o[14] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; T17 ; 67 ; 1 ; resul_o[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; T18 ; 65 ; 1 ; fxx4_o[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; T19 ; 66 ; 1 ; resul_o[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; T20 ; 64 ; 1 ; resul_o[13] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; T21 ; 58 ; 1 ; fxx_o[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; T22 ; 56 ; 1 ; resul_o[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; U1 ; 211 ; 6 ; fxx4_o[14] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; U2 ; 209 ; 6 ; fxx4_o[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; U3 ; ; 6 ; VREFB6 ; power ; ; ; -- ; ; -- ; -- ;; U4 ; 206 ; 6 ; resul_o[15] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; U5 ; 204 ; 6 ; fxx4_o[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; U6 ; 179 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U7 ; 180 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U8 ; 173 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U9 ; 171 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U10 ; 158 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U11 ; ; ; VCCD_PLL6 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; U12 ; 130 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U13 ; 112 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U14 ; 103 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U15 ; 99 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U16 ; 94 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U17 ; 71 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; U18 ; 69 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; U19 ; 70 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; U20 ; 68 ; 1 ; fxx3_o[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; U21 ; 62 ; 1 ; resul_o[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; U22 ; 60 ; 1 ; fxx4_o[13] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; V1 ; 203 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; V2 ; 201 ; 6 ; fxx1_o[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; V3 ; 198 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; V4 ; 196 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; V5 ; 188 ; 7 ; ^PORSEL ; ; ; ; -- ; ; -- ; -- ;; V6 ; 185 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; V7 ; 175 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; V8 ; 166 ; 7 ; fxx4_o[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; V9 ; 149 ; 10 ; fxx4_o[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; V10 ; 165 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; V11 ; 132 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; V12 ; 134 ; 8 ; fxx2_o[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; V13 ; 114 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; V14 ; 105 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; V15 ; 97 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; V16 ; 93 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; V17 ; 90 ; 8 ; ^VCCSEL ; ; ; ; -- ; ; -- ; -- ;; V18 ; 75 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; V19 ; 73 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; V20 ; ; 1 ; VREFB1 ; power ; ; ; -- ; ; -- ; -- ;; V21 ; 74 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; V22 ; 72 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; W1 ; 199 ; 6 ; fxx2_o[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; W2 ; 197 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; W3 ; 194 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; W4 ; 192 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; W5 ; 182 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; W6 ; ; 7 ; VREFB7 ; power ; ; ; -- ; ; -- ; -- ;; W7 ; 177 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; W8 ; ; 7 ; VREFB7 ; power ; ; ; -- ; ; -- ; -- ;; W9 ; 148 ; 10 ; fxx1_o[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; W10 ; 142 ; 7 ; fxx4_o[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; W11 ; 133 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; W12 ; 135 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; W13 ; 128 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; W14 ; 109 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; W15 ; 102 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; W16 ; 101 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; W17 ; 95 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; W18 ; 88 ; 8 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;; W19 ; 79 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; W20 ; 77 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; W21 ; 78 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; W22 ; 76 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; Y1 ; 195 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; Y2 ; 193 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; Y3 ; 184 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y4 ; 189 ; 7 ; PLL_ENA ; ; ; ; -- ; ; -- ; -- ;; Y5 ; 162 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y6 ; 160 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y7 ; 154 ; 7 ; resul_o[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y8 ; 152 ; 7 ; resul_o[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y9 ; 146 ; 10 ; fxx4_o[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y10 ; 140 ; 7 ; fxx1_o[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y11 ; 143 ; 7 ; fxx3_o[13] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y12 ; 136 ; 8 ; fxx3_o[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y13 ; 131 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y14 ; 110 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y15 ; 126 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y16 ; 121 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y17 ; 116 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y18 ; 113 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y19 ; ; 8 ; VREFB8 ; power ; ; ; -- ; ; -- ; -- ;; Y20 ; 91 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y21 ; 82 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; Y22 ; 80 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;+----------+------------+----------+--------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+Note: Pin directions (input, output or bidir) are based on device operating in user mode.+-------------------------------------------------------------------------------+; Output Pin Default Load For Reported TCO ;+----------------------------------+-------+------------------------------------+; I/O Standard ; Load ; Termination Resistance ;+----------------------------------+-------+------------------------------------+; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;; LVDS ; 0 pF ; 100 Ohm (Differential) ;; HyperTransport ; 0 pF ; 100 Ohm (Differential) ;; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;; 3.3-V LVTTL ; 0 pF ; Not Available ;; 3.3-V LVCMOS ; 0 pF ; Not Available ;; 2.5 V ; 0 pF ; Not Available ;; 1.8 V ; 0 pF ; Not Available ;; 1.5 V ; 0 pF ; Not Available ;; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;; 1.2-V HSTL ; 0 pF ; Not Available ;; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;; Differential 1.2-V HSTL ; 0 pF ; Not Available ;+----------------------------------+-------+------------------------------------+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Resource Utilization by Entity ;+----------------------------------------+---------------------+-----------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+---------------------------------------------------------------------+--------------+; Compilation Hierarchy Node ; Combinational ALUTs ; ALMs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Combinational with no register ; Register-Only ; Combinational with a register ; Full Hierarchy Name ; Library Name ;; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ALUT/register pair ; ALUT/register pair ; ALUT/register pair ; ; ;+----------------------------------------+---------------------+-----------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+---------------------------------------------------------------------+--------------+; |gnextrapolator ; 169 (169) ; 117 (117) ; 190 (190) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 107 ; 0 ; 43 (43) ; 64 (64) ; 126 (126) ; |gnextrapolator ; work ;; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |gnextrapolator|altsyncram:ram_rtl_0 ; ;; |altsyncram_uv61:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |gnextrapolator|altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated ; ;+----------------------------------------+---------------------+-----------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+---------------------------------------------------------------------+--------------+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.+---------------------------------------------------------------------------------------------------------------------------------------+; Delay Chain Summary ;+----------------+----------+---------------+---------------+-----------------------+-----+-----------+---------+----------+------------+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; DQS bus ; NDQS bus ; DQS output ;+----------------+----------+---------------+---------------+-----------------------+-----+-----------+---------+----------+------------+; fxx_o[0] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx_o[1] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx_o[2] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx_o[3] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx_o[4] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx_o[5] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx_o[6] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx_o[7] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx_o[8] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx_o[9] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx_o[10] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx_o[11] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx_o[12] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx_o[13] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx_o[14] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx_o[15] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[0] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[1] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[2] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[3] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[4] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[5] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[6] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[7] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[8] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[9] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[10] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[11] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[12] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[13] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[14] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx1_o[15] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[0] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[1] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[2] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[3] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[4] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[5] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[6] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[7] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[8] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[9] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[10] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[11] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[12] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[13] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[14] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx2_o[15] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[0] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[1] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[2] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[3] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[4] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[5] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[6] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[7] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[8] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[9] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[10] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[11] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[12] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[13] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[14] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx3_o[15] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[0] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[1] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[2] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[3] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[4] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[5] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[6] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[7] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[8] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[9] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[10] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[11] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[12] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[13] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[14] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; fxx4_o[15] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[0] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[1] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[2] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[3] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[4] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[5] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[6] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[7] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[8] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[9] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[10] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[11] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[12] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[13] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[14] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; resul_o[15] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ;; extrapolar_i ; Input ; (7) 3445 ps ; (7) 3445 ps ; -- ; -- ; -- ; -- ; -- ; -- ;; clk_i ; Input ; (0) 236 ps ; (0) 236 ps ; -- ; -- ; -- ; -- ; -- ; -- ;; rst_i ; Input ; (7) 3544 ps ; (7) 3544 ps ; -- ; -- ; -- ; -- ; -- ; -- ;; distancia_i[5] ; Input ; (7) 3445 ps ; (7) 3445 ps ; -- ; -- ; -- ; -- ; -- ; -- ;; distancia_i[3] ; Input ; (7) 3445 ps ; (7) 3445 ps ; -- ; -- ; -- ; -- ; -- ; -- ;; distancia_i[4] ; Input ; (7) 3445 ps ; (7) 3445 ps ; -- ; -- ; -- ; -- ; -- ; -- ;; distancia_i[2] ; Input ; (7) 3544 ps ; (7) 3544 ps ; -- ; -- ; -- ; -- ; -- ; -- ;; distancia_i[0] ; Input ; (7) 3445 ps ; (7) 3445 ps ; -- ; -- ; -- ; -- ; -- ; -- ;; distancia_i[1] ; Input ; (7) 3544 ps ; (7) 3544 ps ; -- ; -- ; -- ; -- ; -- ; -- ;; distancia_i[6] ; Input ; (7) 3544 ps ; (7) 3544 ps ; -- ; -- ; -- ; -- ; -- ; -- ;; distancia_i[7] ; Input ; (7) 3544 ps ; (7) 3544 ps ; -- ; -- ; -- ; -- ; -- ; -- ;+----------------+----------+---------------+---------------+-----------------------+-----+-----------+---------+----------+------------++------------------------------------------------------+; Pad To Core Delay Chain Fanout ;+------------------------+-------------------+---------+; Source Pin / Fanout ; Pad To Core Index ; Setting ;+------------------------+-------------------+---------+; extrapolar_i ; ; ;; - Add2~9 ; 0 ; 7 ;; - Add2~13 ; 0 ; 7 ;; - Add2~17 ; 0 ; 7 ;; - Add2~21 ; 0 ; 7 ;; - Add2~25 ; 0 ; 7 ;; - Add2~29 ; 0 ; 7 ;; - Add2~33 ; 0 ; 7 ;; - Add2~37 ; 0 ; 7 ;; - Add2~41 ; 0 ; 7 ;; - Add2~45 ; 0 ; 7 ;; - Add2~49 ; 0 ; 7 ;; - Add2~53 ; 0 ; 7 ;; - Add2~57 ; 0 ; 7 ;; - Add2~61 ; 0 ; 7 ;; - Add2~65 ; 0 ; 7 ;; - Add2~69 ; 0 ; 7 ;; - Add6~1 ; 0 ; 7 ;; - Add6~5 ; 0 ; 7 ;; - Add6~9 ; 0 ; 7 ;; - Add6~13 ; 0 ; 7 ;; - Add6~17 ; 0 ; 7 ;; - Add6~21 ; 0 ; 7 ;; - Add6~25 ; 0 ; 7 ;; - Add6~29 ; 0 ; 7 ;; - Add6~33 ; 0 ; 7 ;; - Add6~37 ; 0 ; 7 ;; - Add6~41 ; 0 ; 7 ;; - Add6~45 ; 0 ; 7 ;; - Add6~49 ; 0 ; 7 ;; - Add6~53 ; 0 ; 7 ;; - Add6~57 ; 0 ; 7 ;; - Add6~61 ; 0 ; 7 ;; - Add0~1 ; 0 ; 7 ;; - fx~0 ; 0 ; 7 ;; - fx~1 ; 0 ; 7 ;; - fx~2 ; 0 ; 7 ;; - fx~3 ; 0 ; 7 ;; - fx~4 ; 0 ; 7 ;; - fx~5 ; 0 ; 7 ;; - fx~6 ; 0 ; 7 ;; - fx~7 ; 0 ; 7 ;; - fx~8 ; 0 ; 7 ;; - fx~9 ; 0 ; 7 ;; - fx~10 ; 0 ; 7 ;; - fx~11 ; 0 ; 7 ;; - fx~12 ; 0 ; 7 ;; - fx~13 ; 0 ; 7 ;; - fx~14 ; 0 ; 7 ;; - fx~15 ; 0 ; 7 ;; - fx~16 ; 0 ; 7 ;; - fx~17 ; 0 ; 7 ;; - fx~18 ; 0 ; 7 ;; - fx~19 ; 0 ; 7 ;; - fx~20 ; 0 ; 7 ;; - fx~21 ; 0 ; 7 ;; - fx~22 ; 0 ; 7 ;; - fx~23 ; 0 ; 7 ;; - fx~24 ; 0 ; 7 ;; - fx~25 ; 0 ; 7 ;; - fx~26 ; 0 ; 7 ;; - fx~27 ; 0 ; 7 ;; - fx~28 ; 0 ; 7 ;; - fx~29 ; 0 ; 7 ;; - fx~30 ; 0 ; 7 ;; - fx~31 ; 0 ; 7 ;; clk_i ; ; ;; rst_i ; ; ;; - resultado[0] ; 1 ; 7 ;; - fxx_o[15]~reg0 ; 1 ; 7 ;; - fxx_o[14]~reg0 ; 1 ; 7 ;; - fxx_o[13]~reg0 ; 1 ; 7 ;; - fxx_o[12]~reg0 ; 1 ; 7 ;; - fxx_o[11]~reg0 ; 1 ; 7 ;; - fxx_o[10]~reg0 ; 1 ; 7 ;; - fxx_o[9]~reg0 ; 1 ; 7 ;; - fxx_o[8]~reg0 ; 1 ; 7 ;; - fxx_o[7]~reg0 ; 1 ; 7 ;; - fxx_o[6]~reg0 ; 1 ; 7 ;; - fxx_o[5]~reg0 ; 1 ; 7 ;; - fxx_o[4]~reg0 ; 1 ; 7 ;; - fxx_o[3]~reg0 ; 1 ; 7 ;; - fxx_o[2]~reg0 ; 1 ; 7 ;; - fxx_o[1]~reg0 ; 1 ; 7 ;; - fxx_o[0]~reg0 ; 1 ; 7 ;; - fxx1_o[14]~reg0 ; 1 ; 7 ;; - fxx1_o[11]~reg0 ; 1 ; 7 ;; - fxx1_o[9]~reg0 ; 1 ; 7 ;; - fxx1_o[7]~reg0 ; 1 ; 7 ;; - fxx1_o[6]~reg0 ; 1 ; 7 ;; - fxx1_o[5]~reg0 ; 1 ; 7 ;; - fxx1_o[4]~reg0 ; 1 ; 7 ;; - fxx1_o[3]~reg0 ; 1 ; 7 ;; - fxx1_o[2]~reg0 ; 1 ; 7 ;; - fxx1_o[1]~reg0 ; 1 ; 7 ;; - fxx1_o[0]~reg0 ; 1 ; 7 ;; - fxx2_o[15]~reg0 ; 1 ; 7 ;; - fxx2_o[14]~reg0 ; 1 ; 7 ;; - fxx2_o[13]~reg0 ; 1 ; 7 ;; - fxx2_o[12]~reg0 ; 1 ; 7 ;; - fxx2_o[11]~reg0 ; 1 ; 7 ;; - fxx2_o[10]~reg0 ; 1 ; 7 ;; - fxx2_o[9]~reg0 ; 1 ; 7 ;; - fxx2_o[8]~reg0 ; 1 ; 7 ;; - fxx2_o[7]~reg0 ; 1 ; 7 ;; - fxx2_o[6]~reg0 ; 1 ; 7 ;; - fxx2_o[5]~reg0 ; 1 ; 7 ;; - fxx2_o[4]~reg0 ; 1 ; 7 ;; - fxx2_o[3]~reg0 ; 1 ; 7 ;; - fxx2_o[2]~reg0 ; 1 ; 7 ;; - fxx2_o[1]~reg0 ; 1 ; 7 ;; - fxx2_o[0]~reg0 ; 1 ; 7 ;; - fxx3_o[15]~reg0 ; 1 ; 7 ;; - fxx3_o[14]~reg0 ; 1 ; 7 ;; - fxx3_o[13]~reg0 ; 1 ; 7 ;; - fxx3_o[12]~reg0 ; 1 ; 7 ;; - fxx3_o[11]~reg0 ; 1 ; 7 ;; - fxx3_o[10]~reg0 ; 1 ; 7 ;; - fxx3_o[9]~reg0 ; 1 ; 7 ;; - fxx3_o[8]~reg0 ; 1 ; 7 ;; - fxx3_o[7]~reg0 ; 1 ; 7 ;; - fxx3_o[6]~reg0 ; 1 ; 7 ;; - fxx3_o[5]~reg0 ; 1 ; 7 ;; - fxx3_o[4]~reg0 ; 1 ; 7 ;; - fxx3_o[3]~reg0 ; 1 ; 7 ;; - fxx3_o[2]~reg0 ; 1 ; 7 ;; - fxx3_o[1]~reg0 ; 1 ; 7 ;; - fxx3_o[0]~reg0 ; 1 ; 7 ;; - fxx4_o[15]~reg0 ; 1 ; 7 ;; - fxx4_o[14]~reg0 ; 1 ; 7 ;; - fxx4_o[13]~reg0 ; 1 ; 7 ;; - fxx4_o[12]~reg0 ; 1 ; 7 ;; - fxx4_o[11]~reg0 ; 1 ; 7 ;; - fxx4_o[10]~reg0 ; 1 ; 7 ;; - fxx4_o[9]~reg0 ; 1 ; 7 ;; - fxx4_o[8]~reg0 ; 1 ; 7 ;; - fxx4_o[7]~reg0 ; 1 ; 7 ;; - fxx4_o[6]~reg0 ; 1 ; 7 ;; - fxx4_o[5]~reg0 ; 1 ; 7 ;; - fxx4_o[4]~reg0 ; 1 ; 7 ;; - fxx4_o[3]~reg0 ; 1 ; 7 ;; - fxx4_o[2]~reg0 ; 1 ; 7 ;; - fxx4_o[1]~reg0 ; 1 ; 7 ;; - fxx4_o[0]~reg0 ; 1 ; 7 ;; - resultado[1] ; 1 ; 7 ;; - resultado[2] ; 1 ; 7 ;; - resultado[3] ; 1 ; 7 ;; - resultado[4] ; 1 ; 7 ;; - resultado[5] ; 1 ; 7 ;; - resultado[6] ; 1 ; 7 ;; - resultado[7] ; 1 ; 7 ;; - resultado[8] ; 1 ; 7 ;; - resultado[9] ; 1 ; 7 ;; - resultado[10] ; 1 ; 7 ;; - resultado[11] ; 1 ; 7 ;; - resultado[12] ; 1 ; 7 ;; - resultado[13] ; 1 ; 7 ;; - resultado[14] ; 1 ; 7 ;; - resul_o[15]~0 ; 1 ; 7 ;; distancia_i[5] ; ; ;; - Equal0~0 ; 0 ; 7 ;; distancia_i[3] ; ; ;; - Equal0~0 ; 0 ; 7 ;; distancia_i[4] ; ; ;; - Equal0~0 ; 0 ; 7 ;; distancia_i[2] ; ; ;; - Equal0~1 ; 1 ; 7 ;; distancia_i[0] ; ; ;; - Equal0~1 ; 1 ; 7 ;; distancia_i[1] ; ; ;; - Equal0~1 ; 0 ; 7 ;; distancia_i[6] ; ; ;; - Equal0~2 ; 0 ; 7 ;; - Equal0~3 ; 0 ; 7 ;; distancia_i[7] ; ; ;; - resul_o[15]~0 ; 0 ; 7 ;; - Equal0~3 ; 0 ; 7 ;+------------------------+-------------------+---------++-------------------------------------------------------------------------------------------------------------------------------------------+; Control Signals ;+---------------+-------------------+---------+--------------+--------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+---------------+-------------------+---------+--------------+--------+----------------------+------------------+---------------------------+; Equal0~3 ; LCCOMB_X27_Y5_N10 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ;; clk_i ; PIN_N20 ; 191 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ;; resul_o[15]~0 ; LCCOMB_X27_Y5_N14 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;; rst_i ; PIN_M21 ; 98 ; Clock enable ; no ; -- ; -- ; -- ;; rst_i ; PIN_M21 ; 78 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ;+---------------+-------------------+---------+--------------+--------+----------------------+------------------+---------------------------++--------------------------------------------------------------------------------------------------+; Global & Other Fast Signals ;+-------+----------+---------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+-------+----------+---------+----------------------+------------------+---------------------------+; clk_i ; PIN_N20 ; 191 ; Global Clock ; GCLK3 ; -- ;; rst_i ; PIN_M21 ; 78 ; Global Clock ; GCLK1 ; -- ;+-------+----------+---------+----------------------+------------------+---------------------------++---------------------------------+; Non-Global High Fan-Out Signals ;+---------------+-----------------+; Name ; Fan-Out ;+---------------+-----------------+; rst_i ; 97 ;; extrapolar_i ; 65 ;; resul_o[15]~0 ; 16 ;; i[0] ; 16 ;; Equal0~3 ; 8 ;; resultado[15] ; 4 ;; resultado[14] ; 4 ;; resultado[13] ; 4 ;; resultado[12] ; 4 ;; resultado[11] ; 4 ;; resultado[10] ; 4 ;; resultado[9] ; 4 ;; resultado[8] ; 4 ;; resultado[7] ; 4 ;; resultado[6] ; 4 ;; resultado[5] ; 4 ;; resultado[4] ; 4 ;; resultado[3] ; 4 ;; resultado[2] ; 4 ;; resultado[1] ; 4 ;; resultado[0] ; 4 ;; Add4~69 ; 4 ;; Add4~65 ; 4 ;; Add4~61 ; 4 ;; Add4~57 ; 4 ;; Add4~53 ; 4 ;; Add4~49 ; 4 ;; Add4~45 ; 4 ;; Add4~41 ; 4 ;; Add4~37 ; 4 ;; Add4~33 ; 4 ;; Add4~29 ; 4 ;; Add4~25 ; 4 ;; Add4~21 ; 4 ;; Add4~17 ; 4 ;; Add4~13 ; 4 ;; Add4~9 ; 4 ;; Add3~65 ; 4 ;; Add3~61 ; 4 ;; Add3~57 ; 4 ;; Add3~53 ; 4 ;; Add3~49 ; 4 ;; Add3~45 ; 4 ;; Add3~41 ; 4 ;; Add3~37 ; 4 ;; Add3~33 ; 4 ;; Add3~29 ; 4 ;; Add3~25 ; 4 ;; Add3~21 ; 4 ;; Add3~17 ; 4 ;+---------------+-----------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter RAM Summary ;+----------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------+------+--------+--------------------+-------------+; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M512s ; M4Ks ; M-RAMs ; MIF ; Location ;+----------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------+------+--------+--------------------+-------------+; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ALTSYNCRAM ; M512 ; ROM ; Single Clock ; 32 ; 16 ; -- ; -- ; yes ; no ; -- ; -- ; 512 ; 32 ; 16 ; -- ; -- ; 512 ; 1 ; 0 ; 0 ; gnextrapolator.mif ; M512_X24_Y8 ;+----------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------+------+--------+--------------------+-------------+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.+--------------------------------------------------------------------+; Interconnect Usage Summary ;+-------------------------------------------+------------------------+; Interconnect Resource Type ; Usage ;+-------------------------------------------+------------------------+; Block interconnects ; 453 / 51,960 ( < 1 % ) ;; C16 interconnects ; 18 / 1,680 ( 1 % ) ;; C4 interconnects ; 379 / 38,400 ( < 1 % ) ;; DPA clocks ; 0 / 4 ( 0 % ) ;; DQS bus muxes ; 0 / 18 ( 0 % ) ;; DQS-18 I/O buses ; 0 / 4 ( 0 % ) ;; DQS-4 I/O buses ; 0 / 18 ( 0 % ) ;; DQS-9 I/O buses ; 0 / 8 ( 0 % ) ;; Differential I/O clocks ; 0 / 32 ( 0 % ) ;; Direct links ; 54 / 51,960 ( < 1 % ) ;; Global clocks ; 2 / 16 ( 13 % ) ;; Local interconnects ; 58 / 12,480 ( < 1 % ) ;; NDQS bus muxes ; 0 / 18 ( 0 % ) ;; NDQS-18 I/O buses ; 0 / 4 ( 0 % ) ;; NDQS-4 I/O buses ; 0 / 18 ( 0 % ) ;; NDQS-9 I/O buses ; 0 / 8 ( 0 % ) ;; PLL transmitter or receiver load enables ; 0 / 8 ( 0 % ) ;; PLL transmitter or receiver synch. clocks ; 0 / 8 ( 0 % ) ;; R24 interconnects ; 16 / 1,664 ( < 1 % ) ;; R24/C16 interconnect drivers ; 23 / 4,160 ( < 1 % ) ;; R4 interconnects ; 524 / 59,488 ( < 1 % ) ;; Regional clocks ; 0 / 32 ( 0 % ) ;+-------------------------------------------+------------------------++-----------------------------------------------------------------+; LAB Logic Elements ;+----------------------------------+------------------------------+; Number of ALMs (Average = 7.31) ; Number of LABs (Total = 16) ;+----------------------------------+------------------------------+; 1 ; 0 ;; 2 ; 0 ;; 3 ; 1 ;; 4 ; 1 ;; 5 ; 0 ;; 6 ; 1 ;; 7 ; 0 ;; 8 ; 13 ;+----------------------------------+------------------------------++-------------------------------------------------------------------+; LAB-wide Signals ;+------------------------------------+------------------------------+; LAB-wide Signals (Average = 2.63) ; Number of LABs (Total = 16) ;+------------------------------------+------------------------------+; 1 Async. clear ; 11 ;; 1 Clock ; 16 ;; 1 Clock enable ; 13 ;; 1 Sync. clear ; 1 ;; 2 Clock enables ; 1 ;+------------------------------------+------------------------------++-----------------------------------------------------------------------------+; LAB Signals Sourced ;+----------------------------------------------+------------------------------+; Number of Signals Sourced (Average = 15.94) ; Number of LABs (Total = 16) ;+----------------------------------------------+------------------------------+; 0 ; 0 ;; 1 ; 0 ;; 2 ; 0 ;; 3 ; 0 ;; 4 ; 0 ;; 5 ; 0 ;; 6 ; 1 ;; 7 ; 1 ;; 8 ; 1 ;; 9 ; 0 ;; 10 ; 0 ;; 11 ; 1 ;; 12 ; 0 ;; 13 ; 1 ;; 14 ; 0 ;; 15 ; 1 ;; 16 ; 1 ;; 17 ; 1 ;; 18 ; 0 ;; 19 ; 3 ;; 20 ; 2 ;; 21 ; 2 ;; 22 ; 0 ;; 23 ; 1 ;+----------------------------------------------+------------------------------++---------------------------------------------------------------------------------+; LAB Signals Sourced Out ;+--------------------------------------------------+------------------------------+; Number of Signals Sourced Out (Average = 10.75) ; Number of LABs (Total = 16) ;+--------------------------------------------------+------------------------------+; 0 ; 1 ;; 1 ; 0 ;; 2 ; 0 ;; 3 ; 0 ;; 4 ; 1 ;; 5 ; 1 ;; 6 ; 0 ;; 7 ; 0 ;; 8 ; 2 ;; 9 ; 1 ;; 10 ; 2 ;; 11 ; 0 ;; 12 ; 1 ;; 13 ; 2 ;; 14 ; 2 ;; 15 ; 0 ;; 16 ; 1 ;; 17 ; 1 ;; 18 ; 0 ;; 19 ; 1 ;+--------------------------------------------------+------------------------------++-----------------------------------------------------------------------------+; LAB Distinct Inputs ;+----------------------------------------------+------------------------------+; Number of Distinct Inputs (Average = 23.31) ; Number of LABs (Total = 16) ;+----------------------------------------------+------------------------------+; 0 ; 0 ;; 1 ; 0 ;; 2 ; 1 ;; 3 ; 0 ;; 4 ; 1 ;; 5 ; 0 ;; 6 ; 0 ;; 7 ; 0 ;; 8 ; 0 ;; 9 ; 0 ;; 10 ; 0 ;; 11 ; 0 ;; 12 ; 0 ;; 13 ; 0 ;; 14 ; 0 ;; 15 ; 1 ;; 16 ; 1 ;; 17 ; 0 ;; 18 ; 2 ;; 19 ; 0 ;; 20 ; 0 ;; 21 ; 0 ;; 22 ; 0 ;; 23 ; 0 ;; 24 ; 0 ;; 25 ; 0 ;; 26 ; 1 ;; 27 ; 0 ;; 28 ; 2 ;; 29 ; 1 ;; 30 ; 3 ;; 31 ; 1 ;; 32 ; 0 ;; 33 ; 1 ;; 34 ; 0 ;; 35 ; 1 ;+----------------------------------------------+------------------------------++------------------------------------------+; I/O Rules Summary ;+----------------------------------+-------+; I/O Rules Statistic ; Total ;+----------------------------------+-------+; Total I/O Rules ; 31 ;; Number of I/O Rules Passed ; 4 ;; Number of I/O Rules Failed ; 0 ;; Number of I/O Rules Unchecked ; 0 ;; Number of I/O Rules Inapplicable ; 27 ;+----------------------------------+-------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; I/O Rules Details ;+--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;+--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ;; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No PCI I/O assignments found. ; I/O ; ;; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No PCI I/O assignments found. ; I/O ; ;; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;; Inapplicable ; IO_000032 ; I/O Properties Checks for Multiple I/Os ; I/O registers and SERDES should not be used at the same XY location. ; Critical ; No I/O Registers or Differential I/O Standard assignments found. ; I/O ; ;; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 250mA for row I/Os and 250mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 1 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;; Inapplicable ; IO_000037 ; SI Related Distance Checks ; Single-ended I/O and differential I/O should not coexist in a PLL output I/O bank. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;; Inapplicable ; IO_000038 ; SI Related SSO Limit Checks ; Single-ended outputs and High-speed LVDS should not coexist in an I/O bank. ; High ; No High-speed LVDS found. ; I/O ; ;; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;; Inapplicable ; IO_000040 ; SI Related SSO Limit Checks ; The total drive strength of single ended outputs in a DPA bank should not exceed 120mA. ; High ; No DPA found. ; I/O ; ;+--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; I/O Rules Matrix ;+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000032 ; IO_000033 ; IO_000034 ; IO_000037 ; IO_000038 ; IO_000042 ; IO_000040 ;+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 107 ; 0 ; 0 ; 107 ; 107 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 107 ; 0 ; 0 ; 0 ; 0 ; 0 ;; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; Total Inapplicable ; 107 ; 107 ; 107 ; 107 ; 107 ; 0 ; 107 ; 107 ; 0 ; 0 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 0 ; 107 ; 107 ; 107 ; 107 ; 107 ;; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; fxx_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx_o[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx_o[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx_o[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx_o[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx_o[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx_o[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx_o[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx_o[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx_o[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx_o[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx_o[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx_o[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx_o[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx1_o[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx2_o[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx3_o[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; fxx4_o[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; resul_o[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; extrapolar_i ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; clk_i ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; rst_i ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; distancia_i[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; distancia_i[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; distancia_i[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; distancia_i[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; distancia_i[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; distancia_i[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; distancia_i[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; distancia_i[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------++-------------------------------------------------------------------------+; Fitter Device Options ;+----------------------------------------------+--------------------------+; Option ; Setting ;+----------------------------------------------+--------------------------+; Enable user-supplied start-up clock (CLKUSR) ; Off ;; Enable device-wide reset (DEV_CLRn) ; Off ;; Enable device-wide output enable (DEV_OE) ; Off ;; Enable INIT_DONE output ; Off ;; Configuration scheme ; Passive Serial ;; Error detection CRC ; Off ;; Configuration Voltage Level ; Auto ;; Force Configuration Voltage Level ; Off ;; nWS, nRS, nCS, CS ; Unreserved ;; RDYnBUSY ; Unreserved ;; Data[7..1] ; Unreserved ;; Data[0] ; As input tri-stated ;; ASDO,nCSO ; Unreserved ;; Reserve all unused pins ; As output driving ground ;; Base pin-out file on sameframe device ; Off ;+----------------------------------------------+--------------------------++------------------------------------+; Operating Settings and Conditions ;+---------------------------+--------+; Setting ; Value ;+---------------------------+--------+; Nominal Core Voltage ; 1.20 V ;+---------------------------+--------++------------------------------------------------------------+; Estimated Delay Added for Hold Timing ;+-----------------+----------------------+-------------------+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;+-----------------+----------------------+-------------------++-----------------+; Fitter Messages ;+-----------------+Info: *******************************************************************Info: Running Quartus II FitterInfo: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web EditionInfo: Processing started: Tue Aug 14 00:27:38 2012Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolatorInfo: Selected device EP2S15F484C4 for design "gnextrapolator"Info: Low junction temperature is 0 degrees CInfo: High junction temperature is 85 degrees CInfo: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation timeWarning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devicesInfo: Device EP2S15F484I4 is compatibleInfo: Fitter converted 1 user pins into dedicated programming pinsInfo: Pin ~DATA0~ is reserved at location E13Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.Critical Warning: No exact pin location assignment(s) for 107 pins of 107 total pinsInfo: Pin fxx_o[0] not assigned to an exact location on the deviceInfo: Pin fxx_o[1] not assigned to an exact location on the deviceInfo: Pin fxx_o[2] not assigned to an exact location on the deviceInfo: Pin fxx_o[3] not assigned to an exact location on the deviceInfo: Pin fxx_o[4] not assigned to an exact location on the deviceInfo: Pin fxx_o[5] not assigned to an exact location on the deviceInfo: Pin fxx_o[6] not assigned to an exact location on the deviceInfo: Pin fxx_o[7] not assigned to an exact location on the deviceInfo: Pin fxx_o[8] not assigned to an exact location on the deviceInfo: Pin fxx_o[9] not assigned to an exact location on the deviceInfo: Pin fxx_o[10] not assigned to an exact location on the deviceInfo: Pin fxx_o[11] not assigned to an exact location on the deviceInfo: Pin fxx_o[12] not assigned to an exact location on the deviceInfo: Pin fxx_o[13] not assigned to an exact location on the deviceInfo: Pin fxx_o[14] not assigned to an exact location on the deviceInfo: Pin fxx_o[15] not assigned to an exact location on the deviceInfo: Pin fxx1_o[0] not assigned to an exact location on the deviceInfo: Pin fxx1_o[1] not assigned to an exact location on the deviceInfo: Pin fxx1_o[2] not assigned to an exact location on the deviceInfo: Pin fxx1_o[3] not assigned to an exact location on the deviceInfo: Pin fxx1_o[4] not assigned to an exact location on the deviceInfo: Pin fxx1_o[5] not assigned to an exact location on the deviceInfo: Pin fxx1_o[6] not assigned to an exact location on the deviceInfo: Pin fxx1_o[7] not assigned to an exact location on the deviceInfo: Pin fxx1_o[8] not assigned to an exact location on the deviceInfo: Pin fxx1_o[9] not assigned to an exact location on the deviceInfo: Pin fxx1_o[10] not assigned to an exact location on the deviceInfo: Pin fxx1_o[11] not assigned to an exact location on the deviceInfo: Pin fxx1_o[12] not assigned to an exact location on the deviceInfo: Pin fxx1_o[13] not assigned to an exact location on the deviceInfo: Pin fxx1_o[14] not assigned to an exact location on the deviceInfo: Pin fxx1_o[15] not assigned to an exact location on the deviceInfo: Pin fxx2_o[0] not assigned to an exact location on the deviceInfo: Pin fxx2_o[1] not assigned to an exact location on the deviceInfo: Pin fxx2_o[2] not assigned to an exact location on the deviceInfo: Pin fxx2_o[3] not assigned to an exact location on the deviceInfo: Pin fxx2_o[4] not assigned to an exact location on the deviceInfo: Pin fxx2_o[5] not assigned to an exact location on the deviceInfo: Pin fxx2_o[6] not assigned to an exact location on the deviceInfo: Pin fxx2_o[7] not assigned to an exact location on the deviceInfo: Pin fxx2_o[8] not assigned to an exact location on the deviceInfo: Pin fxx2_o[9] not assigned to an exact location on the deviceInfo: Pin fxx2_o[10] not assigned to an exact location on the deviceInfo: Pin fxx2_o[11] not assigned to an exact location on the deviceInfo: Pin fxx2_o[12] not assigned to an exact location on the deviceInfo: Pin fxx2_o[13] not assigned to an exact location on the deviceInfo: Pin fxx2_o[14] not assigned to an exact location on the deviceInfo: Pin fxx2_o[15] not assigned to an exact location on the deviceInfo: Pin fxx3_o[0] not assigned to an exact location on the deviceInfo: Pin fxx3_o[1] not assigned to an exact location on the deviceInfo: Pin fxx3_o[2] not assigned to an exact location on the deviceInfo: Pin fxx3_o[3] not assigned to an exact location on the deviceInfo: Pin fxx3_o[4] not assigned to an exact location on the deviceInfo: Pin fxx3_o[5] not assigned to an exact location on the deviceInfo: Pin fxx3_o[6] not assigned to an exact location on the deviceInfo: Pin fxx3_o[7] not assigned to an exact location on the deviceInfo: Pin fxx3_o[8] not assigned to an exact location on the deviceInfo: Pin fxx3_o[9] not assigned to an exact location on the deviceInfo: Pin fxx3_o[10] not assigned to an exact location on the deviceInfo: Pin fxx3_o[11] not assigned to an exact location on the deviceInfo: Pin fxx3_o[12] not assigned to an exact location on the deviceInfo: Pin fxx3_o[13] not assigned to an exact location on the deviceInfo: Pin fxx3_o[14] not assigned to an exact location on the deviceInfo: Pin fxx3_o[15] not assigned to an exact location on the deviceInfo: Pin fxx4_o[0] not assigned to an exact location on the deviceInfo: Pin fxx4_o[1] not assigned to an exact location on the deviceInfo: Pin fxx4_o[2] not assigned to an exact location on the deviceInfo: Pin fxx4_o[3] not assigned to an exact location on the deviceInfo: Pin fxx4_o[4] not assigned to an exact location on the deviceInfo: Pin fxx4_o[5] not assigned to an exact location on the deviceInfo: Pin fxx4_o[6] not assigned to an exact location on the deviceInfo: Pin fxx4_o[7] not assigned to an exact location on the deviceInfo: Pin fxx4_o[8] not assigned to an exact location on the deviceInfo: Pin fxx4_o[9] not assigned to an exact location on the deviceInfo: Pin fxx4_o[10] not assigned to an exact location on the deviceInfo: Pin fxx4_o[11] not assigned to an exact location on the deviceInfo: Pin fxx4_o[12] not assigned to an exact location on the deviceInfo: Pin fxx4_o[13] not assigned to an exact location on the deviceInfo: Pin fxx4_o[14] not assigned to an exact location on the deviceInfo: Pin fxx4_o[15] not assigned to an exact location on the deviceInfo: Pin resul_o[0] not assigned to an exact location on the deviceInfo: Pin resul_o[1] not assigned to an exact location on the deviceInfo: Pin resul_o[2] not assigned to an exact location on the deviceInfo: Pin resul_o[3] not assigned to an exact location on the deviceInfo: Pin resul_o[4] not assigned to an exact location on the deviceInfo: Pin resul_o[5] not assigned to an exact location on the deviceInfo: Pin resul_o[6] not assigned to an exact location on the deviceInfo: Pin resul_o[7] not assigned to an exact location on the deviceInfo: Pin resul_o[8] not assigned to an exact location on the deviceInfo: Pin resul_o[9] not assigned to an exact location on the deviceInfo: Pin resul_o[10] not assigned to an exact location on the deviceInfo: Pin resul_o[11] not assigned to an exact location on the deviceInfo: Pin resul_o[12] not assigned to an exact location on the deviceInfo: Pin resul_o[13] not assigned to an exact location on the deviceInfo: Pin resul_o[14] not assigned to an exact location on the deviceInfo: Pin resul_o[15] not assigned to an exact location on the deviceInfo: Pin extrapolar_i not assigned to an exact location on the deviceInfo: Pin clk_i not assigned to an exact location on the deviceInfo: Pin rst_i not assigned to an exact location on the deviceInfo: Pin distancia_i[5] not assigned to an exact location on the deviceInfo: Pin distancia_i[3] not assigned to an exact location on the deviceInfo: Pin distancia_i[4] not assigned to an exact location on the deviceInfo: Pin distancia_i[2] not assigned to an exact location on the deviceInfo: Pin distancia_i[0] not assigned to an exact location on the deviceInfo: Pin distancia_i[1] not assigned to an exact location on the deviceInfo: Pin distancia_i[6] not assigned to an exact location on the deviceInfo: Pin distancia_i[7] not assigned to an exact location on the deviceWarning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for detailsInfo: Timing-driven compilation is using the Classic Timing AnalyzerInfo: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.Info: Automatically promoted node clk_i (placed in PIN N20 (CLK3p, Input))Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3Info: Automatically promoted node rst_i (placed in PIN M21 (CLK1p, Input))Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1Info: Following destination nodes may be non-global or may not use global or regional clocksInfo: Destination node resultado[0]Info: Destination node fxx_o[15]~reg0Info: Destination node fxx_o[14]~reg0Info: Destination node fxx_o[13]~reg0Info: Destination node fxx_o[12]~reg0Info: Destination node fxx_o[11]~reg0Info: Destination node fxx_o[10]~reg0Info: Destination node fxx_o[9]~reg0Info: Destination node fxx_o[8]~reg0Info: Destination node fxx_o[7]~reg0Info: Non-global destination nodes limited to 10 nodesInfo: Starting register packingExtra Info: Performing register packing on registers with non-logic cell location assignmentsExtra Info: Completed register packing on registers with non-logic cell location assignmentsExtra Info: Started Fast Input/Output/OE register processingExtra Info: Finished Fast Input/Output/OE register processingExtra Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and densityExtra Info: Finished moving registers into I/O cells, DSP blocks, and RAM blocksInfo: Finished register packingExtra Info: No registers were packed into other blocksInfo: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placementInfo: Number of I/O pins in group: 105 (unused VREF, 3.3V VCCIO, 9 input, 96 output, 0 bidirectional)Info: I/O standards used: 3.3-V LVTTL.Info: I/O bank details before I/O pin placementInfo: Statistics of I/O banksInfo: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 39 pins availableInfo: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 43 pins availableInfo: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 49 pins availableInfo: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins availableInfo: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins availableInfo: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins availableInfo: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 34 pins availableInfo: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins availableInfo: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins availableInfo: I/O bank number 10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins availableInfo: Fitter preparation operations ending: elapsed time is 00:00:03Info: Fitter placement preparation operations beginningInfo: Fitter placement preparation operations ending: elapsed time is 00:00:00Info: Fitter placement operations beginningInfo: Fitter placement was successfulInfo: Fitter placement operations ending: elapsed time is 00:00:03Info: Estimated most critical path is memory to register delay of 10.924 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X24_Y8; Fanout = 1; MEM Node = 'altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7~porta_address_reg4'Info: 2: + IC(0.000 ns) + CELL(2.061 ns) = 2.061 ns; Loc. = M512_X24_Y8; Fanout = 6; MEM Node = 'altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7'Info: 3: + IC(0.821 ns) + CELL(0.313 ns) = 3.195 ns; Loc. = LAB_X27_Y5; Fanout = 2; COMB Node = 'fx~23'Info: 4: + IC(0.879 ns) + CELL(0.480 ns) = 4.554 ns; Loc. = LAB_X23_Y8; Fanout = 6; COMB Node = 'Add2~37'Info: 5: + IC(0.580 ns) + CELL(0.480 ns) = 5.614 ns; Loc. = LAB_X22_Y7; Fanout = 7; COMB Node = 'Add3~33'Info: 6: + IC(0.833 ns) + CELL(0.426 ns) = 6.873 ns; Loc. = LAB_X22_Y6; Fanout = 7; COMB Node = 'Add4~37'Info: 7: + IC(0.775 ns) + CELL(0.480 ns) = 8.128 ns; Loc. = LAB_X25_Y6; Fanout = 2; COMB Node = 'Add8~29'Info: 8: + IC(0.580 ns) + CELL(0.403 ns) = 9.111 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~30'Info: 9: + IC(0.102 ns) + CELL(0.041 ns) = 9.254 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~34'Info: 10: + IC(0.000 ns) + CELL(0.041 ns) = 9.295 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~38'Info: 11: + IC(0.000 ns) + CELL(0.041 ns) = 9.336 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~42'Info: 12: + IC(0.000 ns) + CELL(0.041 ns) = 9.377 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~46'Info: 13: + IC(0.000 ns) + CELL(0.041 ns) = 9.418 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~50'Info: 14: + IC(0.000 ns) + CELL(0.041 ns) = 9.459 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~54'Info: 15: + IC(0.000 ns) + CELL(0.041 ns) = 9.500 ns; Loc. = LAB_X26_Y5; Fanout = 1; COMB Node = 'Add9~58'Info: 16: + IC(0.000 ns) + CELL(0.144 ns) = 9.644 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~61'Info: 17: + IC(1.102 ns) + CELL(0.178 ns) = 10.924 ns; Loc. = LAB_X23_Y7; Fanout = 4; REG Node = 'resultado[15]'Info: Total cell delay = 5.252 ns ( 48.08 % )Info: Total interconnect delay = 5.672 ns ( 51.92 % )Info: Fitter routing operations beginningInfo: Average interconnect usage is 0% of the available device resourcesInfo: Peak interconnect usage is 2% of the available device resources in the region that extends from location X13_Y0 to location X26_Y13Info: Fitter routing operations ending: elapsed time is 00:00:02Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.Info: Optimizations that may affect the design's routability were skippedInfo: Optimizations that may affect the design's timing were skippedInfo: Started post-fitting delay annotationWarning: Found 96 output pins without output pin load capacitance assignmentInfo: Pin "fxx_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx1_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx2_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx3_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "fxx4_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "resul_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Delay annotation completed successfullyWarning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.Info: Quartus II Fitter was successful. 0 errors, 5 warningsInfo: Peak virtual memory: 233 megabytesInfo: Processing ended: Tue Aug 14 00:28:05 2012Info: Elapsed time: 00:00:27Info: Total CPU time (on all processors): 00:00:27