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-- VHDL Instantiation Created from source file FreqDiv.vhd -- 10:14:57 05/14/2011
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

        COMPONENT FreqDiv
        PORT(
                Clk : IN std_logic;          
                Clk2 : OUT std_logic
                );
        END COMPONENT;

        Inst_FreqDiv: FreqDiv PORT MAP(
                Clk => ,
                Clk2 => 
        );