Subversion Repositories graphicsaccelerator

Release 12.3 - xst M.70d (lin)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
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Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
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Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
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Reading design: Synchronizer.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "Synchronizer.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "Synchronizer"
Output Format                      : NGC
Target Device                      : xa3s200-4-ftg256

---- Source Options
Top Module Name                    : Synchronizer
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/omar/LineFPGA/Synchronizer.vhd" in Library work.
Architecture behavioral of Entity synchronizer is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <Synchronizer> in library <work> (architecture <behavioral>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <Synchronizer> in library <work> (Architecture <behavioral>).
Entity <Synchronizer> analyzed. Unit <Synchronizer> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <Synchronizer>.
    Related source file is "/home/omar/LineFPGA/Synchronizer.vhd".
    Found finite state machine <FSM_0> for signal <YState>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 43                                             |
    | Inputs             | 5                                              |
    | Outputs            | 8                                              |
    | Clock              | Clk                       (rising_edge)        |
    | Reset              | YState$and0000            (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 01                                             |
    | Power Up State     | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <XState>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 48364                                          |
    | Inputs             | 23                                             |
    | Outputs            | 5                                              |
    | Clock              | Clk                       (rising_edge)        |
    | Clock enable       | XState$not0000            (positive)           |
    | Power Up State     | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 9-bit subtractor for signal <AddressY>.
    Found 9-bit register for signal <AddressOfY>.
    Found 9-bit adder for signal <nAddressOfY>.
    Found 11-bit adder for signal <nX>.
    Found 11-bit register for signal <X>.
    Found 21-bit up counter for signal <Y>.
    Summary:
        inferred   2 Finite State Machine(s).
        inferred   1 Counter(s).
        inferred  20 D-type flip-flop(s).
        inferred   3 Adder/Subtractor(s).
Unit <Synchronizer> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 3
 11-bit adder                                          : 1
 9-bit adder                                           : 1
 9-bit subtractor                                      : 1
# Counters                                             : 1
 21-bit up counter                                     : 1
# Registers                                            : 2
 11-bit register                                       : 1
 9-bit register                                        : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <XState/FSM> on signal <XState[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 11
 11    | 10
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <YState/FSM> on signal <YState[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 11
 11    | 10
-------------------

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 2
# Adders/Subtractors                                   : 3
 11-bit adder                                          : 1
 9-bit adder                                           : 1
 9-bit subtractor                                      : 1
# Counters                                             : 1
 21-bit up counter                                     : 1
# Registers                                            : 20
 Flip-Flops                                            : 20

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <Synchronizer> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block Synchronizer, actual ratio is 3.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 45
 Flip-Flops                                            : 45

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : Synchronizer.ngr
Top Level Output File Name         : Synchronizer
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 28

Cell Usage :
# BELS                             : 164
#      GND                         : 1
#      INV                         : 3
#      LUT1                        : 20
#      LUT2                        : 15
#      LUT2_L                      : 5
#      LUT3                        : 17
#      LUT3_L                      : 4
#      LUT4                        : 40
#      LUT4_D                      : 10
#      LUT4_L                      : 4
#      MUXCY                       : 20
#      MUXF5                       : 3
#      VCC                         : 1
#      XORCY                       : 21
# FlipFlops/Latches                : 45
#      FD                          : 10
#      FDE                         : 2
#      FDR                         : 23
#      FDRE                        : 9
#      FDS                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 27
#      IBUF                        : 3
#      OBUF                        : 24
=========================================================================

Device utilization summary:
---------------------------

Selected Device : xa3s200ftg256-4 

 Number of Slices:                       62  out of   1920     3%  
 Number of Slice Flip Flops:             45  out of   3840     1%  
 Number of 4 input LUTs:                118  out of   3840     3%  
 Number of IOs:                          28
 Number of bonded IOBs:                  28  out of    173    16%  
 Number of GCLKs:                         1  out of      8    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
Clk                                | BUFGP                  | 45    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 9.732ns (Maximum Frequency: 102.754MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 10.918ns
   Maximum combinational path delay: 8.957ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'Clk'
  Clock period: 9.732ns (frequency: 102.754MHz)
  Total number of paths / destination ports: 3100 / 89
-------------------------------------------------------------------------
Delay:               9.732ns (Levels of Logic = 5)
  Source:            Y_3 (FF)
  Destination:       Y_0 (FF)
  Source Clock:      Clk rising
  Destination Clock: Clk rising

  Data Path: Y_3 to Y_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.720   1.216  Y_3 (Y_3)
     LUT2_L:I0->LO         1   0.551   0.126  YState_cmp_eq00001_SW0 (N201)
     LUT4:I3->O            5   0.551   0.989  YState_cmp_eq00001 (N29)
     LUT4:I2->O           16   0.551   1.576  XState_FSM_FFd1-In15 (N2)
     LUT3:I0->O            1   0.551   0.000  Y_or0000_G (N51)
     MUXF5:I1->O          21   0.360   1.515  Y_or0000 (Y_or0000)
     FDR:R                     1.026          Y_0
    ----------------------------------------
    Total                      9.732ns (4.310ns logic, 5.422ns route)
                                       (44.3% logic, 55.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
  Total number of paths / destination ports: 64 / 24
-------------------------------------------------------------------------
Offset:              10.918ns (Levels of Logic = 3)
  Source:            AddressOfY_4 (FF)
  Destination:       AddressY<7> (PAD)
  Source Clock:      Clk rising

  Data Path: AddressOfY_4 to AddressY<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             3   0.720   1.246  AddressOfY_4 (AddressOfY_4)
     LUT4:I0->O            7   0.551   1.405  Madd_nAddressOfY_xor<5>1_SW0 (N01)
     LUT4:I0->O            1   0.551   0.801  Msub_AddressY_xor<7>11 (AddressY_7_OBUF)
     OBUF:I->O                 5.644          AddressY_7_OBUF (AddressY<7>)
    ----------------------------------------
    Total                     10.918ns (7.466ns logic, 3.452ns route)
                                       (68.4% logic, 31.6% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Delay:               8.957ns (Levels of Logic = 3)
  Source:            dataIn<1> (PAD)
  Destination:       B (PAD)

  Data Path: dataIn<1> to B
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.821   1.140  dataIn_1_IBUF (dataIn_1_IBUF)
     LUT2:I0->O            1   0.551   0.801  B2 (B_OBUF)
     OBUF:I->O                 5.644          B_OBUF (B)
    ----------------------------------------
    Total                      8.957ns (7.016ns logic, 1.941ns route)
                                       (78.3% logic, 21.7% route)

=========================================================================


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.43 secs
 
--> 


Total memory usage is 150684 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)