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Release 13.1 - xst O.40d (lin)Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.-->Parameter TMPDIR set to xst/projnav.tmpTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.07 secs-->Parameter xsthdpdir set to xstTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.07 secs-->Reading design: VGA_Top.prjTABLE OF CONTENTS1) Synthesis Options Summary2) HDL Compilation3) Design Hierarchy Analysis4) HDL Analysis5) HDL Synthesis5.1) HDL Synthesis Report6) Advanced HDL Synthesis6.1) Advanced HDL Synthesis Report7) Low Level Synthesis8) Partition Report9) Final Report9.1) Device utilization summary9.2) Partition Resource Summary9.3) TIMING REPORT=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "VGA_Top.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "VGA_Top"Output Format : NGCTarget Device : xc3s200-5-ft256---- Source OptionsTop Module Name : VGA_TopAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoSafe Implementation : NoFSM Style : LUTRAM Extraction : YesRAM Style : AutoROM Extraction : YesMux Style : AutoDecoder Extraction : YESPriority Encoder Extraction : YesShift Register Extraction : YESLogical Shifter Extraction : YESXOR Collapsing : YESROM Style : AutoMux Extraction : YesResource Sharing : YESAsynchronous To Synchronous : NOMultiplier Style : AutoAutomatic Register Balancing : No---- Target OptionsAdd IO Buffers : YESGlobal Maximum Fanout : 500Add Generic Clock Buffer(BUFG) : 8Register Duplication : YESSlice Packing : YESOptimize Instantiated Primitives : NOUse Clock Enable : YesUse Synchronous Set : YesUse Synchronous Reset : YesPack IO Registers into IOBs : AutoEquivalent register Removal : YES---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Keep Hierarchy : NoNetlist Hierarchy : As_OptimizedRTL Output : YesGlobal Optimization : AllClockNetsRead Cores : YESWrite Timing Constraints : NOCross Clock Analysis : NOHierarchy Separator : /Bus Delimiter : <>Case Specifier : MaintainSlice Utilization Ratio : 100BRAM Utilization Ratio : 100Verilog 2001 : YESAuto BRAM Packing : NOSlice Utilization Ratio Delta : 5==================================================================================================================================================* HDL Compilation *=========================================================================Compiling vhdl file "/home/omar/LineFPGA/FrameBuffer2.vhd" in Library work.Architecture behavioral of Entity framebuffer is up to date.Compiling vhdl file "/home/omar/LineFPGA/Synchronizer.vhd" in Library work.Architecture behavioral of Entity synchronizer is up to date.Compiling vhdl file "/home/omar/LineFPGA/Debouncer.vhd" in Library work.Architecture behavioral of Entity debouncer is up to date.Compiling vhdl file "/home/omar/LineFPGA/Bresenhamer.vhd" in Library work.Entity <bresenhamer> compiled.Entity <bresenhamer> (Architecture <behavioral>) compiled.Compiling vhdl file "/home/omar/LineFPGA/SevenSegment.vhd" in Library work.Architecture behavioral of Entity sevensegment is up to date.Compiling vhdl file "/home/omar/LineFPGA/Pointer.vhd" in Library work.Architecture behavioral of Entity pointer is up to date.Compiling vhdl file "/home/omar/LineFPGA/FreqDiv.vhd" in Library work.Architecture behavioral of Entity freqdiv is up to date.Compiling vhdl file "/home/omar/LineFPGA/VGA_Top.vhd" in Library work.Architecture behavioral of Entity vga_top is up to date.=========================================================================* Design Hierarchy Analysis *=========================================================================Analyzing hierarchy for entity <VGA_Top> in library <work> (architecture <behavioral>).Analyzing hierarchy for entity <FrameBuffer> in library <work> (architecture <behavioral>).Analyzing hierarchy for entity <Synchronizer> in library <work> (architecture <behavioral>).Analyzing hierarchy for entity <Debouncer> in library <work> (architecture <behavioral>).Analyzing hierarchy for entity <Bresenhamer> in library <work> (architecture <behavioral>).Analyzing hierarchy for entity <SevenSegment> in library <work> (architecture <behavioral>).Analyzing hierarchy for entity <Pointer> in library <work> (architecture <behavioral>) with generics.initX = "0000000100"initY = "011110000"Analyzing hierarchy for entity <FreqDiv> in library <work> (architecture <behavioral>).Analyzing hierarchy for entity <Pointer> in library <work> (architecture <behavioral>) with generics.initX = "1001111000"initY = "011110000"=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <VGA_Top> in library <work> (Architecture <behavioral>).WARNING:Xst:753 - "/home/omar/LineFPGA/VGA_Top.vhd" line 127: Unconnected output port 'dbg' of component 'Bresenhamer'.Entity <VGA_Top> analyzed. Unit <VGA_Top> generated.Analyzing Entity <FrameBuffer> in library <work> (Architecture <behavioral>).Entity <FrameBuffer> analyzed. Unit <FrameBuffer> generated.Analyzing Entity <Synchronizer> in library <work> (Architecture <behavioral>).Entity <Synchronizer> analyzed. Unit <Synchronizer> generated.Analyzing Entity <Debouncer> in library <work> (Architecture <behavioral>).Entity <Debouncer> analyzed. Unit <Debouncer> generated.Analyzing Entity <Bresenhamer> in library <work> (Architecture <behavioral>).INFO:Xst:2679 - Register <myX2<11>> in unit <Bresenhamer> has a constant value of 0 during circuit operation. The register is replaced by logic.INFO:Xst:2679 - Register <myX2<10>> in unit <Bresenhamer> has a constant value of 0 during circuit operation. The register is replaced by logic.INFO:Xst:2679 - Register <myY2<11>> in unit <Bresenhamer> has a constant value of 0 during circuit operation. The register is replaced by logic.INFO:Xst:2679 - Register <myY2<10>> in unit <Bresenhamer> has a constant value of 0 during circuit operation. The register is replaced by logic.INFO:Xst:2679 - Register <myY2<9>> in unit <Bresenhamer> has a constant value of 0 during circuit operation. The register is replaced by logic.Entity <Bresenhamer> analyzed. Unit <Bresenhamer> generated.Analyzing Entity <SevenSegment> in library <work> (Architecture <behavioral>).Entity <SevenSegment> analyzed. Unit <SevenSegment> generated.Analyzing generic Entity <Pointer.1> in library <work> (Architecture <behavioral>).initX = "0000000100"initY = "011110000"Entity <Pointer.1> analyzed. Unit <Pointer.1> generated.Analyzing Entity <FreqDiv> in library <work> (Architecture <behavioral>).Entity <FreqDiv> analyzed. Unit <FreqDiv> generated.Analyzing generic Entity <Pointer.2> in library <work> (Architecture <behavioral>).initX = "1001111000"initY = "011110000"Entity <Pointer.2> analyzed. Unit <Pointer.2> generated.=========================================================================* HDL Synthesis *=========================================================================Performing bidirectional port resolution...Synthesizing Unit <FrameBuffer>.Related source file is "/home/omar/LineFPGA/FrameBuffer2.vhd".WARNING:Xst:647 - Input <outX<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <outY<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <inX<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <inY<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.Found 32768x3-bit dual-port RAM <Mram_mybuffer> for signal <mybuffer>.Found 3-bit register for signal <temp>.Summary:inferred 1 RAM(s).inferred 3 D-type flip-flop(s).Unit <FrameBuffer> synthesized.Synthesizing Unit <Synchronizer>.Related source file is "/home/omar/LineFPGA/Synchronizer.vhd".Found finite state machine <FSM_0> for signal <YState>.-----------------------------------------------------------------------| States | 4 || Transitions | 43 || Inputs | 5 || Outputs | 8 || Clock | Clk (rising_edge) || Reset | YState$and0000 (positive) || Reset type | synchronous || Reset State | 01 || Power Up State | 00 || Encoding | automatic || Implementation | LUT |-----------------------------------------------------------------------Found finite state machine <FSM_1> for signal <XState>.-----------------------------------------------------------------------| States | 4 || Transitions | 48364 || Inputs | 23 || Outputs | 5 || Clock | Clk (rising_edge) || Clock enable | XState$not0000 (positive) || Power Up State | 00 || Encoding | automatic || Implementation | LUT |-----------------------------------------------------------------------Found 9-bit subtractor for signal <AddressY>.Found 9-bit register for signal <AddressOfY>.Found 9-bit adder for signal <nAddressOfY>.Found 11-bit adder for signal <nX>.Found 11-bit register for signal <X>.Found 21-bit up counter for signal <Y>.Summary:inferred 2 Finite State Machine(s).inferred 1 Counter(s).inferred 20 D-type flip-flop(s).inferred 3 Adder/Subtractor(s).Unit <Synchronizer> synthesized.Synthesizing Unit <Debouncer>.Related source file is "/home/omar/LineFPGA/Debouncer.vhd".Found 2-bit register for signal <ButtonHistory>.Found 24-bit register for signal <Counter>.Found 24-bit addsub for signal <nCounter$mux0000>.Summary:inferred 26 D-type flip-flop(s).inferred 1 Adder/Subtractor(s).Unit <Debouncer> synthesized.Synthesizing Unit <Bresenhamer>.Related source file is "/home/omar/LineFPGA/Bresenhamer.vhd".WARNING:Xst:646 - Signal <minus_dx_plus_dy<10:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <minus_dx_minus_dy<10:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <dx_plus_dy<10:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal <dx_minus_dy<10:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:1780 - Signal <condY1Y2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:1780 - Signal <condX1X2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.Found finite state machine <FSM_2> for signal <State>.-----------------------------------------------------------------------| States | 11 || Transitions | 29 || Inputs | 11 || Outputs | 14 || Clock | Clk (rising_edge) || Power Up State | 0000 || Encoding | automatic || Implementation | LUT |-----------------------------------------------------------------------Found 19-bit up counter for signal <ccounter>.Found 12-bit register for signal <dx>.Found 12-bit adder for signal <dx_minus_dy>.Found 12-bit adder for signal <dx_plus_dy>.Found 12-bit register for signal <dy>.Found 12-bit adder for signal <minus_dx_minus_dy>.Found 12-bit adder for signal <minus_dx_plus_dy>.Found 12-bit register for signal <myX1>.Found 12-bit adder for signal <myX1$add0000> created at line 127.Found 12-bit subtractor for signal <myX1$sub0000> created at line 150.Found 10-bit register for signal <myX2<9:0>>.Found 12-bit register for signal <myY1>.Found 12-bit adder for signal <myY1$add0000> created at line 130.Found 12-bit subtractor for signal <myY1$sub0000> created at line 170.Found 9-bit register for signal <myY2<8:0>>.Found 12-bit subtractor for signal <ndx>.Found 12-bit subtractor for signal <ndy>.Found 12-bit adder for signal <neg_dx>.Found 12-bit adder for signal <neg_dy>.Found 12-bit register for signal <p>.Found 12-bit adder for signal <p0_1>.Found 12-bit adder for signal <p0_2>.Found 12-bit adder for signal <p0_3>.Found 12-bit adder for signal <p0_5>.Found 12-bit adder for signal <p_1$addsub0000> created at line 66.Found 12-bit adder for signal <p_2$addsub0000> created at line 67.Found 12-bit adder for signal <p_3$addsub0000> created at line 68.Found 12-bit adder for signal <p_4$add0000> created at line 69.Found 12-bit adder for signal <p_4$addsub0000> created at line 69.Found 12-bit adder for signal <p_5$addsub0000> created at line 70.Found 12-bit adder for signal <p_6$add0000> created at line 71.Found 12-bit adder for signal <p_6$addsub0000> created at line 71.Found 12-bit adder for signal <p_7$add0000> created at line 72.Found 12-bit adder for signal <p_7$addsub0000> created at line 72.Found 12-bit adder for signal <p_8$add0000> created at line 73.Found 12-bit adder for signal <p_8$addsub0000> created at line 73.Found 12-bit comparator equal for signal <State$cmp_eq0000> created at line 124.Found 12-bit comparator equal for signal <State$cmp_eq0001> created at line 134.Summary:inferred 1 Finite State Machine(s).inferred 1 Counter(s).inferred 79 D-type flip-flop(s).inferred 28 Adder/Subtractor(s).inferred 2 Comparator(s).Unit <Bresenhamer> synthesized.Synthesizing Unit <SevenSegment>.Related source file is "/home/omar/LineFPGA/SevenSegment.vhd".Found 16x7-bit ROM for signal <Segments>.Found 1-of-4 decoder for signal <Enables>.Found 4-bit 4-to-1 multiplexer for signal <Chosen>.Found 17-bit up counter for signal <Counter>.Summary:inferred 1 ROM(s).inferred 1 Counter(s).inferred 4 Multiplexer(s).inferred 1 Decoder(s).Unit <SevenSegment> synthesized.Synthesizing Unit <Pointer_1>.Related source file is "/home/omar/LineFPGA/Pointer.vhd".WARNING:Xst:647 - Input <syncX<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <syncY<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.Found 7-bit comparator equal for signal <Here$cmp_eq0000> created at line 24.Found 6-bit comparator equal for signal <Here$cmp_eq0001> created at line 24.Found 10-bit updown counter for signal <rX>.Found 9-bit updown counter for signal <rY>.Summary:inferred 2 Counter(s).inferred 2 Comparator(s).Unit <Pointer_1> synthesized.Synthesizing Unit <FreqDiv>.Related source file is "/home/omar/LineFPGA/FreqDiv.vhd".Found 20-bit up counter for signal <counter>.Summary:inferred 1 Counter(s).Unit <FreqDiv> synthesized.Synthesizing Unit <Pointer_2>.Related source file is "/home/omar/LineFPGA/Pointer.vhd".WARNING:Xst:647 - Input <syncX<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <syncY<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.Found 7-bit comparator equal for signal <Here$cmp_eq0000> created at line 24.Found 6-bit comparator equal for signal <Here$cmp_eq0001> created at line 24.Found 10-bit updown counter for signal <rX>.Found 9-bit updown counter for signal <rY>.Summary:inferred 2 Counter(s).inferred 2 Comparator(s).Unit <Pointer_2> synthesized.Synthesizing Unit <VGA_Top>.Related source file is "/home/omar/LineFPGA/VGA_Top.vhd".WARNING:Xst:1780 - Signal <GPU_COLOR_TO_BUFFER> is never used or assigned. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:1780 - Signal <GIM> is never used or assigned. This unconnected signal will be trimmed during the optimization process.Unit <VGA_Top> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================HDL Synthesis ReportMacro Statistics# RAMs : 132768x3-bit dual-port RAM : 1# ROMs : 116x7-bit ROM : 1# Adders/Subtractors : 3211-bit adder : 112-bit adder : 2412-bit subtractor : 424-bit addsub : 19-bit adder : 19-bit subtractor : 1# Counters : 810-bit updown counter : 217-bit up counter : 119-bit up counter : 120-bit up counter : 121-bit up counter : 19-bit updown counter : 2# Registers : 511-bit register : 4311-bit register : 112-bit register : 32-bit register : 124-bit register : 13-bit register : 19-bit register : 1# Comparators : 612-bit comparator equal : 26-bit comparator equal : 27-bit comparator equal : 2# Multiplexers : 14-bit 4-to-1 multiplexer : 1# Decoders : 11-of-4 decoder : 1==================================================================================================================================================* Advanced HDL Synthesis *=========================================================================Analyzing FSM <FSM_2> for best encoding.Optimizing FSM <Inst_Bresenhamer/State/FSM> on signal <State[1:11]> with one-hot encoding.----------------------State | Encoding----------------------0000 | 000000000011010 | 000000000100001 | 000000001000010 | 000000010000011 | 000000100000100 | 000001000000101 | 000010000000110 | 000100000000111 | 001000000001000 | 010000000001001 | 10000000000----------------------Analyzing FSM <FSM_1> for best encoding.Optimizing FSM <ins_Synchronizer/XState/FSM> on signal <XState[1:2]> with gray encoding.-------------------State | Encoding-------------------00 | 0001 | 0110 | 1111 | 10-------------------Analyzing FSM <FSM_0> for best encoding.Optimizing FSM <ins_Synchronizer/YState/FSM> on signal <YState[1:2]> with gray encoding.-------------------State | Encoding-------------------00 | 0001 | 0110 | 1111 | 10-------------------Synthesizing (advanced) Unit <FrameBuffer>.INFO:Xst:3226 - The RAM <Mram_mybuffer> will be implemented as a BLOCK RAM, absorbing the following register(s): <temp>-----------------------------------------------------------------------| ram_type | Block | |-----------------------------------------------------------------------| Port A || aspect ratio | 32768-word x 3-bit | || mode | read-first | || clkA | connected to signal <Clk> | rise || weA | connected to signal <BufferWrite> | high || addrA | connected to signal <inY> | || diA | connected to signal <inColor> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------| Port B || aspect ratio | 32768-word x 3-bit | || mode | write-first | || clkB | connected to signal <Clk> | rise || addrB | connected to signal <outY> | || doB | connected to signal <temp> | |-----------------------------------------------------------------------| optimization | speed | |-----------------------------------------------------------------------Unit <FrameBuffer> synthesized (advanced).=========================================================================Advanced HDL Synthesis ReportMacro Statistics# FSMs : 3# RAMs : 132768x3-bit dual-port block RAM : 1# ROMs : 116x7-bit ROM : 1# Adders/Subtractors : 3211-bit adder : 112-bit adder : 2412-bit subtractor : 424-bit addsub : 19-bit adder : 19-bit subtractor : 1# Counters : 810-bit updown counter : 217-bit up counter : 119-bit up counter : 120-bit up counter : 121-bit up counter : 19-bit updown counter : 2# Registers : 125Flip-Flops : 125# Comparators : 612-bit comparator equal : 26-bit comparator equal : 27-bit comparator equal : 2# Multiplexers : 14-bit 4-to-1 multiplexer : 1# Decoders : 11-of-4 decoder : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================INFO:Xst:2146 - In block <VGA_Top>, Counter <Inst_FreqDiv/counter> <Inst_SevenSegment/Counter> are equivalent, XST will keep only <Inst_FreqDiv/counter>.INFO:Xst:2261 - The FF/Latch <dy_10> in Unit <Bresenhamer> is equivalent to the following FF/Latch, which will be removed : <dy_11>Optimizing unit <VGA_Top> ...Optimizing unit <Synchronizer> ...Optimizing unit <Debouncer> ...Optimizing unit <Bresenhamer> ...Optimizing unit <Pointer_1> ...Optimizing unit <Pointer_2> ...WARNING:Xst:2677 - Node <Inst_Bresenhamer/p_0> of sequential type is unconnected in block <VGA_Top>.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block VGA_Top, actual ratio is 28.Final Macro Processing ...=========================================================================Final Register ReportMacro Statistics# Registers : 237Flip-Flops : 237==================================================================================================================================================* Partition Report *=========================================================================Partition Implementation Status-------------------------------No Partitions were found in this design.-------------------------------=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : VGA_Top.ngrTop Level Output File Name : VGA_TopOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : NoDesign Statistics# IOs : 29Cell Usage :# BELS : 1785# GND : 7# INV : 51# LUT1 : 84# LUT2 : 316# LUT2_D : 3# LUT2_L : 23# LUT3 : 117# LUT3_D : 2# LUT3_L : 2# LUT4 : 282# LUT4_D : 18# LUT4_L : 30# MUXCY : 435# MUXF5 : 17# VCC : 1# XORCY : 397# FlipFlops/Latches : 237# FD : 34# FDE : 82# FDR : 24# FDRE : 28# FDS : 69# RAMS : 6# RAMB16 : 6# Clock Buffers : 2# BUFG : 1# BUFGP : 1# IO Buffers : 28# IBUF : 11# OBUF : 17=========================================================================Device utilization summary:---------------------------Selected Device : 3s200ft256-5Number of Slices: 498 out of 1920 25%Number of Slice Flip Flops: 237 out of 3840 6%Number of 4 input LUTs: 928 out of 3840 24%Number of IOs: 29Number of bonded IOBs: 29 out of 173 16%Number of BRAMs: 6 out of 12 50%Number of GCLKs: 2 out of 8 25%---------------------------Partition Resource Summary:---------------------------No Partitions were found in this design.---------------------------=========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORTGENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+Clk | BUFGP | 205 |Inst_FreqDiv/counter_191 | BUFG | 38 |-----------------------------------+------------------------+-------+Asynchronous Control Signals Information:----------------------------------------No asynchronous control signals found in this designTiming Summary:---------------Speed Grade: -5Minimum period: 12.431ns (Maximum Frequency: 80.446MHz)Minimum input arrival time before clock: 7.231nsMaximum output required time after clock: 15.490nsMaximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'Clk'Clock period: 12.431ns (frequency: 80.446MHz)Total number of paths / destination ports: 47319 / 517-------------------------------------------------------------------------Delay: 12.431ns (Levels of Logic = 18)Source: Inst_Bresenhamer/dx_0 (FF)Destination: Inst_Bresenhamer/p_8 (FF)Source Clock: Clk risingDestination Clock: Clk risingData Path: Inst_Bresenhamer/dx_0 to Inst_Bresenhamer/p_8Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDE:C->Q 7 0.626 1.201 Inst_Bresenhamer/dx_0 (Inst_Bresenhamer/dx_0)LUT1:I0->O 1 0.479 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<0>_rt (Inst_Bresenhamer/Madd_neg_dx_cy<0>_rt)MUXCY:S->O 1 0.435 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<0> (Inst_Bresenhamer/Madd_neg_dx_cy<0>)MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<1> (Inst_Bresenhamer/Madd_neg_dx_cy<1>)MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<2> (Inst_Bresenhamer/Madd_neg_dx_cy<2>)MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<3> (Inst_Bresenhamer/Madd_neg_dx_cy<3>)MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<4> (Inst_Bresenhamer/Madd_neg_dx_cy<4>)MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<5> (Inst_Bresenhamer/Madd_neg_dx_cy<5>)MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<6> (Inst_Bresenhamer/Madd_neg_dx_cy<6>)MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<7> (Inst_Bresenhamer/Madd_neg_dx_cy<7>)MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<8> (Inst_Bresenhamer/Madd_neg_dx_cy<8>)MUXCY:CI->O 1 0.056 0.000 Inst_Bresenhamer/Madd_neg_dx_cy<9> (Inst_Bresenhamer/Madd_neg_dx_cy<9>)XORCY:CI->O 7 0.786 1.201 Inst_Bresenhamer/Madd_neg_dx_xor<10> (Inst_Bresenhamer/neg_dx<10>)LUT2:I0->O 1 0.479 0.000 Inst_Bresenhamer/Madd_minus_dx_minus_dy_lut<10> (Inst_Bresenhamer/Madd_minus_dx_minus_dy_lut<10>)MUXCY:S->O 0 0.435 0.000 Inst_Bresenhamer/Madd_minus_dx_minus_dy_cy<10> (Inst_Bresenhamer/Madd_minus_dx_minus_dy_cy<10>)XORCY:CI->O 4 0.786 0.802 Inst_Bresenhamer/Madd_minus_dx_minus_dy_xor<11> (Inst_Bresenhamer/minus_dx_minus_dy<11>)LUT4_D:I3->O 10 0.479 0.987 Inst_Bresenhamer/p_mux0007<10>13 (Inst_Bresenhamer/N34)LUT4:I3->O 1 0.479 0.704 Inst_Bresenhamer/p_mux0007<8>32_SW0 (N145)LUT4:I3->O 1 0.479 0.681 Inst_Bresenhamer/p_mux0007<8>59 (Inst_Bresenhamer/p_mux0007<8>59)FDS:S 0.892 Inst_Bresenhamer/p_8----------------------------------------Total 12.431ns (6.855ns logic, 5.576ns route)(55.1% logic, 44.9% route)=========================================================================Timing constraint: Default period analysis for Clock 'Inst_FreqDiv/counter_191'Clock period: 6.964ns (frequency: 143.593MHz)Total number of paths / destination ports: 1086 / 76-------------------------------------------------------------------------Delay: 6.964ns (Levels of Logic = 4)Source: Inst_Pointer1/rX_5 (FF)Destination: Inst_Pointer1/rX_9 (FF)Source Clock: Inst_FreqDiv/counter_191 risingDestination Clock: Inst_FreqDiv/counter_191 risingData Path: Inst_Pointer1/rX_5 to Inst_Pointer1/rX_9Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDE:C->Q 6 0.626 1.148 Inst_Pointer1/rX_5 (Inst_Pointer1/rX_5)LUT4:I0->O 1 0.479 0.976 Inst_Pointer1/rX_not000272 (Inst_Pointer1/rX_not000272)LUT3:I0->O 1 0.479 0.976 Inst_Pointer1/rX_not000291_SW0 (N224)LUT4:I0->O 1 0.479 0.000 Inst_Pointer1/rX_not0002117_G (N241)MUXF5:I1->O 10 0.314 0.964 Inst_Pointer1/rX_not0002117 (Inst_Pointer1/rX_not0002)FDE:CE 0.524 Inst_Pointer1/rX_0----------------------------------------Total 6.964ns (2.901ns logic, 4.063ns route)(41.7% logic, 58.3% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'Total number of paths / destination ports: 485 / 161-------------------------------------------------------------------------Offset: 7.231ns (Levels of Logic = 27)Source: button (PAD)Destination: Inst_Debouncer/Counter_23 (FF)Destination Clock: Clk risingData Path: button to Inst_Debouncer/Counter_23Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------IBUF:I->O 50 0.715 1.663 button_IBUF (button_IBUF)INV:I->O 1 0.479 0.681 Inst_Debouncer/nCounter_mux00012_INV_0 (Inst_Debouncer/nCounter_mux0001)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<0> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<0>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<1> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<1>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<2> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<2>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<3> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<3>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<4> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<4>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<5> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<5>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<6> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<6>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<7> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<7>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<8> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<8>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<9> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<9>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<10> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<10>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<11> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<11>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<12> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<12>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<13> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<13>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<14> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<14>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<15> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<15>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<16> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<16>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<17> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<17>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<18> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<18>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<19> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<19>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<20> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<20>)MUXCY:CI->O 1 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<21> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<21>)MUXCY:CI->O 0 0.056 0.000 Inst_Debouncer/Maddsub_nCounter_mux0000_cy<22> (Inst_Debouncer/Maddsub_nCounter_mux0000_cy<22>)XORCY:CI->O 1 0.786 0.976 Inst_Debouncer/Maddsub_nCounter_mux0000_xor<23> (Inst_Debouncer/nCounter_mux0000<23>)LUT3:I0->O 1 0.479 0.000 Inst_Debouncer/nCounter<23>11 (Inst_Debouncer/nCounter<23>1)FDS:D 0.176 Inst_Debouncer/Counter_23----------------------------------------Total 7.231ns (3.912ns logic, 3.319ns route)(54.1% logic, 45.9% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_FreqDiv/counter_191'Total number of paths / destination ports: 666 / 76-------------------------------------------------------------------------Offset: 5.177ns (Levels of Logic = 12)Source: MoveLeft (PAD)Destination: Inst_Pointer1/rX_9 (FF)Destination Clock: Inst_FreqDiv/counter_191 risingData Path: MoveLeft to Inst_Pointer1/rX_9Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------IBUF:I->O 26 0.715 1.841 MoveLeft_IBUF (MoveLeft_IBUF)LUT2:I0->O 1 0.479 0.681 Inst_Pointer2/rX_not0003_inv2 (Inst_Pointer1/rX_not000227)MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<0> (Inst_Pointer2/Mcount_rX_cy<0>)MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<1> (Inst_Pointer2/Mcount_rX_cy<1>)MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<2> (Inst_Pointer2/Mcount_rX_cy<2>)MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<3> (Inst_Pointer2/Mcount_rX_cy<3>)MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<4> (Inst_Pointer2/Mcount_rX_cy<4>)MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<5> (Inst_Pointer2/Mcount_rX_cy<5>)MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<6> (Inst_Pointer2/Mcount_rX_cy<6>)MUXCY:CI->O 1 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<7> (Inst_Pointer2/Mcount_rX_cy<7>)MUXCY:CI->O 0 0.056 0.000 Inst_Pointer2/Mcount_rX_cy<8> (Inst_Pointer2/Mcount_rX_cy<8>)XORCY:CI->O 1 0.786 0.000 Inst_Pointer2/Mcount_rX_xor<9> (Inst_Pointer2/Result<9>)FDE:D 0.176 Inst_Pointer2/rX_9----------------------------------------Total 5.177ns (2.656ns logic, 2.522ns route)(51.3% logic, 48.7% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'Total number of paths / destination ports: 654 / 17-------------------------------------------------------------------------Offset: 15.490ns (Levels of Logic = 8)Source: ins_Synchronizer/AddressOfY_1 (FF)Destination: B (PAD)Source Clock: Clk risingData Path: ins_Synchronizer/AddressOfY_1 to BGate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDRE:C->Q 8 0.626 1.216 ins_Synchronizer/AddressOfY_1 (ins_Synchronizer/AddressOfY_1)LUT4:I0->O 5 0.479 1.078 ins_Synchronizer/Madd_nAddressOfY_xor<5>1_SW0 (N111)LUT4:I0->O 8 0.479 1.091 ins_Synchronizer/Msub_AddressY_xor<7>11 (Ady<7>)LUT4:I1->O 1 0.479 0.704 Inst_Pointer2/Here_and0000231_SW0 (N184)LUT4:I3->O 1 0.479 0.976 Inst_Pointer2/Here_and0000231 (Inst_Pointer2/Here_and0000231)LUT4:I0->O 6 0.479 1.023 Inst_Pointer2/Here_and0000244 (p2Region)LUT4:I1->O 1 0.479 0.000 R11 (R1)MUXF5:I1->O 1 0.314 0.681 R1_f5 (R_OBUF)OBUF:I->O 4.909 R_OBUF (R)----------------------------------------Total 15.490ns (8.723ns logic, 6.767ns route)(56.3% logic, 43.7% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_FreqDiv/counter_191'Total number of paths / destination ports: 156 / 3-------------------------------------------------------------------------Offset: 13.773ns (Levels of Logic = 7)Source: Inst_Pointer1/rX_5 (FF)Destination: B (PAD)Source Clock: Inst_FreqDiv/counter_191 risingData Path: Inst_Pointer1/rX_5 to BGate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDE:C->Q 6 0.626 1.023 Inst_Pointer1/rX_5 (Inst_Pointer1/rX_5)LUT2:I1->O 1 0.479 0.976 Inst_Pointer1/Here_and000085 (Inst_Pointer1/Here_and000085)LUT4:I0->O 1 0.479 0.851 Inst_Pointer1/Here_and0000196 (Inst_Pointer1/Here_and0000196)LUT4:I1->O 1 0.479 0.976 Inst_Pointer1/Here_and0000231 (Inst_Pointer1/Here_and0000231)LUT4:I0->O 6 0.479 1.023 Inst_Pointer1/Here_and0000244 (P1Region)LUT4:I1->O 1 0.479 0.000 G11 (G1)MUXF5:I1->O 1 0.314 0.681 G1_f5 (G_OBUF)OBUF:I->O 4.909 G_OBUF (G)----------------------------------------Total 13.773ns (8.244ns logic, 5.529ns route)(59.9% logic, 40.1% route)=========================================================================Total REAL time to Xst completion: 28.00 secsTotal CPU time to Xst completion: 25.69 secs-->Total memory usage is 184200 kilobytesNumber of errors : 0 ( 0 filtered)Number of warnings : 18 ( 0 filtered)Number of infos : 9 ( 0 filtered)