URL
https://opencores.org/ocsvn/graphicsaccelerator/graphicsaccelerator/trunk
Subversion Repositories graphicsaccelerator
[/] [graphicsaccelerator/] [trunk/] [_xmsgs/] [trce.xmsgs] - Rev 2
Compare with Previous | Blame | View Log
<?xml version="1.0" encoding="UTF-8"?><!-- IMPORTANT: This is an internal file that has been generatedby the Xilinx ISE software. Any direct editing orchanges made to this file may result in unpredictablebehavior or data corruption. It is strongly advised thatusers do not edit the contents of this file. --><messages><msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg><msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg><msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg><msg type="info" file="Timing" num="3390" delta="old" >This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</msg><msg type="info" file="Timing" num="3389" delta="old" >This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</msg></messages>
