Subversion Repositories ha1588

# Date: Sat Feb 02 08:52:06 2013

SET addpads = false
SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7vx330t
SET devicefamily = virtex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg1157
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
SET workingdirectory = .\tmp\

# CRC:  2066751