URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
Subversion Repositories ha1588
[/] [ha1588/] [trunk/] [sys/] [altera_qsys/] [system.qsys] - Rev 75
Go to most recent revision | Compare with Previous | Blame | View Log
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
}
element clk_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element ha1588_avl_0
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element mgc_axi4_inline_monitor_0
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
element mgc_axi4_master_0
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element mgc_axi4_slave_0
{
datum _sortIndex
{
value = "3";
type = "int";
}
}
element ha1588_avl_0.reg_interface
{
datum baseAddress
{
value = "65536";
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="5CSEBA5U19A7" />
<parameter name="deviceFamily" value="Cyclone V" />
<parameter name="deviceSpeedGrade" value="7" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="system.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
<parameter name="timeStamp" value="1360206312732" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
<interface
name="ha1588_avl_0_rtc_interface"
internal="ha1588_avl_0.rtc_interface"
type="conduit"
dir="end" />
<interface
name="ha1588_avl_0_tsu_interface"
internal="ha1588_avl_0.tsu_interface"
type="conduit"
dir="end" />
<interface
name="clk_0_clk_in_reset"
internal="clk_0.clk_in_reset"
type="reset"
dir="end" />
<module kind="clock_source" version="12.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module kind="ha1588_avl" version="1.0" enabled="1" name="ha1588_avl_0">
<parameter name="addr_is_in_word" value="true" />
<parameter name="AUTO_CLOCK_CLOCK_RATE" value="50000000" />
</module>
<module
kind="mgc_axi4_master"
version="10.1.3.1"
enabled="1"
name="mgc_axi4_master_0">
<parameter name="AXI4_ADDRESS_WIDTH" value="32" />
<parameter name="AXI4_RDATA_WIDTH" value="32" />
<parameter name="AXI4_WDATA_WIDTH" value="32" />
<parameter name="AXI4_ID_WIDTH" value="8" />
<parameter name="AXI4_USER_WIDTH" value="8" />
<parameter name="AXI4_REGION_MAP_SIZE" value="16" />
<parameter name="index" value="0" />
<parameter name="AUTO_CLOCK_SINK_CLOCK_RATE" value="50000000" />
</module>
<module
kind="mgc_axi4_inline_monitor"
version="10.1.3.1"
enabled="1"
name="mgc_axi4_inline_monitor_0">
<parameter name="AXI4_ADDRESS_WIDTH" value="32" />
<parameter name="AXI4_RDATA_WIDTH" value="32" />
<parameter name="AXI4_WDATA_WIDTH" value="32" />
<parameter name="AXI4_ID_WIDTH" value="8" />
<parameter name="AXI4_USER_WIDTH" value="8" />
<parameter name="AXI4_REGION_MAP_SIZE" value="16" />
<parameter name="index" value="0" />
<parameter name="AUTO_CLOCK_SINK_CLOCK_RATE" value="50000000" />
</module>
<module
kind="mgc_axi4_slave"
version="10.1.3.1"
enabled="1"
name="mgc_axi4_slave_0">
<parameter name="AXI4_ADDRESS_WIDTH" value="16" />
<parameter name="AXI4_RDATA_WIDTH" value="1024" />
<parameter name="AXI4_WDATA_WIDTH" value="1024" />
<parameter name="AXI4_ID_WIDTH" value="18" />
<parameter name="AXI4_USER_WIDTH" value="8" />
<parameter name="AXI4_REGION_MAP_SIZE" value="16" />
<parameter name="index" value="0" />
<parameter name="AUTO_CLOCK_SINK_CLOCK_RATE" value="50000000" />
</module>
<connection
kind="clock"
version="12.1"
start="clk_0.clk"
end="ha1588_avl_0.clock" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="ha1588_avl_0.clock_reset" />
<connection
kind="avalon"
version="12.1"
start="mgc_axi4_master_0.altera_axi4_master"
end="ha1588_avl_0.reg_interface">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010000" />
</connection>
<connection
kind="clock"
version="12.1"
start="clk_0.clk"
end="mgc_axi4_master_0.clock_sink" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="mgc_axi4_master_0.reset_sink" />
<connection
kind="clock"
version="12.1"
start="clk_0.clk"
end="mgc_axi4_inline_monitor_0.clock_sink" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="mgc_axi4_inline_monitor_0.reset_sink" />
<connection
kind="avalon"
version="12.1"
start="mgc_axi4_inline_monitor_0.altera_axi4_master"
end="ha1588_avl_0.reg_interface">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010000" />
</connection>
<connection
kind="clock"
version="12.1"
start="clk_0.clk"
end="mgc_axi4_slave_0.clock_sink" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="mgc_axi4_slave_0.reset_sink" />
<connection
kind="avalon"
version="12.1"
start="mgc_axi4_master_0.altera_axi4_master"
end="mgc_axi4_slave_0.altera_axi4_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
</connection>
</system>
Go to most recent revision | Compare with Previous | Blame | View Log