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[/] [hicovec/] [trunk/] [assembler/] [cputest.txt] - Rev 12
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; ************************************************************************; * CPU validation program *; ************************************************************************; * Executes all possible commands of the target cpu to be sure that it *; * works properly. *; * *; * If an error occurs, the processor will run into a halt command. *; * Otherwise it will continue execution to the finish symbol and loop *; * there infinety *; * *; ************************************************************************; * Author: Harald Manske, haraldmanske@gmx.de *; * Version: 1.0 *; * Plattform: HiCoVec (highly configurable vector processor) *; ************************************************************************; configuration of the programEQU n 8 ;requires n >= 4EQU k 20 ;requires k = 16EQU use_shuffle 0 ;requires shuffle unitEQU use_mul 0 ;requires both, scalar and vector multiplicateEQU use_vmolr 0 ;requires vmol and vmor commands (32 bit width)JMP 0+STARTHALT;test dataORG $10DATA_V: DC $B2D463BC ; vector input data (max k=32)DATA_V2: DC $AA67Df42DC $A3B78EF3DC $4E6AC974DC $8FEE432EDC $FF3AB876DC $43B57621DC $8E6AC974 ;8DC $7FF3ACD3DC $921BC4D1DC $637DCF67DC $7897AABDDC $973EE234DC $005C6E39DC $A1BC7A35DC $7FF8334E ;16DC $A3486CDFDC $94CA193BDC $445E97C1DC $8836D35EDC $A9B2C45FDC $97A36BFFDC $79835987DC $DCBEDFEADC $975CC213DC $39DA322BDC $8411DEA9DC $FFFFFFFFDC $129DE3AFDC $7881D74ADC $AA8D35A8DC $5247877DV_RES: ORG $30 ; vector result data (max k=32)ORG $50MASK_HW: DC $FFFF0000 ; mask to get only high wordCMP_VAL: DC $ABCD ; value to compare with immediateCMP_VAL2: DC $FEDC ; value to compare with immediateDATA_A: DC $A3BF74E5 ; operand ADATA_B: DC $03C7A483 ; operand BDATA_FF: DC $FFFFFFFF ; operand FFSTORE_DEST: DC $0 ; destination for store command;resultsAND_RES: DC $3872481 ; result: A and BOR_RES: DC $A3FFF4E7 ; result: A or BXOR_RES: DC $A078D066 ; result: A xor BADD_RES: DC $A7871968 ; result: A + BSUB_RES: DC $9FF7D062 ; result: A - BINC_RES: DC $A3BF74E6 ; result: A + 1DEC_RES: DC $A3BF74E4 ; result: A - 1LSL_RES: DC $477EE9CA ; result: lsl ALSR_RES: DC $51DFBA72 ; result: lsr AMUL_RES: DC $4B1E852F ; result A * B (16bit * 16bit)ROL_RES: DC $477EE9CA ; result: rol A, carry not setROL_RES_C: DC $477EE9CB ; result: rol A, carry setROR_RES: DC $51DFBA72ROR_RES_C: DC $D1DFBA72 ; result: ror A, carry setRES_VSHUF_8L: DC $8EF3AA67 ; result: shuffle vwidth=00 low wordRES_VSHUF_8H: DC $DF42B2D4 ; result: shuffle vwidth=00 high word;program startSTART: NOP;test flag commands and conditional jumpsTEST_ZERO: SEZJZ 0+TEST_NOTZEROHALTTEST_NOTZERO: CLZJZ 0+ERR_SCALARJNZ 0+TEST_CARRYHALTTEST_CARRY: SECJC 0+TEST_NOTCARRYHALTTEST_NOTCARRY: CLCJC 0+ERR_SCALARJNC 0+TEST_FLAGSHALTTEST_FLAGS: SUB 0,0,1JZ 0+ERR_SCALARJNC 0+ERR_SCALARJNZ 0+TEST_FLAGS2HALTTEST_FLAGS2: ADD 0,0,0JC 0+ERR_SCALARJZ 0+TEST_LDHALT;test load operationTEST_LD: LD A,0+CMP_VALJZ 0+ERR_SCALARSUB X,A,$ABCDJC 0+ERR_SCALARJZ 0+TEST_LD2HALTTEST_LD2: OR Y,0,CMP_VALOR X,0,1LD Y,Y+XSUB 0,Y,$FEDCJNZ 0+ERR_SCALARJZ 0+TEST_STOREHALT;test store operationTEST_STORE: LD X,0+DATA_ALD Y,0+DATA_BADD A,X,YST 0+STORE_DEST,ALD X,0+ADD_RESLD Y,0+STORE_DESTSUB 0,X,YJZ 0+TEST_STORE2HALTTEST_STORE2: OR A,0,$1234OR X,0,1OR Y,0,STORE_DESTDEC Y,YST X+Y,AOR X,0,0LD X,0+STORE_DESTSUB Y,X,$1234JNZ 0+ERR_SCALAR;test arithmetic and logic operationsTEST_ADD: LD X,0+DATA_ALD Y,0+DATA_BADD A,X,YJC 0+ERR_SCALARJZ 0+ERR_SCALARLD Y,0+ADD_RESSUB 0,A,YJNZ 0+ERR_SCALARJC 0+ERR_SCALARLD X, 0+DATA_FFADD A,X,2JNC 0+ERR_SCALARJZ 0+ERR_SCALARSUB 0,A,1JZ 0+TEST_ADCHALTTEST_ADC: LD A,0+DATA_ALD X,0+DATA_BCLCADC Y,A,XJZ 0+ERR_SCALARJC 0+ERR_SCALARLD A,0+ADD_RESSUB 0,A,YJNZ 0+ERR_SCALARLD Y,0+DATA_ALD X,0+DATA_BSECADC A,X,YJZ 0+ERR_SCALARJC 0+ERR_SCALARSUB A,A,1LD Y,0+ADD_RESSUB 0,A,YJNZ 0+ERR_SCALARJNC 0+TEST_SUBHALTTEST_SUB: LD X,0+DATA_ALD Y,0+DATA_BSUB A,X,YJC 0+ERR_SCALARLD X,0+SUB_RESSUB 0,A,XJNZ 0+ERR_SCALARJC 0+ERR_SCALARLD X,0+DATA_ASUB A,Y,XJNC 0+ERR_SCALARJNZ 0+TEST_SBCHALTTEST_SBC: LD A,0+DATA_ALD Y,0+DATA_BCLCSUB X,A,YSBC A,A,YJZ 0+ERR_SCALARJC 0+ERR_SCALARSUB 0,X,AJNZ 0+ERR_SCALARJC 0+ERR_SCALARLD A,0+DATA_ASECSBC A,A,YJZ 0+ERR_SCALARJC 0+ERR_SCALARSUB X,X,1SUB 0,A,XJC 0+ERR_SCALARJZ 0+TEST_INCHALTTEST_INC: LD A,0+DATA_AINC A,ALD X,0+INC_RESLD Y,0+DATA_AADD Y,Y,1SUB 0,A,XJNZ 0+ERR_SCALARSUB 0,A,YJNZ 0+ERR_SCALARLD A,0+DATA_FFINC A,AJNC 0+ERR_SCALARJZ 0+TEST_DECHALTTEST_DEC: OR A,0,0DEC A,AJNC 0+ERR_SCALARJZ 0+ERR_SCALARLD X,0+DATA_FFSUB 0,A,XJNZ 0+ERR_SCALARJC 0+ERR_SCALARLD A,0+DATA_ADEC A,ALD Y,0+DEC_RESSUB 0,A,YJC 0+ERR_SCALARJZ 0+TEST_ANDHALTTEST_AND: LD A,0+DATA_ALD X,0+DATA_BAND Y,A,XLD A,0+AND_RESSUB 0,Y,AJC 0+ERR_SCALARJNZ 0+ERR_SCALARLD A,0+DATA_FFAND X,Y,ASUB 0,Y,XJNZ 0+ERR_SCALAROR Y,0,$3456AND Y,Y,0JZ 0+TEST_ORHALTTEST_OR: LD X,0+DATA_ALD Y,0+DATA_BOR A,X,YLD X,0+OR_RESJZ 0+ERR_SCALARSUB 0,A,XJNZ 0+ERR_SCALARJC 0+ERR_SCALAROR A,A,$FFAND A,A,$FFSUB 0,A,$FFJC 0+ERR_SCALARJZ 0+TEST_XORHALTTEST_XOR: LD X,0+DATA_ALD Y,0+DATA_BXOR A,X,YLD X,0+XOR_RESSUB 0,A,XJC 0+ERR_SCALARJNZ 0+ERR_SCALARLD Y,0+ADD_RESXOR A,A,YSUB 0,A,XJZ 0+ERR_SCALARXOR A,A,YSUB 0,A,XJZ 0+TEST_LSLHALTTEST_LSL: LD A,0+DATA_ALSL A,AJNC 0+ERR_SCALARLD X,0+LSL_RESSUB 0,A,XJC 0+ERR_SCALARJZ 0+TEST_LSRHALTTEST_LSR: LD A,0+DATA_ALSR A,AJNC 0+ERR_SCALARLD X,0+LSR_RESSUB 0,X,AJC 0+ERR_SCALARJZ 0+TEST_ROLHALTTEST_ROL: CLCLD Y,0+DATA_AROL A,YJNC 0+ERR_SCALARLD X,0+ROL_RESSUB 0,A,XJC 0+ERR_SCALARJNZ 0+ERR_SCALARSECLD Y,0+DATA_AROL A,YJNC 0+ERR_SCALARLD X,0+ROL_RES_CSUB 0,A,XJC 0+ERR_SCALARJZ 0+TEST_RORHALTTEST_ROR: CLCLD Y,0+DATA_AROR A,YJNC 0+ERR_SCALARLD X,0+ROR_RESSUB 0,A,XJC 0+ERR_SCALARJNZ 0+ERR_SCALARSECLD A,0+DATA_AROR A,AJNC 0+ERR_SCALARLD X,0+ROR_RES_CSUB 0,A,XJC 0+ERR_SCALARJZ 0+TEST_JALHALTTEST_JAL: JAL A,0+TEST_JAL2HALTTEST_JAL2: SUB 0,A,TEST_JALJNZ 0+ERR_SCALARJZ 0+TEST_MULTEST_MUL: OR A,0,use_mulJZ 0+NO_MULLD X,0+DATA_ALD Y,0+DATA_BMUL A,X,YJC 0+ERR_SCALARJZ 0+ERR_SCALARLD Y,0+MUL_RESSUB 0,A,YJNZ 0+ERR_SCALARJC 0+ERR_SCALARNO_MUL: JMP 0+TEST_VLD_ST;test cooperative commandsTEST_VLD_ST: OR A,0,0OR Y,0,0VLD_ST_INIT: ST 0+V_RES,A ;init with 0INC Y,YSUB 0,Y,kJNZ 0+VLD_ST_INITOR A,0,DATA_V ;loadVLD R0,0+AOR A,0,V_RESVST 0+A,R0 ;storeOR Y,0,0VLD_ST_LOOP: LD A,Y+V_RES ;checkLD X,Y+DATA_VSUB 0,A,XJNZ 0+ERR_COOPINC Y,YSUB 0,Y,kJNZ 0+VLD_ST_LOOPJMP 0+TEST_MOVHALTTEST_MOV: OR A,0,0MOV_LOOP: LD Y,A+DATA_VMOV R1(A),Y ;scalar => vectorINC A,ASUB 0,A,kJNZ 0+MOV_LOOPOR A,0,0OR X,0,0MOV_LOOP2: MOV X,R1(A) ;vector => scalarLD Y,A+DATA_VSUB 0,Y,XJNZ 0+ERR_COOPINC A,ASUB 0,A,kJNZ 0+MOV_LOOP2JZ 0+TEST_VMOVHALT;test vector commandsTEST_VMOV: VMOV R0,R1VMOV R<2>,R0VMOV R3,R<2>OR A,0,0VMOV_LOOP: LD Y,A+DATA_VMOV X,R0(A)SUB 0,Y,XJNZ 0+ERR_VECTORMOV X,R2(A)SUB 0,Y,XJNZ 0+ERR_VECTORMOV X,R3(A)SUB 0,Y,XJNZ 0+ERR_VECTORINC A,ASUB 0,A,kJNZ 0+VMOV_LOOPTEST_MOVA: LD A,0+DATA_AMOVA R0,AOR X,0,V_RESVST 0+X,R0OR X,0,0MOVA_LOOP: LD Y,X+V_RESSUB 0,Y,AJNZ 0+ERR_COOPINC X,XSUB 0,X,kJNZ 0+MOVA_LOOP;test vector alu commandsOR A,0,DATA_VVLD R0,0+AOR A,0,DATA_V2VLD R1,0+ATEST_VAND: VAND.DW R2,R0,R1OR A,0,V_RESVST 0+A,R2OR A,0,0VAND_LOOP: LD X,A+DATA_VLD Y,A+DATA_V2AND X,X,YLD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUINC A,ASUB 0,A,kJNZ 0+VAND_LOOPTEST_VOR: VOR.DW R2,R0,R1OR A,0,V_RESVST 0+A,R2OR A,0,0VOR_LOOP: LD X,A+DATA_VLD Y,A+DATA_V2OR X,X,YLD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUINC A,ASUB 0,A,kJNZ 0+VOR_LOOPTEST_VXOR: VXOR.DW R2,R0,R1OR A,0,V_RESVST 0+A,R2OR A,0,0VXOR_LOOP: LD X,A+DATA_VLD Y,A+DATA_V2XOR X,X,YLD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUINC A,ASUB 0,A,kJNZ 0+VXOR_LOOPTEST_VADD: VADD.DW R2,R0,R1OR A,0,V_RESVST 0+A,R2;32 bitOR A,0,0VADD_LOOP_DW: LD X,A+DATA_VLD Y,A+DATA_V2ADD X,X,YLD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUINC A,ASUB 0,A,kJNZ 0+VADD_LOOP_DW;64 bitVADD.QW R2,R0,R1OR A,0,V_RESVST 0+A,R2OR A,0,0VADD_LOOP_QW: ST 0+AKKU,A ;reset carryOR A,0,0ST 0+CARRY,ALD A,0+AKKULD X,A+DATA_VLD Y,A+DATA_V2ADD X,X,YJNC 0+VADD_QW_NC ; save carryST 0+AKKU,AOR A,0,1ST 0+CARRY,ALD A,0+AKKUVADD_QW_NC: LD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUINC A,ALD X,A+DATA_VLD Y,A+DATA_V2ADD X,X,YLD Y,0+CARRYADD X,X,YLD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUINC A,ASUB 0,A,kJNZ 0+VADD_LOOP_QW;16bitVADD.W R2,R0,R1OR A,0,V_RESVST 0+A,R2OR A,0,0VADD_LOOP_W: LD X,A+DATA_V ;low wordLD Y,A+DATA_V2ADD X,X,YLD Y,A+V_RESAND X,X,$FFFFAND Y,Y,$FFFFSUB 0,X,YJNZ 0+ERR_VALULD X,A+DATA_V ;high wordLD Y,0+MASK_HWAND X,X,YLD Y,A+DATA_V2ST 0+AKKU,ALD A,0+MASK_HWAND Y,Y,ALD A,0+AKKUADD X,X,YLD Y,A+V_RESST 0+AKKU,AOR A,0,0VADD_LOOP_W2: LSR X,XLSR Y,YINC A,ASUB 0,A,16JNZ 0+VADD_LOOP_W2LD A,0+AKKUAND X,X,$FFFFAND Y,Y,$FFFFSUB 0,X,YJNZ 0+ERR_VALUINC A,ASUB 0,A,kJNZ 0+VADD_LOOP_W;8 bitVADD.B R2,R0,R1OR A,0,V_RESVST 0+A,R2OR A,0,0VADD_LOOP_B: OR X,A,0ST 0+AKKU,ALD A,X+DATA_VST 0+A_REG,ALD A,X+DATA_V2ST 0+B_REG,ALD A,X+V_RESST 0+RES_REG,AOR A,0,0VADD_LOOP_B2: ST 0+I,ALD X,0+A_REGLD Y,0+B_REGLD A,0+RES_REGADD X,X,YAND X,X,$FFAND A,A,$FFSUB 0,X,AJNZ 0+ERR_VALULD X,0+A_REGLD Y,0+B_REGLD A,0+RES_REGLSR X,XLSR Y,YLSR A,ALSR X,XLSR Y,YLSR A,ALSR X,XLSR Y,YLSR A,ALSR X,XLSR Y,YLSR A,ALSR X,XLSR Y,YLSR A,ALSR X,XLSR Y,YLSR A,ALSR X,XLSR Y,YLSR A,ALSR X,XLSR Y,YLSR A,AST 0+RES_REG,AOR A,0,XST 0+A_REG,AOR A,0,YST 0+B_REG,ALD A,0+IINC A,ASUB 0,A,4JNZ 0+VADD_LOOP_B2LD A,0+AKKUINC A,ASUB 0,A,kJNZ 0+VADD_LOOP_BTEST_VSUB: VSUB.DW R2,R0,R1OR A,0,V_RESVST 0+A,R2;32 bitOR A,0,0VSUB_LOOP_DW: LD X,A+DATA_VLD Y,A+DATA_V2SUB X,X,YLD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUINC A,ASUB 0,A,kJNZ 0+VSUB_LOOP_DW;64 bitVSUB.QW R2,R0,R1OR A,0,V_RESVST 0+A,R2OR A,0,0VSUB_LOOP_QW: ST 0+AKKU,A ;reset carryOR A,0,0ST 0+CARRY,ALD A,0+AKKULD X,A+DATA_VLD Y,A+DATA_V2SUB X,X,YJNC 0+VSUB_QW_NC ; save carryST 0+AKKU,AOR A,0,1ST 0+CARRY,ALD A,0+AKKUVSUB_QW_NC: LD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUINC A,ALD X,A+DATA_VLD Y,A+DATA_V2SUB X,X,YLD Y,0+CARRYSUB X,X,YLD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUINC A,ASUB 0,A,kJNZ 0+VSUB_LOOP_QW;16bitVSUB.W R2,R0,R1OR A,0,V_RESVST 0+A,R2OR A,0,0VSUB_LOOP_W: LD X,A+DATA_V ;low wordLD Y,A+DATA_V2SUB X,X,YLD Y,A+V_RESAND X,X,$FFFFAND Y,Y,$FFFFSUB 0,X,YJNZ 0+ERR_VALULD X,A+DATA_V ;high wordLD Y,0+MASK_HWAND X,X,YLD Y,A+DATA_V2ST 0+AKKU,ALD A,0+MASK_HWAND Y,Y,ALD A,0+AKKUSUB X,X,YLD Y,A+V_RESST 0+AKKU,AOR A,0,0VSUB_LOOP_W2: LSR X,XLSR Y,YINC A,ASUB 0,A,16JNZ 0+VSUB_LOOP_W2LD A,0+AKKUAND X,X,$FFFFAND Y,Y,$FFFFSUB 0,X,YJNZ 0+ERR_VALUINC A,ASUB 0,A,kJNZ 0+VSUB_LOOP_W;8 bitVSUB.B R2,R0,R1OR A,0,V_RESVST 0+A,R2OR A,0,0VSUB_LOOP_B: OR X,A,0ST 0+AKKU,ALD A,X+DATA_VST 0+A_REG,ALD A,X+DATA_V2ST 0+B_REG,ALD A,X+V_RESST 0+RES_REG,AOR A,0,0VSUB_LOOP_B2: ST 0+I,ALD X,0+A_REGLD Y,0+B_REGLD A,0+RES_REGSUB X,X,YAND X,X,$FFAND A,A,$FFSUB 0,X,AJNZ 0+ERR_VALULD X,0+A_REGLD Y,0+B_REGLD A,0+RES_REGLSR X,XLSR Y,YLSR A,ALSR X,XLSR Y,YLSR A,ALSR X,XLSR Y,YLSR A,ALSR X,XLSR Y,YLSR A,ALSR X,XLSR Y,YLSR A,ALSR X,XLSR Y,YLSR A,ALSR X,XLSR Y,YLSR A,ALSR X,XLSR Y,YLSR A,AST 0+RES_REG,AOR A,0,XST 0+A_REG,AOR A,0,YST 0+B_REG,ALD A,0+IINC A,ASUB 0,A,4JNZ 0+VSUB_LOOP_B2LD A,0+AKKUINC A,ASUB 0,A,kJNZ 0+VSUB_LOOP_BTEST_VLSL: VLSL.DW R2,R0OR A,0,V_RESVST 0+A,R2;32 bitOR A,0,0VLSL_LOOP_DW: LD X,A+DATA_VLSL X,XLD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUINC A,ASUB 0,A,kJNZ 0+VLSL_LOOP_DW;64 bitVLSL.QW R2,R0OR A,0,V_RESVST 0+A,R2OR A,0,0VLSL_LOOP_QW: ST 0+AKKU,A ;reset carryOR A,0,0ST 0+CARRY,ALD A,0+AKKULD X,A+DATA_VLSL X,XJNC 0+VLSL_QW_NC ; save carryST 0+AKKU,AOR A,0,1ST 0+CARRY,ALD A,0+AKKUVLSL_QW_NC: LD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUINC A,ALD X,A+DATA_VLD Y,0+CARRYLSR Y,YROL X,XLD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUINC A,ASUB 0,A,kJNZ 0+VLSL_LOOP_QW;16bitVLSL.W R2,R0OR A,0,V_RESVST 0+A,R2OR A,0,0VLSL_LOOP_W: LD X,A+DATA_V ;low wordLSL X,XLD Y,A+V_RESAND X,X,$FFFFAND Y,Y,$FFFFSUB 0,X,YJNZ 0+ERR_VALULD X,A+DATA_V ;high wordLD Y,0+MASK_HWAND X,X,YLSL X,XLD Y,A+V_RESST 0+AKKU,AOR A,0,0VLSL_LOOP_W2: LSR X,XLSR Y,YINC A,ASUB 0,A,16JNZ 0+VLSL_LOOP_W2LD A,0+AKKUAND X,X,$FFFFAND Y,Y,$FFFFSUB 0,X,YJNZ 0+ERR_VALUINC A,ASUB 0,A,kJNZ 0+VLSL_LOOP_W;8 bitVLSL.B R2,R0OR A,0,V_RESVST 0+A,R2OR A,0,0VLSL_LOOP_B: OR X,A,0ST 0+AKKU,ALD A,X+DATA_VST 0+A_REG,ALD A,X+V_RESST 0+RES_REG,AOR A,0,0VLSL_LOOP_B2: ST 0+I,ALD X,0+A_REGLD A,0+RES_REGLSL X,XAND X,X,$FFAND A,A,$FFSUB 0,X,AJNZ 0+ERR_VALULD X,0+A_REGLD A,0+RES_REGLSR X,XLSR A,ALSR X,XLSR A,ALSR X,XLSR A,ALSR X,XLSR A,ALSR X,XLSR A,ALSR X,XLSR A,ALSR X,XLSR A,ALSR X,XLSR A,AST 0+RES_REG,AOR A,0,XST 0+A_REG,ALD A,0+IINC A,ASUB 0,A,4JNZ 0+VLSL_LOOP_B2LD A,0+AKKUINC A,ASUB 0,A,kJNZ 0+VLSL_LOOP_BTEST_VLSR: VLSR.DW R2,R0OR A,0,V_RESVST 0+A,R2;32 bitOR A,0,0VLSR_LOOP_DW: LD X,A+DATA_VLSR X,XLD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUINC A,ASUB 0,A,kJNZ 0+VLSR_LOOP_DW;64 bitVLSR.QW R2,R0OR A,0,V_RESVST 0+A,R2OR A,0,0VLSR_LOOP_QW: ST 0+AKKU,A ;reset carryOR A,0,0ST 0+CARRY,ALD A,0+AKKUINC A,ALD X,A+DATA_VLSR X,XJNC 0+VLSR_QW_NC ; save carryST 0+AKKU,AOR A,0,1ST 0+CARRY,ALD A,0+AKKUVLSR_QW_NC: LD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUDEC A,ALD X,A+DATA_VLD Y,0+CARRYLSR Y,YROR X,XLD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUINC A,AINC A,ASUB 0,A,kJNZ 0+VLSR_LOOP_QW;16bitVLSR.W R2,R0OR A,0,V_RESVST 0+A,R2OR A,0,0VLSR_LOOP_W: LD X,A+DATA_V ;low wordAND X,X,$FFFFLSR X,XLD Y,A+V_RESAND Y,Y,$FFFFSUB 0,X,YJNZ 0+ERR_VALULD X,A+DATA_V ;high wordLD Y,0+MASK_HWAND X,X,YLSR X,XLD Y,A+V_RESST 0+AKKU,AOR A,0,0VLSR_LOOP_W2: LSR X,XLSR Y,YINC A,ASUB 0,A,16JNZ 0+VLSR_LOOP_W2LD A,0+AKKUAND X,X,$FFFFAND Y,Y,$FFFFSUB 0,X,YJNZ 0+ERR_VALUINC A,ASUB 0,A,kJNZ 0+VLSR_LOOP_W;8 bitVLSR.B R2,R0OR A,0,V_RESVST 0+A,R2OR A,0,0VLSR_LOOP_B: OR X,A,0ST 0+AKKU,ALD A,X+DATA_VST 0+A_REG,ALD A,X+V_RESST 0+RES_REG,AOR A,0,0VLSR_LOOP_B2: ST 0+I,ALD X,0+A_REGLD A,0+RES_REGAND X,X,$FFLSR X,XAND A,A,$FFSUB 0,X,AJNZ 0+ERR_VALULD X,0+A_REGLD A,0+RES_REGLSR X,XLSR A,ALSR X,XLSR A,ALSR X,XLSR A,ALSR X,XLSR A,ALSR X,XLSR A,ALSR X,XLSR A,ALSR X,XLSR A,ALSR X,XLSR A,AST 0+RES_REG,AOR A,0,XST 0+A_REG,ALD A,0+IINC A,ASUB 0,A,4JNZ 0+VLSR_LOOP_B2LD A,0+AKKUINC A,ASUB 0,A,kJNZ 0+VLSR_LOOP_B;vector and scalar commands simultaneousTEST_SIMUL: OR A,0,DATA_VVLD R0,0+AOR A,0,DATA_V2VLD R1,0+ALD X,0+DATA_ALD Y,0+DATA_BOR A,0,0VADD.DW R2,R0,R1VADD.DW R3,R0,R1 | ADD A,X,YVSUB.DW R3,R3,R2OR Y,0,V_RESVST 0+Y,R3LD X,0+ADD_RESSUB 0,X,AJNZ 0+ERR_SIMULOR A,0,0SIMUL_LOOP1: LD X,A+V_RESJNZ 0+ERR_SIMULINC A,ASUB 0,A,kJNZ 0+SIMUL_LOOP1LD X,0+DATA_ALD Y,0+DATA_BOR A,0,0VXOR.DW R2,R0,R1VXOR.DW R3,R0,R1 | SUB A,X,YVSUB.DW R3,R3,R2OR Y,0,V_RESVST 0+Y,R3LD X,0+SUB_RESSUB 0,X,AJNZ 0+ERR_SIMULOR A,0,0SIMUL_LOOP2: LD X,A+V_RESJNZ 0+ERR_SIMULINC A,ASUB 0,A,kJNZ 0+SIMUL_LOOP2LD X,0+DATA_ALD Y,0+DATA_BOR A,0,0VMOV R2,R0VMOV R3,R0 | AND A,X,YVSUB.DW R3,R3,R2OR Y,0,V_RESVST 0+Y,R3LD X,0+AND_RESSUB 0,X,AJNZ 0+ERR_SIMULOR A,0,0SIMUL_LOOP3: LD X,A+V_RESJNZ 0+ERR_SIMULINC A,ASUB 0,A,kJNZ 0+SIMUL_LOOP3TEST_VSHUF: OR A,0,use_shuffleJZ 0+NO_SHUFFLEOR A,0,DATA_VVLD R0,0+AOR A,0,DATA_V2VLD R1,0+ATEST_VSHUF1: VSHUF R2,R0,R1,00101000011011 ;vwidth + ssss + vnOR A,0,V_RESVST 0+A,R2LD X,A+0LD A,0+RES_VSHUF_8LSUB 0,A,XJNZ 0+ERR_VSHUFOR A,0,V_RESLD Y,A+1LD A,0+RES_VSHUF_8HSUB 0,A,YJNZ 0+ERR_VSHUFTEST_VSHUF2: VSHUF R2,R0,R1,01110010110001 ;vwidth + ssss + vnOR A,0,V_RESVST 0+A,R2OR A,0,0LD X,A+V_RESOR A,0,1LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,1LD X,A+V_RESOR A,0,0LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,2LD X,A+V_RESOR A,0,4LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,3LD X,A+V_RESOR A,0,3LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFTEST_VSHUF3: VSHUF R2,R0,R1,10001101110010 ;vwidth + ssss + vnOR A,0,V_RESVST 0+A,R2OR A,0,0LD X,A+V_RESOR A,0,5LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,1LD X,A+V_RESOR A,0,6LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,2LD X,A+V_RESOR A,0,1LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,3LD X,A+V_RESOR A,0,2LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,4LD X,A+V_RESOR A,0,6LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,5LD X,A+V_RESOR A,0,7LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,6LD X,A+V_RESOR A,0,2LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,7LD X,A+V_RESOR A,0,3LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFTEST_VSHUF4: VSHUF R2,R0,R1,11010100100111 ;vwidth + ssss + vnOR A,0,V_RESVST 0+A,R2OR A,0,0LD X,A+V_RESOR A,0,13LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,1LD X,A+V_RESOR A,0,14LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,2LD X,A+V_RESOR A,0,15LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,3LD X,A+V_RESOR A,0,16LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUF;--------------OR A,0,4LD X,A+V_RESOR A,0,4LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,5LD X,A+V_RESOR A,0,5LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,6LD X,A+V_RESOR A,0,6LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,7LD X,A+V_RESOR A,0,7LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUF;--------------OR A,0,8LD X,A+V_RESOR A,0,9LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,9LD X,A+V_RESOR A,0,10LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,10LD X,A+V_RESOR A,0,11LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,11LD X,A+V_RESOR A,0,12LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUF;--------------OR A,0,12LD X,A+V_RESOR A,0,0LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,13LD X,A+V_RESOR A,0,1LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,14LD X,A+V_RESOR A,0,2LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFOR A,0,15LD X,A+V_RESOR A,0,3LD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VSHUFNO_SHUFFLE: NOPTEST_VMUL: OR A,0,use_mulJZ 0+NO_VMUL;16 bitVMUL.W R2,R0,R1OR A,0,V_RESVST 0+A,R2OR A,0,0VMUL_LOOP_W: LD X,A+DATA_VLD Y,A+DATA_V2MUL X,X,YLD Y,A+V_RESSUB 0,X,YJNZ 0+ERR_VALUINC A,ASUB 0,A,kJNZ 0+VMUL_LOOP_W;8 bitVMUL.B R2,R0,R1OR A,0,V_RESVST 0+A,R2OR A,0,0VMUL_LOOP_B: LD X,A+DATA_V ;high wordLD Y,A+DATA_V2AND X,X,$FFAND Y,Y,$FFMUL X,X,YLD Y,A+V_RESAND Y,Y,$FFFFSUB 0,X,YJNZ 0+ERR_VALULD X,A+DATA_V ;low wordLD Y,A+DATA_V2ST 0+AKKU,AOR A,0,0VMUL_LOOP_B2: LSR X,XLSR Y,YINC A,ASUB 0,A,16JNZ 0+VMUL_LOOP_B2AND X,X,$FFAND Y,Y,$FFMUL X,X,YLD A,0+AKKULD Y,A+V_RESOR A,0,0VMUL_LOOP_B3: LSR Y,YINC A,ASUB 0,A,16JNZ 0+VMUL_LOOP_B3SUB 0,X,YJNZ 0+ERR_VALULD A,0+AKKUINC A,ASUB 0,A,kJNZ 0+VMUL_LOOP_BNO_VMUL: NOPTEST_VMOLR: OR A,0,use_mulJZ 0+NO_VMOLROR A,0,DATA_VVLD R0,0+AOR A,0,DATA_V2VLD R1,0+AVMOL R2,R0OR A,0,V_RESVST 0+A,R2OR A,0,0VMOL_LOOP: LD X,A+V_RESLD Y,A+DATA_V2SUB 0,X,YJNZ 0+ERR_VMOLRSUB 0,A,kJNZ 0+VMOL_LOOPVMOR R2,R1OR A,0,V_RESVST 0+A,R2OR A,0,0VMOR_LOOP: LD X,A+V_RESLD Y,A+DATA_VSUB 0,X,YJNZ 0+ERR_VMOLRSUB 0,A,kJNZ 0+VMOR_LOOPNO_VMOLR: NOPFINISH: JMP 0+FINISHERR_SCALAR: HALTERR_COOP: HALTERR_VECTOR: HALTERR_VALU: HALTERR_SIMUL: HALTERR_VSHUF: HALTERR_VMOLR: HALTAKKU: DC 0CARRY: DC 0X_REG: DC 0Y_REG: DC 0I: DC 0A_REG: DC 0B_REG: DC 0RES_REG: DC 0