Subversion Repositories hpc-16

D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/cpu_pkg.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/cpu_pkg.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling package cpu_pkg

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/con_pkg.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/con_pkg.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling package con_pkg

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/log.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/log.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity log
-- Compiling architecture dataflow of log

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/dp.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/dp.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package dp_pkg
-- Compiling entity dp
-- Compiling architecture rtl of dp
-- Loading package std_logic_unsigned
-- Loading entity regfile
-- Loading entity alu
-- Loading entity shifter
-- Loading entity flags
-- Loading entity fcmp

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/shifter.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/shifter.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling entity shifter
-- Compiling architecture dataflow of shifter

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/dp_pkg.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/dp_pkg.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling package dp_pkg

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/sync.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/sync.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity sync
-- Compiling architecture behavioral of sync
-- Compiling architecture behave2 of sync
-- Loading entity sync

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ram8x16.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ram8x16.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling entity ram8x16
-- Compiling architecture sim of ram8x16

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/test.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/test.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling entity test
-- Compiling architecture sim of test
-- Loading package textio
-- Loading package std_logic_textio
-- Loading entity ramnx16
-- Loading package cpu_pkg
-- Loading entity cpu
-- Loading entity ram8x16

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/arith.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/arith.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package numeric_std
-- Loading package vital_timing
-- Loading package vcomponents
-- Compiling entity m2_1_mxilinx_arith
-- Compiling architecture behavioral of m2_1_mxilinx_arith
-- Loading entity and2b1
-- Loading entity or2
-- Loading entity and2
-- Compiling entity adsu16_mxilinx_arith
-- Compiling architecture behavioral of adsu16_mxilinx_arith
-- Loading entity fmap
-- Loading entity xor3
-- Loading package vital_primitives
-- Loading entity muxcy_l
-- Loading entity muxcy
-- Loading entity xorcy
-- Loading entity muxcy_d
-- Loading entity xor2
-- Loading entity inv
-- Compiling entity arith
-- Compiling architecture behavioral of arith
-- Loading entity adsu16_mxilinx_arith
-- Loading entity m2_1_mxilinx_arith
-- Loading entity gnd

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/con1.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/con1.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package con_pkg
-- Compiling entity con1
-- Compiling architecture rtl of con1
-- Loading entity sync

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/alu.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/alu.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity alu
-- Compiling architecture struct of alu
-- Loading package numeric_std
-- Loading package vital_timing
-- Loading package vcomponents
-- Loading entity arith
-- Loading entity log

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/flags.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/flags.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity flags
-- Compiling architecture behavioral of flags

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ramNx16.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ramNx16.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Loading package textio
-- Loading package std_logic_textio
-- Compiling entity ramnx16
-- Compiling architecture async of ramnx16

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/fcmp.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/fcmp.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity fcmp
-- Compiling architecture behavioral of fcmp

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/regfile.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/regfile.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling entity regfile
-- Compiling architecture behavioral of regfile

} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/cpu.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/cpu.vhd
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package cpu_pkg
-- Compiling entity cpu
-- Compiling architecture struct of cpu
-- Loading package con_pkg
-- Loading entity con1
-- Loading package std_logic_arith
-- Loading package dp_pkg
-- Loading entity dp

} {} {}}