URL
https://opencores.org/ocsvn/i2c/i2c/trunk
Subversion Repositories i2c
[/] [i2c/] [trunk/] [sim/] [i2c_verilog/] [run/] [run] - Rev 72
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#!/bin/csh
set i2c = ../../..
set bench = $i2c/bench
set wave_dir = $i2c/sim/rtl_sim/i2c_verilog/waves
ncverilog \
\
+access+rwc \
+define+WAVES \
\
+incdir+$bench/verilog \
+incdir+$i2c/rtl/verilog \
\
$i2c/rtl/verilog/i2c_master_bit_ctrl.v \
$i2c/rtl/verilog/i2c_master_byte_ctrl.v \
$i2c/rtl/verilog/i2c_master_top.v \
\
$bench/verilog/i2c_slave_model.v \
$bench/verilog/wb_master_model.v \
$bench/verilog/tst_bench_top.v
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