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[/] [i2c_to_wb/] [trunk/] [src/] [i2c_to_wb_config.v] - Rev 4

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`include "timescale.v"
 
 
module
  i2c_to_wb_config
  (
    input   [7:0]       i2c_byte_in,
    input               tip_addr_ack,
    output              i2c_ack_out,
 
    input               wb_clk_i,
    input               wb_rst_i  
  );
 
 
  // --------------------------------------------------------------------
  //  address decoder  
  reg i2c_addr_ack_out_r;
 
  always @(*)
    casez( i2c_byte_in )
      8'b1111_000?: i2c_addr_ack_out_r = 1'b0;
      default:      i2c_addr_ack_out_r = 1'b1;
    endcase
 
 
  // --------------------------------------------------------------------
  //  outputs  
  assign i2c_ack_out = tip_addr_ack ? i2c_addr_ack_out_r : 1'b0;
//   assign i2c_ack_out = 1'b0;
 
 
endmodule
 
 

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