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`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // IBM 650 Reconstruction in Verilog (i650) // // This file is part of the IBM 650 Reconstruction in Verilog (i650) project // http:////www.opencores.org/project,i650 // // Description: Top level. // // Additional Comments: // // Copyright (c) 2015 Robert Abeles // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // either version 2.1 of the License, or (at your option) any // later version. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.opencores.org/lgpl.shtml ////////////////////////////////////////////////////////////////////////////////// `include "defines.v" module toplev ( input clk, input rst, input [0:6] cmd_digit_in, io_buffer_in, input [0:5] command, output [0:6] cmd_digit_out, display_digit, output busy, digit_ready, punch_card, read_card, card_digit_ready, output digit_sync, word_upper, output [0:3] digit_ctr ); wire ap, bp, cp, dp; wire dx, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d1_d5, d5_dx, d5_d10, d1_dx, d5_d9, d10_d1_d5, dxl, dxu, d0l, d0u, d1l, d1u, d2l, d10u; wire w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, wl, wu, ewl; wire s0, s1, s2, s3, s4, hp; wire [0:9] digit_idx; wire [0:3] early_idx, ontime_idx; assign digit_sync = bp; assign digit_ctr = ontime_idx; assign word_upper = wu; timing tm ( .clk(clk), .rst(rst), .ap(ap), .bp(bp), .cp(cp), .dp(dp), .dx(dx), .d0(d0), .d1(d1), .d2(d2), .d3(d3), .d4(d4), .d5(d5), .d6(d6), .d7(d7), .d8(d8), .d9(d9), .d10(d10), .d1_d5(d1_d5), .d5_dx(d5_dx), .d5_d10(d5_d10), .d1_dx(d1_dx), .d5_d9(d5_d9), .d10_d1_d5(d10_d1_d5), .dxl(dxl), .dxu(dxu), .d0l(d0l), .d0u(d0u), .d1l(d1l), .d1u(d1u), .d2l(d2l), .d10u(d10u), .w0(w0), .w1(w1), .w2(w2), .w3(w3), .w4(w4), .w5(w5), .w6(w6), .w7(w7), .w8(w8), .w9(w9), .wl(wl), .wu(wu), .ewl(ewl), .s0(s0), .s1(s1), .s2(s2), .s3(s3), .s4(s4), .hp(hp), .digit_idx(digit_idx), .early_idx(early_idx), .ontime_idx(ontime_idx) ); //----------------------------------------------------------------------------- // Adder input muxes //----------------------------------------------------------------------------- wire [0:6] aa_entry_a, ab_entry_b; //----------------------------------------------------------------------------- // Accumulator //----------------------------------------------------------------------------- wire [0:6] ac_early_out, ac_ontime_out, ac_ped_out; //----------------------------------------------------------------------------- // Adder //----------------------------------------------------------------------------- wire [0:6] ad_adder_out; wire ad_carry_test, ad_no_carry_test, ad_d0l_carry_sig, ad_overflow_stop, ad_overflow_light, ad_overflow_sense_sig; //----------------------------------------------------------------------------- // Address register //----------------------------------------------------------------------------- wire [0:6] ar_addr_th, ar_addr_h, ar_addr_t, ar_addr_u; wire ar_dynamic_addr_hit, ar_addr_no_800x, ar_addr_8000, ar_addr_8001, ar_addr_8002, ar_addr_8003, ar_addr_8002_8003, ar_invalid_addr; //----------------------------------------------------------------------------- // Accumulator and TLU validity checking //----------------------------------------------------------------------------- wire ca_acc_zero, ca_acc_no_zero, ca_check_latch; //----------------------------------------------------------------------------- // Register validity checking //----------------------------------------------------------------------------- wire ck_error_stop, ck_acc_check_light, ck_prog_check_light, ck_dist_check_light; //----------------------------------------------------------------------------- // Decode control //----------------------------------------------------------------------------- wire dc_all_restarts, dc_use_d_for_i, dc_turn_on_single_intlk, dc_turn_on_op_intlk, dc_stop_code, dc_code_69, dc_tlu_sig, dc_mult_sig, dc_divide_sig, dc_reset_sig, dc_no_reset_sig, dc_abs_sig, dc_no_abs_sig, dc_lower_sig, dc_upper_sig, dc_add_sig, dc_subt_sig, dc_right_shift_sig, dc_left_shift_sig, dc_half_correct_sig, dc_shift_count_sig, dc_overflow_sense_latch; //----------------------------------------------------------------------------- // Distributor //----------------------------------------------------------------------------- wire [0:6] ds_early_out, ds_ontime_out; wire ds_back_sig; //----------------------------------------------------------------------------- // Error stop //----------------------------------------------------------------------------- wire es_err_sense_light, es_err_stop_ed0u, es_err_sense_restart, es_restart_reset; //----------------------------------------------------------------------------- // General storage //----------------------------------------------------------------------------- wire [0:4] gs_out; wire gs_double_write, gs_no_write; //----------------------------------------------------------------------------- // Opcode register //----------------------------------------------------------------------------- wire [0:6] op_opreg_t, op_opreg_u; wire op_ri_addr_reg; //----------------------------------------------------------------------------- // Operator controls //----------------------------------------------------------------------------- wire [0:6] oc_data_out, oc_addr_out, oc_console_out, oc_display_digit; wire oc_console_to_addr, oc_acc_ri_console; wire [0:14] oc_gs_ram_addr; wire oc_read_gs, oc_write_gs; wire oc_pgm_start, oc_pgm_stop, oc_err_reset, oc_err_sense_reset; wire oc_run_control, oc_half_or_pgm_stop, oc_ri_storage, oc_ro_storage, oc_storage_control, oc_err_restart_sw, oc_ovflw_stop_sw, oc_ovflw_sense_sw; wire oc_man_pgm_reset, oc_man_acc_reset, oc_set_8000, oc_reset_8000, oc_hard_reset; wire oc_restart_reset_busy; assign display_digit = oc_display_digit; //----------------------------------------------------------------------------- // Program step register //----------------------------------------------------------------------------- wire [0:6] ps_early_out, ps_ontime_out, ps_ped_out; wire ps_restart_sig; //----------------------------------------------------------------------------- // Storage select //----------------------------------------------------------------------------- wire [0:6] ss_selected_out; //----------------------------------------------------------------------------- // Translators //----------------------------------------------------------------------------- wire tr_gs_write; wire [0:4] tr_gs_in; wire [0:6] tr_gs_out; //----------------------------------------------------------------------------- // Accumulator zero check //----------------------------------------------------------------------------- wire zc_acc_no_zero_test, zc_acc_zero_test; add_in_a aa ( .acc_early_out(ac_early_out), .acc_ontime_out(ac_ontime_out), .prog_step_early_out(ps_early_out), .select_storage_out(ss_selected_out), .addr_u(ar_addr_u), .acc_true_add_gate(1'b0), // .acc_compl_add_gate(1'b0), // .left_shift_gate(1'b0), // .prog_step_add_gate(1'b0), // .shift_num_gate(1'b0), // .select_stor_add_gate(1'b0), // .adder_entry_a(aa_entry_a) ); add_in_b ab ( .dist_early_out(ds_early_out), .dist_ontime_out(ds_ontime_out), .special_int_entry(10'd0), // .ontime_dist_add_gate_tlu(1'b0), // .dist_compl_add_gate(1'b0), // .upper_lower_check(1'b0), // .dist_blank_gate(1'b0), // .early_dist_zero_entry(1'b0), // .dist_true_add_gate(1'b0), // .adder_entry_b(ab_entry_b) ); accumulator ac ( .rst(oc_hard_reset), .ap(ap), .bp(bp), .dp(dp), .dx(dx), .d1(d1), .d2(d2), .d10(d10), .dxu(dxu), .d0u(d0u), .wu(wu), .wl(wl), .adder_out(ad_adder_out), .console_out(oc_console_out), .acc_regen_gate(1'b1), // .right_shift_gate(1'b0), // .acc_ri_gate(1'b0), // .acc_ri_console(oc_acc_ri_console), .zero_shift_count(1'b0), // .man_acc_reset(oc_man_acc_reset), .reset_op(1'b0), // .early_idx(early_idx), .ontime_idx(ontime_idx), .early_out(ac_early_out), .ontime_out(ac_ontime_out), .ped_out(ac_ped_out) ); adder ad ( .rst(oc_hard_reset), .ap(ap), .bp(bp), .dp(dp), .dxu(dxu), .dx(dx), .d0u(d0u), .d1(d1), .d1l(d1l), .d10(d10), .d10u(d10u), .wl(wl), .entry_a(aa_entry_a), .entry_b(ab_entry_b), .tlu_on(1'b0), // .left_shift_off(1'b1), // .left_shift_on(1'b0), // .no_carry_insert(1'b0), // .no_carry_blank(1'b0), // .carry_insert(1'b0), // .carry_blank(1'b0), // .zero_insert(1'b0), // .error_reset(oc_err_reset), .quotient_digit_on(1'b0), // .overflow_stop_sw(oc_ovflw_stop_sw), .overflow_sense_sw(oc_ovflw_sense_sw), .mult_div_off(1'b0), // .dist_true_add_gate(1'b0), // .acc_true_add_latch(1'b0), // .shift_overflow(1'b0), // .adder_out(ad_adder_out), .carry_test(ad_carry_test), .no_carry_test(ad_no_carry_test), .d0l_carry_sig(ad_d0l_carry_sig), .overflow_stop(ad_overflow_stop), .overflow_light(ad_overflow_light), .overflow_sense_sig(ad_overflow_sense_sig) ); addr_reg ar ( .rst(oc_hard_reset), .ap(ap), .bp(bp), .dx(dx), .d1(d1), .d2(d2), .d3(d3), .d4(d4), .d5(d5), .d6(d6), .d7(d7), .d8(d8), .d9(d9), .w0(w0), .w1(w1), .w2(w2), .w3(w3), .w4(w4), .w5(w5), .w6(w6), .w7(w7), .w8(w8), .w9(w9), .s0(s0), .s1(s1), .s2(s2), .s3(s3), .s4(s4), .error_reset(oc_err_reset), .restart_a(1'b0), // .set_8000(oc_set_8000), .reset_8000(oc_reset_8000), .tlu_band_change(1'b0), // .double_write(gs_double_write), .no_write(gs_no_write), .bs_to_gs(1'b0), // .ri_gs(1'b0), // .ps_reg_in(ps_ontime_out), .console_in(oc_addr_out), .ri_addr_reg(op_ri_addr_reg), .console_to_addr_reg(oc_console_to_addr), .addr_th(ar_addr_th), .addr_h(ar_addr_h), .addr_t(ar_addr_t), .addr_u(ar_addr_u), .dynamic_addr_hit(ar_dynamic_addr_hit), .addr_no_800x(ar_addr_no_800x), .addr_8000(ar_addr_8000), .addr_8001(ar_addr_8001), .addr_8002(ar_addr_8002), .addr_8003(ar_addr_8003), .addr_8002_8003(ar_addr_8002_8003), .invalid_addr(ar_invalid_addr) ); check_acc_tlu ca ( .rst(oc_hard_reset), .ap(ap), .bp(bp), .d0(d0), .d2(d2), .d1_dx(d1_dx), .acc_ped_out(ac_ped_out), .sel_store_add_gate(1'b0), // .err_reset(oc_err_reset), .carry_test_latch(ad_carry_test), .no_carry_test_latch(ad_no_carry_test), .acc_zero(ca_acc_zero), .acc_no_zero(ca_acc_no_zero), .check_latch(ca_check_latch) ); checking ck ( .rst(oc_hard_reset), .bp(bp), .d1_dx(d1_dx), .acc_ontime(ac_ontime_out), .prog_ontime(ps_ontime_out), .dist_ontime(ds_ontime_out), .error_reset(oc_err_reset), .tlu_or_zero_check(ca_check_latch), .error_stop(ck_error_stop), .acc_check_light(ck_acc_check_light), .prog_check_light(ck_prog_check_light), .dist_check_light(ck_dist_check_light) ); decode_ctl dc ( .rst(oc_hard_reset), .ap(ap), .bp(bp), .cp(cp), .dx(dx), .d0(d0), .d1(d1), .d2(d2), .d3(d3), .d4(d4), .d5(d5), .d6(d6), .d7(d7), .d8(d8), .d9(d9), .d10(d10), .d5_d10(d5_d10), .d10_d1_d5(d10_d1_d5), .dxl(dxl), .dxu(dxu), .d10u(d10u), .opreg_t(op_opreg_t), .opreg_u(op_opreg_u), .addr_u(ar_addr_u), .ontime_dist(ds_ontime_out), .man_ro_storage(1'b0), // .dist_back_sig(ds_back_sig), .d_control(1'b0), // .ena_arith_codes(1'b0), // .pgm_stop_sw(pgm_stop_sw), // *** .acc_zero_test(zc_acc_zero_test), .acc_no_zero_test(zc_acc_no_zero_test), .acc_plus_test(1'b0), // .acc_minus_test(1'b0), // .single_intlk(1'b0), // .arith_restart(1'b0), // .overflow_sense_sig(ad_overflow_sense_sig), .man_acc_reset(oc_man_acc_reset), .all_restarts(dc_all_restarts), .use_d_for_i(dc_use_d_for_i), .turn_on_single_intlk(dc_turn_on_single_intlk), .turn_on_op_intlk(dc_turn_on_op_intlk), .stop_code(dc_stop_code), .code_69(dc_code_69), .tlu_sig(dc_tlu_sig), .mult_sig(dc_mult_sig), .divide_sig(dc_divide_sig), .reset_sig(dc_reset_sig), .no_reset_sig(dc_no_reset_sig), .abs_sig(dc_abs_sig), .no_abs_sig(dc_no_abs_sig), .lower_sig(dc_lower_sig), .upper_sig(dc_upper_sig), .add_sig(dc_add_sig), .subt_sig(dc_subt_sig), .right_shift_sig(dc_right_shift_sig), .left_shift_sig(dc_left_shift_sig), .half_correct_sig(dc_half_correct_sig), .shift_count_sig(dc_shift_count_sig), .overflow_sense_latch(dc_overflow_sense_latch) ); distributor ds ( .rst(oc_hard_reset), .ap(ap), .cp(cp), .dp(dp), .dx(dx), .d0(d0), .d10(d10), .selected_storage(ss_selected_out), .ri_dist(1'd0), // .acc_ontime(ac_ontime_out), .start_acc_dist_ri(1'd0), // .end_acc_dist_ri(1'd0), .acc_dist_ri(1'd0), // .man_acc_reset(oc_man_acc_reset), .early_idx(early_idx), .ontime_idx(ontime_idx), .ontime_out(ds_ontime_out), .early_out(ds_early_out), .dist_back_sig(ds_back_sig) ); error_stop es ( .rst(oc_hard_reset), .ap(ap), .dp(dp), .dxu(dxu), .d10(d10), .wl(wl), .err_restart_sw(oc_err_restart_sw), .err_reset(oc_err_reset), .err_sense_reset(oc_err_sense_reset), .clock_err_sig(1'b0), // .err_stop_sig(ck_error_stop), .restart_reset_busy(oc_restart_reset_busy), .err_sense_light(es_err_sense_light), .err_stop_ed0u(es_err_stop_ed0u), .err_sense_restart(es_err_sense_restart), .restart_reset(es_restart_reset) ); gen_store gs ( .rst(oc_hard_reset), .ap(ap), .dp(dp), .write_gate(tr_gs_write), .addr_th(ar_addr_th), .addr_h(ar_addr_h), .addr_t(ar_addr_t), .dynamic_addr(digit_idx), .gs_in(tr_gs_in), .console_ram_addr(oc_gs_ram_addr), .console_read_gs(oc_read_gs), .console_write_gs(oc_write_gs), .gs_out(gs_out), .double_write(gs_double_write), .no_write(gs_no_write) ); operator_ctl oc ( .rst(rst), .clk(clk), .ap(ap), .dp(dp), .dx(dx), .d0(d0), .d1(d1), .d2(d2), .d3(d3), .d4(d4), .d5(d5), .d6(d6), .d9(d9), .d10(d10), .wu(wu), .wl(wl), .hp(hp), .early_idx(early_idx), .ontime_idx(ontime_idx), .cmd_digit_in(cmd_digit_in), .io_buffer_in(io_buffer_in), .gs_in(tr_gs_out), .acc_ontime(ac_ontime_out), .dist_ontime(ds_ontime_out), .prog_ontime(ps_ontime_out), .command(command), .restart_reset(es_restart_reset), .data_out(oc_data_out), .addr_out(oc_addr_out), .console_out(oc_console_out), .display_digit(oc_display_digit), .console_to_addr(oc_console_to_addr), .acc_ri_console(oc_acc_ri_console), .gs_ram_addr(oc_gs_ram_addr), .read_gs(oc_read_gs), .write_gs(oc_write_gs), .pgm_start(oc_pgm_start), .pgm_stop(oc_pgm_stop), .err_reset(oc_err_reset), .err_sense_reset(oc_err_sense_reset), .run_control(oc_run_control), .half_or_pgm_stop(oc_half_or_pgm_stop), .ri_storage(oc_ri_storage), .ro_storage(oc_ro_storage), .storage_control(oc_storage_control), .err_restart_sw(oc_err_restart_sw), .ovflw_stop_sw(oc_ovflw_stop_sw), .ovflw_sense_sw(oc_ovflw_sense_sw), .man_pgm_reset(oc_man_pgm_reset), .man_acc_reset(oc_man_acc_reset), .set_8000(oc_set_8000), .reset_8000(oc_reset_8000), .hard_reset(oc_hard_reset), .cmd_digit_out(cmd_digit_out), .busy(busy), .digit_ready(digit_ready), .restart_reset_busy(oc_restart_reset_busy), .punch_card(punch_card), .read_card(read_card), .card_digit_ready(card_digit_ready) ); op_reg op ( .rst(oc_hard_reset), .cp(cp), .d0(d0), .d9(d9), .d10(d10), .d1_d5(d1_d5), .d5_dx(d5_dx), .restart_a(1'b0), // .restart_b(1'b0), // .d_alt(1'b0), // .i_alt(1'b0), // .tlu_band_change(1'b0), // .man_prog_reset(oc_man_pgm_reset), .prog_step_ped(ps_ped_out), .opreg_t(op_opreg_t), .opreg_u(op_opreg_u), .ri_addr_reg(op_ri_addr_reg) ); prog_step ps ( .rst(oc_hard_reset), .ap(ap), .dp(dp), .dx(dx), .d0(d0), .d10(d10), .early_idx(early_idx), .ontime_idx(ontime_idx), .man_prog_reset(oc_man_pgm_reset), .rips(1'b0), // .adder_out(ad_adder_out), .sel_store_out(ss_selected_out), .prog_ped_regen(1'b1), // .prog_add(1'b0), // .early_out(ps_early_out), .ontime_out(ps_ontime_out), .ped_out(ps_ped_out), .prog_restart_sig(ps_restart_sig) ); store_select ss ( .d0(d0), .d1_dx(d1_dx), .addr_no_800x(ar_addr_no_800x), .addr_8000(ar_addr_8000), .addr_8001(ar_addr_8001), .addr_8002_8003(ar_addr_8002_8003), .addr_hot_8000(1'b0), // .acc_ontime(ac_ontime_out), .dist_ontime(ds_ontime_out), .gs_out(tr_gs_out), .console_switches(oc_data_out), .acc_plus(1'b0), // .acc_minus(1'b0), // .selected_out(ss_selected_out) ); translators tr ( .dist_early_out(`biq_blank), .bs_out(`biq_blank), .console_out(oc_console_out), .ri_gs(1'b0), // .ri_bs(1'b0), // .ri_console(oc_write_gs), .n800x(ar_addr_no_800x), .console_read_gs(oc_read_gs), .gs_out(gs_out), .gs_write(tr_gs_write), .gs_in(tr_gs_in), .gs_biq_out(tr_gs_out) ); zero_check zc ( .rst(oc_hard_reset), .bp(bp), .d0(d0), .d1_dx(d1_dx), .wu(wu), .acc_no_zero(ca_acc_no_zero), .acc_no_zero_test(zc_acc_no_zero_test), .acc_zero_test(zc_acc_zero_test) ); endmodule
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