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-- VHDL data flow description generated from `comp1_bopo`
--              date : Sat Sep  8 01:32:44 2001


-- Entity Declaration

ENTITY comp1_bopo IS
  PORT (
  kin : in bit_vector(15 DOWNTO 0) ;    -- kin
  kout1 : out bit_vector(16 DOWNTO 0) ; -- kout1
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END comp1_bopo;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF comp1_bopo IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on com1"
    SEVERITY WARNING;


kout1 (0) <= kin (0);

kout1 (1) <= kin (1);

kout1 (2) <= kin (2);

kout1 (3) <= kin (3);

kout1 (4) <= kin (4);

kout1 (5) <= kin (5);

kout1 (6) <= kin (6);

kout1 (7) <= kin (7);

kout1 (8) <= kin (8);

kout1 (9) <= kin (9);

kout1 (10) <= kin (10);

kout1 (11) <= kin (11);

kout1 (12) <= kin (12);

kout1 (13) <= kin (13);

kout1 (14) <= kin (14);

kout1 (15) <= kin (15);

kout1 (16) <= (not (kin (15)) and not (kin (14)) and not (kin (13)) and not
(kin (12)) and not (kin (11)) and not (kin (10)) and not (kin
(9)) and not (kin (8)) and not (kin (7)) and not (kin (6)) and
not (kin (5)) and not (kin (4)) and not (kin (3)) and not (kin
(2)) and not (kin (1)) and not (kin (0)));
END;