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--      File Name    : d_latch.vbe                                     --       
--      Modul Name   : D latch with asynchronized clr                  --
--      Purpose      : To be Syntesized by SCMAP                       --
--      Author       : Martadinata A                                   --
--      Date         : February 18, 2001                               --       

entity d_latch is
port(
  d       : in    bit;  
  en      : in    bit; 
  clr     : in    bit;  
  q       : inout bit;
  vdd     : in    bit;  
  vss     : in    bit   
  );
end d_latch;

architecture vbe of d_latch is
  signal nq  : bit;     
      
begin
  assert ((vdd and not (vss)) = '1')
    report "power supply is missing on d_latch"
    severity warning;
  
  nq <= not ((en and d) or q);
   q <= not ((en and not d) or nq or clr);
   
END ;