Subversion Repositories idea

-- VHDL data flow description generated from `fulladder_bop`
--              date : Tue Sep  4 19:38:11 2001


-- Entity Declaration

ENTITY fulladder_bop IS
  PORT (
  a : in BIT;   -- a
  b : in BIT;   -- b
  cin : in BIT; -- cin
  cout : out BIT;       -- cout
  sout : out BIT;       -- sout
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END fulladder_bop;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF fulladder_bop IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on fulladder"
    SEVERITY WARNING;


sout <= (a xor b xor cin);

cout <= ((b and cin) or (a and (b or cin)));
END;