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-- VHDL data flow description generated from `halfadder_bop`
--              date : Tue Sep  4 19:30:19 2001


-- Entity Declaration

ENTITY halfadder_bop IS
  PORT (
  a : in BIT;   -- a
  b : in BIT;   -- b
  cout : out BIT;       -- cout
  sout : out BIT;       -- sout
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END halfadder_bop;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF halfadder_bop IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on halfadder"
    SEVERITY WARNING;


sout <= (a xor b);

cout <= (a and b);
END;