Subversion Repositories idea

-- VHDL data flow description generated from `heart_ctrl_bop`
--              date : Sat Sep  1 15:57:59 2001


-- Entity Declaration

ENTITY heart_ctrl_bop IS
  PORT (
  vss : in BIT; -- vss
  vdd : in BIT; -- vdd
  finish : out BIT;     -- finish
  reset_crnd : out BIT; -- reset_crnd
  ck_crnd : out BIT;    -- ck_crnd
  sel_in : out BIT;     -- sel_in
  en_key_out : out BIT; -- en_key_out
  en_out : out BIT;     -- en_out
  en7 : out BIT;        -- en7
  en6 : out BIT;        -- en6
  en5 : out BIT;        -- en5
  en4 : out BIT;        -- en4
  en3 : out BIT;        -- en3
  en2 : out BIT;        -- en2
  en1 : out BIT;        -- en1
  round : in bit_vector(0 TO 2) ;       -- round
  key_ready : in BIT;   -- key_ready
  start : in BIT;       -- start
  reset : in BIT;       -- reset
  ck : in BIT   -- ck
  );
END heart_ctrl_bop;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF heart_ctrl_bop IS
  SIGNAL current_state : REG_VECTOR(0 TO 3) REGISTER;   -- current_state
  SIGNAL aux10 : BIT;           -- aux10
  SIGNAL aux9 : BIT;            -- aux9
  SIGNAL aux8 : BIT;            -- aux8
  SIGNAL aux0 : BIT;            -- aux0
  SIGNAL current_state_s0 : BIT;                -- current_state_s0
  SIGNAL current_state_s5 : BIT;                -- current_state_s5
  SIGNAL current_state_s6 : BIT;                -- current_state_s6
  SIGNAL current_state_s7 : BIT;                -- current_state_s7
  SIGNAL current_state_s9 : BIT;                -- current_state_s9
  SIGNAL current_state_s10 : BIT;               -- current_state_s10
  SIGNAL aux5 : BIT;            -- aux5

BEGIN
  aux5 <= (round (2) and round (1) and round (0) and current_state (1)
and not (current_state (0)) and not (current_state (3)));
  current_state_s10 <= (current_state (2) and current_state (3) and current_state (0));
  current_state_s9 <= (not (current_state (1)) and not (current_state (3)) and current_state
(2));
  current_state_s7 <= (not (current_state (0)) and current_state (3) and not (current_state
(2)) and current_state (1));
  current_state_s6 <= (not (current_state (3)) and current_state (0) and not (current_state
(2)) and current_state (1));
  current_state_s5 <= (current_state (3) and not (current_state (1)) and not (current_state
(2)));
  current_state_s0 <= (not (current_state (3)) and current_state (2) and current_state
(1));
  aux0 <= (start and key_ready and not (current_state (0)) and not (current_state
(3)) and not (current_state (1)) and not (current_state (2)));
  aux8 <= (not (reset) and current_state (1) and not (current_state (0))
and not (current_state (3)));
  aux9 <= ((not (current_state (1)) and current_state (0)) or (not (current_state
(2)) and current_state (3) and current_state (0)));
  aux10 <= ((current_state (2) and not (current_state (0)) and current_state
(3)) or aux9);
  label0 : BLOCK ((ck and not (ck'STABLE)) = '1')
  BEGIN
    current_state (3) <= GUARDED (not (reset) and (current_state_s9 or current_state_s6 or aux10));
  END BLOCK label0;
  label1 : BLOCK ((ck and not (ck'STABLE)) = '1')
  BEGIN
    current_state (2) <= GUARDED (reset or current_state_s9 or (not (current_state (2)) and current_state
(3) and current_state (0)) or aux5);
  END BLOCK label1;
  label2 : BLOCK ((ck and not (ck'STABLE)) = '1')
  BEGIN
    current_state (1) <= GUARDED (reset or current_state_s9 or current_state_s7 or current_state_s5
or current_state_s6 or aux9);
  END BLOCK label2;
  label3 : BLOCK ((ck and not (ck'STABLE)) = '1')
  BEGIN
    current_state (0) <= GUARDED (reset or (not (current_state (1)) and current_state (0)) or
current_state_s9 or current_state_s5 or aux0);
  END BLOCK label3;

en1 <= (not (reset) and not (current_state (1)) and current_state (0));

en2 <= (not (reset) and not (current_state (2)) and current_state (3)
and current_state (0));

en3 <= (not (reset) and current_state (2) and not (current_state (0))
and current_state (3));

en4 <= (not (reset) and current_state_s5);

en5 <= (not (reset) and current_state_s6);

en6 <= (not (reset) and current_state_s7);

en7 <= aux8;

en_out <= (not (reset) and current_state_s9);

en_key_out <= ((not (reset) and aux5) or (not (reset) and aux0));

sel_in <= (not (reset) and (round (2) or round (1) or round (0)) and ((current_state
(1) and not (current_state (0)) and not (current_state (3)))
or current_state_s7 or current_state_s5 or current_state_s6
or aux0 or aux10));

ck_crnd <= ((not ((round (2) and round (1) and round (0))) and aux8) or
(not (reset) and (current_state_s10 or current_state_s0)));

reset_crnd <= (not (reset) and current_state_s0);

finish <= (not (reset) and current_state_s10);
END;