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-- VHDL data flow description generated from `control_datain`
--              date : Mon Aug 27 03:14:20 2001


-- Entity Declaration

ENTITY control_datain IS
  PORT (
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  dt_sended : in BIT;   -- dt_sended
  emp_buf : in BIT;     -- emp_buf
  en_bufin : out BIT;   -- en_bufin
  req_dt : out BIT;     -- req_dt
  dt_ready : out BIT;   -- dt_ready
  n_block : out BIT;    -- n_block
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END control_datain;


-- Architecture Declaration

ARCHITECTURE VBE OF control_datain IS
  SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER;       -- current_state
  SIGNAL current_state_s4 : BIT;                -- current_state_s4
  SIGNAL next_state_s4 : BIT;           -- next_state_s4
  SIGNAL current_state_s3 : BIT;                -- current_state_s3
  SIGNAL next_state_s3 : BIT;           -- next_state_s3
  SIGNAL current_state_s2 : BIT;                -- current_state_s2
  SIGNAL next_state_s2 : BIT;           -- next_state_s2
  SIGNAL current_state_s1 : BIT;                -- current_state_s1
  SIGNAL next_state_s1 : BIT;           -- next_state_s1
  SIGNAL current_state_s0 : BIT;                -- current_state_s0
  SIGNAL next_state_s0 : BIT;           -- next_state_s0
  SIGNAL next_state : BIT_VECTOR(2 DOWNTO 0);   -- next_state

BEGIN
  next_state(0) <= (next_state_s2 OR next_state_s3);
  next_state(1) <= next_state_s4;
  next_state(2) <= (next_state_s1 OR next_state_s3);
  next_state_s0 <= ((current_state_s0 AND NOT(dt_sended)) OR (
current_state_s4 AND emp_buf));
  current_state_s0 <= (NOT(current_state(2)) AND NOT(current_state(1)) 
AND NOT(current_state(0)));
  next_state_s1 <= (current_state_s0 AND dt_sended);
  current_state_s1 <= (current_state(2) AND NOT(current_state(0)));
  next_state_s2 <= (current_state_s1 OR (current_state_s2 AND NOT(
dt_sended)));
  current_state_s2 <= (NOT(current_state(2)) AND current_state(0));
  next_state_s3 <= (current_state_s2 AND dt_sended);
  current_state_s3 <= (current_state(2) AND current_state(0));
  next_state_s4 <= (current_state_s3 OR (current_state_s4 AND NOT(
emp_buf)));
  current_state_s4 <= (NOT(current_state(2)) AND current_state(1));
  label0 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
  BEGIN
    current_state(0) <= GUARDED (next_state(0) AND NOT(rst));
  END BLOCK label0;
  label1 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
  BEGIN
    current_state(1) <= GUARDED (next_state(1) AND NOT(rst));
  END BLOCK label1;
  label2 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
  BEGIN
    current_state(2) <= GUARDED (next_state(2) AND NOT(rst));
  END BLOCK label2;

n_block <= ((current_state_s1 AND NOT(rst)) OR (
current_state_s2 AND NOT(rst)));

dt_ready <= ((current_state_s3 AND NOT(rst)) OR (
current_state_s4 AND NOT(rst) AND NOT(emp_buf)));

req_dt <= (rst OR (current_state_s0 AND NOT(rst) AND NOT(
dt_sended)) OR (current_state_s1 AND NOT(rst)) OR (
current_state_s2 AND NOT(rst) AND NOT(dt_sended)) OR (
current_state_s4 AND NOT(rst) AND emp_buf));

en_bufin <= ((current_state_s0 AND NOT(rst) AND dt_sended) OR
 (current_state_s2 AND NOT(rst) AND dt_sended));
END;