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-- VHDL data flow description generated from `control_datain_bop`
--              date : Mon Aug 27 03:14:30 2001


-- Entity Declaration

ENTITY control_datain_bop IS
  PORT (
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  dt_sended : in BIT;   -- dt_sended
  emp_buf : in BIT;     -- emp_buf
  en_bufin : out BIT;   -- en_bufin
  req_dt : out BIT;     -- req_dt
  dt_ready : out BIT;   -- dt_ready
  n_block : out BIT;    -- n_block
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END control_datain_bop;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF control_datain_bop IS
  SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER;       -- current_state
  SIGNAL auxinit1 : BIT;                -- auxinit1
  SIGNAL auxinit2 : BIT;                -- auxinit2
  SIGNAL auxinit3 : BIT;                -- auxinit3

BEGIN
  auxinit3 <= (not (current_state (2)) and not (rst) and dt_sended and not
((not (current_state (0)) and current_state (1))));
  auxinit2 <= (not ((not (current_state (2)) or not (current_state (0)) or
rst)) or (not (current_state (2)) and not (rst) and not (emp_buf)
and current_state (1)));
  auxinit1 <= (not (rst) and (current_state (2) xor current_state (0)));
  label0 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    current_state (0) <= GUARDED auxinit1;
  END BLOCK label0;
  label1 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    current_state (1) <= GUARDED auxinit2;
  END BLOCK label1;
  label2 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    current_state (2) <= GUARDED auxinit3;
  END BLOCK label2;

n_block <= auxinit1;

dt_ready <= auxinit2;

req_dt <= ((not (current_state (2)) or not (current_state (0)) or rst)
and (rst or current_state (2) or (emp_buf and current_state
(1)) or (not (dt_sended) and not ((not (current_state (0)) and
current_state (1))))));

en_bufin <= auxinit3;
END;