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-- VHDL data flow description generated from `control_dataout_bop`
--              date : Mon Aug 27 07:32:00 2001


-- Entity Declaration

ENTITY control_dataout_bop IS
  PORT (
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  cp_ready : in BIT;    -- cp_ready
  emp_bufout : in BIT;  -- emp_bufout
  en_bufout : out BIT;  -- en_bufout
  req_cp : out BIT;     -- req_cp
  cp_sended : out BIT;  -- cp_sended
  n_block : out BIT;    -- n_block
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END control_dataout_bop;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF control_dataout_bop IS
  SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER;       -- current_state
  SIGNAL auxinit1 : BIT;                -- auxinit1
  SIGNAL auxinit2 : BIT;                -- auxinit2

BEGIN
  auxinit2 <= (not (rst) and not (current_state (2)) and ((emp_bufout and current_state
(1)) or (not (current_state (0)) and not (current_state (1))
and cp_ready)));
  auxinit1 <= (not (rst) and (current_state (2) xor current_state (1)));
  label0 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    current_state (0) <= GUARDED ((not (rst) and current_state (2) and current_state (1)) or (not
(rst) and not (emp_bufout) and current_state (0)));
  END BLOCK label0;
  label1 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    current_state (1) <= GUARDED auxinit1;
  END BLOCK label1;
  label2 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    current_state (2) <= GUARDED auxinit2;
  END BLOCK label2;

n_block <= auxinit1;

cp_sended <= ((not (rst) and not (emp_bufout) and current_state (0)) or (not
(current_state (0)) and not (rst) and (current_state (2) or
(not (emp_bufout) and current_state (1)))));

req_cp <= (rst or (emp_bufout and current_state (0)) or (not (current_state
(0)) and not (current_state (2)) and not (current_state (1))
and not (cp_ready)));

en_bufout <= auxinit2;
END;