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-- VHDL data flow description generated from `in_key`
--              date : Sat Sep  1 20:10:14 2001


-- Entity Declaration

ENTITY in_key IS
  PORT (
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  key_sended : in BIT;  -- key_sended
  en_bufin : out BIT;   -- en_bufin
  req_key : out BIT;    -- req_key
  ikey_ready : out BIT; -- ikey_ready
  n_block : out BIT;    -- n_block
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END in_key;


-- Architecture Declaration

ARCHITECTURE VBE OF in_key IS
  SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER;       -- current_state
  SIGNAL current_state_s7 : BIT;                -- current_state_s7
  SIGNAL next_state_s7 : BIT;           -- next_state_s7
  SIGNAL current_state_s6 : BIT;                -- current_state_s6
  SIGNAL next_state_s6 : BIT;           -- next_state_s6
  SIGNAL current_state_s5 : BIT;                -- current_state_s5
  SIGNAL next_state_s5 : BIT;           -- next_state_s5
  SIGNAL current_state_s4 : BIT;                -- current_state_s4
  SIGNAL next_state_s4 : BIT;           -- next_state_s4
  SIGNAL current_state_s3 : BIT;                -- current_state_s3
  SIGNAL next_state_s3 : BIT;           -- next_state_s3
  SIGNAL current_state_s2 : BIT;                -- current_state_s2
  SIGNAL next_state_s2 : BIT;           -- next_state_s2
  SIGNAL current_state_s1 : BIT;                -- current_state_s1
  SIGNAL next_state_s1 : BIT;           -- next_state_s1
  SIGNAL current_state_s0 : BIT;                -- current_state_s0
  SIGNAL next_state_s0 : BIT;           -- next_state_s0
  SIGNAL next_state : BIT_VECTOR(2 DOWNTO 0);   -- next_state

BEGIN
  next_state(0) <= (next_state_s0 OR next_state_s1 OR next_state_s6 
OR next_state_s7);
  next_state(1) <= (next_state_s2 OR next_state_s3 OR next_state_s6 
OR next_state_s7);
  next_state(2) <= (next_state_s1 OR next_state_s3 OR next_state_s5 
OR next_state_s7);
  next_state_s0 <= ((current_state_s0 AND NOT(key_sended)) OR 
current_state_s6);
  current_state_s0 <= (NOT(current_state(2)) AND NOT(current_state(1)) 
AND current_state(0));
  next_state_s1 <= (current_state_s0 AND key_sended);
  current_state_s1 <= (current_state(2) AND NOT(current_state(1)) AND 
current_state(0));
  next_state_s2 <= (current_state_s1 OR (current_state_s2 AND NOT(
key_sended)));
  current_state_s2 <= (NOT(current_state(2)) AND current_state(1) AND 
NOT(current_state(0)));
  next_state_s3 <= (current_state_s2 AND key_sended);
  current_state_s3 <= (current_state(2) AND current_state(1) AND NOT(
current_state(0)));
  next_state_s4 <= (current_state_s3 OR (current_state_s4 AND NOT(
key_sended)));
  current_state_s4 <= (NOT(current_state(2)) AND NOT(current_state(1)) 
AND NOT(current_state(0)));
  next_state_s5 <= (current_state_s4 AND key_sended);
  current_state_s5 <= (current_state(2) AND NOT(current_state(1)) AND 
NOT(current_state(0)));
  next_state_s6 <= current_state_s5;
  current_state_s6 <= (NOT(current_state(2)) AND current_state(1) AND 
current_state(0));
  next_state_s7 <= '0';
  current_state_s7 <= (current_state(2) AND current_state(1) AND 
current_state(0));
  label0 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
  BEGIN
    current_state(0) <= GUARDED (next_state(0) OR rst);
  END BLOCK label0;
  label1 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
  BEGIN
    current_state(1) <= GUARDED (next_state(1) AND NOT(rst));
  END BLOCK label1;
  label2 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
  BEGIN
    current_state(2) <= GUARDED (next_state(2) AND NOT(rst));
  END BLOCK label2;

n_block <= NOT(rst OR (current_state_s0 AND NOT(rst)) OR (
current_state_s6 AND NOT(rst)));

ikey_ready <= (current_state_s6 AND NOT(rst));

req_key <= NOT((current_state_s0 AND NOT(rst) AND key_sended
) OR (current_state_s2 AND NOT(rst) AND key_sended
) OR (current_state_s4 AND NOT(rst) AND key_sended
) OR (current_state_s6 AND NOT(rst)));

en_bufin <= ((current_state_s0 AND NOT(rst) AND key_sended) 
OR (current_state_s2 AND NOT(rst) AND key_sended) 
OR (current_state_s4 AND NOT(rst) AND key_sended));
END;