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-- VHDL data flow description generated from `mux2to1_bop`
--              date : Mon Aug 27 06:31:45 2001


-- Entity Declaration

ENTITY mux2to1_bop IS
  PORT (
  y : in bit_vector(63 DOWNTO 0) ;      -- y
  sel : in BIT; -- sel
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  cp : out bit_vector(31 DOWNTO 0) ;    -- cp
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END mux2to1_bop;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF mux2to1_bop IS
  SIGNAL reg : REG_VECTOR(31 DOWNTO 0) REGISTER;        -- reg
  SIGNAL aux12 : BIT;           -- aux12
  SIGNAL aux11 : BIT;           -- aux11

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on mux2to1"
    SEVERITY WARNING;

  aux11 <= (not (sel) and not (rst));
  aux12 <= (not (rst) and sel);
  label0 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (0) <= GUARDED ((not (y (32)) and not (sel)) or not ((not (rst) and (not (sel)
or y (0)))));
  END BLOCK label0;
  label1 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (1) <= GUARDED ((not (y (33)) and aux11) or (not (y (1)) and aux12));
  END BLOCK label1;
  label2 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (2) <= GUARDED ((not (y (34)) and aux11) or (not (y (2)) and aux12));
  END BLOCK label2;
  label3 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (3) <= GUARDED ((not (y (35)) and aux11) or (not (y (3)) and aux12));
  END BLOCK label3;
  label4 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (4) <= GUARDED ((not (y (36)) and not (sel)) or not ((not (rst) and (not (sel)
or y (4)))));
  END BLOCK label4;
  label5 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (5) <= GUARDED ((not (y (37)) and aux11) or (not (y (5)) and aux12));
  END BLOCK label5;
  label6 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (6) <= GUARDED ((not (y (38)) and aux11) or (not (y (6)) and aux12));
  END BLOCK label6;
  label7 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (7) <= GUARDED ((not (y (39)) and aux11) or (not (y (7)) and aux12));
  END BLOCK label7;
  label8 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (8) <= GUARDED ((not (y (40)) and not (sel)) or not ((not (rst) and (not (sel)
or y (8)))));
  END BLOCK label8;
  label9 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (9) <= GUARDED ((not (y (41)) and aux11) or (not (y (9)) and aux12));
  END BLOCK label9;
  label10 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (10) <= GUARDED ((not (y (42)) and aux11) or (not (y (10)) and aux12));
  END BLOCK label10;
  label11 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (11) <= GUARDED ((not (y (43)) and aux11) or (not (y (11)) and aux12));
  END BLOCK label11;
  label12 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (12) <= GUARDED ((not (y (44)) and not (sel)) or not ((not (rst) and (not (sel)
or y (12)))));
  END BLOCK label12;
  label13 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (13) <= GUARDED ((not (y (45)) and aux11) or (not (y (13)) and aux12));
  END BLOCK label13;
  label14 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (14) <= GUARDED ((not (y (46)) and aux11) or (not (y (14)) and aux12));
  END BLOCK label14;
  label15 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (15) <= GUARDED ((not (y (47)) and aux11) or (not (y (15)) and aux12));
  END BLOCK label15;
  label16 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (16) <= GUARDED ((not (y (48)) and not (sel)) or not ((not (rst) and (not (sel)
or y (16)))));
  END BLOCK label16;
  label17 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (17) <= GUARDED ((not (y (49)) and aux11) or (not (y (17)) and aux12));
  END BLOCK label17;
  label18 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (18) <= GUARDED ((not (y (50)) and aux11) or (not (y (18)) and aux12));
  END BLOCK label18;
  label19 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (19) <= GUARDED ((not (y (51)) and aux11) or (not (y (19)) and aux12));
  END BLOCK label19;
  label20 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (20) <= GUARDED ((not (y (52)) and not (sel)) or not ((not (rst) and (not (sel)
or y (20)))));
  END BLOCK label20;
  label21 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (21) <= GUARDED ((not (y (53)) and aux11) or (not (y (21)) and aux12));
  END BLOCK label21;
  label22 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (22) <= GUARDED ((not (y (54)) and aux11) or (not (y (22)) and aux12));
  END BLOCK label22;
  label23 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (23) <= GUARDED ((not (y (55)) and aux11) or (not (y (23)) and aux12));
  END BLOCK label23;
  label24 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (24) <= GUARDED ((not (y (56)) and not (sel)) or not ((not (rst) and (not (sel)
or y (24)))));
  END BLOCK label24;
  label25 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (25) <= GUARDED ((not (y (57)) and aux11) or (not (y (25)) and aux12));
  END BLOCK label25;
  label26 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (26) <= GUARDED ((not (y (58)) and aux11) or (not (y (26)) and aux12));
  END BLOCK label26;
  label27 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (27) <= GUARDED ((not (y (59)) and aux11) or (not (y (27)) and aux12));
  END BLOCK label27;
  label28 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (28) <= GUARDED ((not (y (60)) and not (sel)) or not ((not (rst) and (not (sel)
or y (28)))));
  END BLOCK label28;
  label29 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (29) <= GUARDED ((not (y (61)) and aux11) or (not (y (29)) and aux12));
  END BLOCK label29;
  label30 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (30) <= GUARDED ((not (y (62)) and aux11) or (not (y (30)) and aux12));
  END BLOCK label30;
  label31 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    reg (31) <= GUARDED ((not (y (63)) and aux11) or (not (y (31)) and aux12));
  END BLOCK label31;

cp (0) <= not (reg (0));

cp (1) <= not (reg (1));

cp (2) <= not (reg (2));

cp (3) <= not (reg (3));

cp (4) <= not (reg (4));

cp (5) <= not (reg (5));

cp (6) <= not (reg (6));

cp (7) <= not (reg (7));

cp (8) <= not (reg (8));

cp (9) <= not (reg (9));

cp (10) <= not (reg (10));

cp (11) <= not (reg (11));

cp (12) <= not (reg (12));

cp (13) <= not (reg (13));

cp (14) <= not (reg (14));

cp (15) <= not (reg (15));

cp (16) <= not (reg (16));

cp (17) <= not (reg (17));

cp (18) <= not (reg (18));

cp (19) <= not (reg (19));

cp (20) <= not (reg (20));

cp (21) <= not (reg (21));

cp (22) <= not (reg (22));

cp (23) <= not (reg (23));

cp (24) <= not (reg (24));

cp (25) <= not (reg (25));

cp (26) <= not (reg (26));

cp (27) <= not (reg (27));

cp (28) <= not (reg (28));

cp (29) <= not (reg (29));

cp (30) <= not (reg (30));

cp (31) <= not (reg (31));
END;