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-- VHDL data flow description generated from `count2`
--              date : Thu Aug  2 08:33:34 2001


-- Entity Declaration

ENTITY count2 IS
  PORT (
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  q : out bit_vector(1 DOWNTO 0) ;      -- q
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END count2;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF count2 IS
  SIGNAL current_state : REG_VECTOR(1 DOWNTO 0) REGISTER;       -- current_state

BEGIN
  label0 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    current_state (0) <= GUARDED (not (current_state (0)) or rst);
  END BLOCK label0;
  label1 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    current_state (1) <= GUARDED (rst or not ((current_state (1) xor current_state (0))));
  END BLOCK label1;

q (0) <= (not (current_state (0)) and not (rst));

q (1) <= (not (current_state (1)) and not (rst));
END;