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-- VHDL data flow description generated from `count3`
--              date : Thu Aug  2 09:53:06 2001


-- Entity Declaration

ENTITY count3 IS
  PORT (
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  q : out bit_vector(2 DOWNTO 0) ;      -- q
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END count3;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF count3 IS
  SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER;       -- current_state
  SIGNAL aux9 : BIT;            -- aux9

BEGIN
  aux9 <= not ((not (current_state (0)) and current_state (2)));
  label0 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    current_state (0) <= GUARDED (rst or not ((current_state (2) xor current_state (1) xor current_state
(0))));
  END BLOCK label0;
  label1 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    current_state (1) <= GUARDED (not (rst) and (current_state (2) or current_state (1)) and aux9);
  END BLOCK label1;
  label2 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    current_state (2) <= GUARDED (not (current_state (2)) or rst);
  END BLOCK label2;

q (0) <= (not (current_state (2)) and not (rst));

q (1) <= (not (rst) and not ((current_state (0) xor (current_state (2)
and current_state (1)))));

q (2) <= (not (rst) and (not (current_state (1)) or current_state (2))
and not ((current_state (2) and current_state (0))));
END;