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-- VHDL data flow description generated from `count4`
--              date : Thu Aug  2 08:55:51 2001


-- Entity Declaration

ENTITY count4 IS
  PORT (
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  q : out bit_vector(3 DOWNTO 0) ;      -- q
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END count4;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF count4 IS
  SIGNAL current_state : REG_VECTOR(3 DOWNTO 0) REGISTER;       -- current_state
  SIGNAL aux35 : BIT;           -- aux35
  SIGNAL aux27 : BIT;           -- aux27
  SIGNAL aux31 : BIT;           -- aux31
  SIGNAL aux32 : BIT;           -- aux32

BEGIN
  aux32 <= (not (rst) and not (current_state (2)));
  aux31 <= (not (rst) and current_state (2));
  aux27 <= (not (current_state (0)) and current_state (1));
  aux35 <= (rst or (not (current_state (2)) and not (current_state (0))
and not (current_state (1))));
  label0 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    current_state (0) <= GUARDED ((not (current_state (3)) and not (current_state (0))) or (current_state
(2) and (not (current_state (3)) or aux27)) or aux35);
  END BLOCK label0;
  label1 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    current_state (1) <= GUARDED (rst or (current_state (0) and (current_state (2) or current_state
(1))) or (not (current_state (0)) and not (current_state (3))
and not (current_state (1))));
  END BLOCK label1;
  label2 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    current_state (2) <= GUARDED ((current_state (3) and (not (current_state (0)) or current_state
(1))) or (current_state (2) and not ((not (current_state (0))
or not (current_state (1))))) or aux35);
  END BLOCK label2;
  label3 : BLOCK ((clk and not (clk'STABLE)) = '1')
  BEGIN
    current_state (3) <= GUARDED ((current_state (3) and aux32 and (not (current_state (0)) or
not (current_state (1)))) or (aux31 and (current_state (0) or
(not (current_state (3)) and current_state (1)))));
  END BLOCK label3;

q (0) <= ((not (current_state (0)) and aux32) or (aux31 and (current_state
(3) xor (not (current_state (0)) or not (current_state (1))))));

q (1) <= ((not (current_state (1)) and aux32) or (aux31 and ((not (current_state
(0)) and current_state (3)) or (not (current_state (3)) and
not (current_state (1))))));

q (2) <= (not (rst) and (not (current_state (2)) or aux27) and (not (current_state
(3)) or not (aux27)));

q (3) <= ((not (current_state (1)) and (not (current_state (0)) or current_state
(3)) and aux31) or (aux32 and (not (current_state (3)) or aux27)));
END;