Subversion Repositories idea

-- VHDL data flow description generated from `ctr_enkeyx`
--              date : Tue Jul 31 14:21:49 2001


-- Entity Declaration

ENTITY ctr_enkeyx IS
  PORT (
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  start : in BIT;       -- start
  count : in bit_vector(2 DOWNTO 0) ;   -- count
  en_shft : out BIT;    -- en_shft
  en_count : out BIT;   -- en_count
  sel1 : out BIT;       -- sel1
  sel2 : out BIT;       -- sel2
  c_count : out BIT;    -- c_count
  finish : out BIT;     -- finish
  en_out : out BIT;     -- en_out
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END ctr_enkeyx;


-- Architecture Declaration

ARCHITECTURE VBE OF ctr_enkeyx IS
  SIGNAL current_state : REG_VECTOR(3 DOWNTO 0) REGISTER;       -- current_state
  SIGNAL current_state_s10 : BIT;               -- current_state_s10
  SIGNAL next_state_s10 : BIT;          -- next_state_s10
  SIGNAL current_state_s9 : BIT;                -- current_state_s9
  SIGNAL next_state_s9 : BIT;           -- next_state_s9
  SIGNAL current_state_s8 : BIT;                -- current_state_s8
  SIGNAL next_state_s8 : BIT;           -- next_state_s8
  SIGNAL current_state_s7 : BIT;                -- current_state_s7
  SIGNAL next_state_s7 : BIT;           -- next_state_s7
  SIGNAL current_state_s6 : BIT;                -- current_state_s6
  SIGNAL next_state_s6 : BIT;           -- next_state_s6
  SIGNAL current_state_s5 : BIT;                -- current_state_s5
  SIGNAL next_state_s5 : BIT;           -- next_state_s5
  SIGNAL current_state_s4 : BIT;                -- current_state_s4
  SIGNAL next_state_s4 : BIT;           -- next_state_s4
  SIGNAL current_state_s3 : BIT;                -- current_state_s3
  SIGNAL next_state_s3 : BIT;           -- next_state_s3
  SIGNAL current_state_s2 : BIT;                -- current_state_s2
  SIGNAL next_state_s2 : BIT;           -- next_state_s2
  SIGNAL current_state_s1 : BIT;                -- current_state_s1
  SIGNAL next_state_s1 : BIT;           -- next_state_s1
  SIGNAL current_state_s0 : BIT;                -- current_state_s0
  SIGNAL next_state_s0 : BIT;           -- next_state_s0
  SIGNAL next_state : BIT_VECTOR(3 DOWNTO 0);   -- next_state

BEGIN
  next_state(0) <= (next_state_s2 OR next_state_s4 OR next_state_s5 
OR next_state_s7 OR next_state_s9 OR next_state_s10
);
  next_state(1) <= (next_state_s3 OR next_state_s5 OR next_state_s7 
OR next_state_s8 OR next_state_s9);
  next_state(2) <= (next_state_s1 OR next_state_s2 OR next_state_s8 
OR next_state_s9);
  next_state(3) <= (next_state_s0 OR next_state_s2 OR next_state_s4 
OR next_state_s5 OR next_state_s8 OR next_state_s9);
  next_state_s0 <= (current_state_s0 AND NOT(start));
  current_state_s0 <= (current_state(3) AND NOT(current_state(2)) AND 
NOT(current_state(0)));
  next_state_s1 <= (current_state_s0 AND NOT(count(1)) AND NOT(
count(0)) AND NOT(count(2)) AND start);
  current_state_s1 <= (NOT(current_state(3)) AND current_state(2) AND 
NOT(current_state(1)));
  next_state_s2 <= (current_state_s1 OR current_state_s2);
  current_state_s2 <= (current_state(3) AND current_state(2) AND NOT(
current_state(1)));
  next_state_s3 <= (current_state_s0 AND NOT(count(1)) AND count(0) 
AND NOT(count(2)) AND start);
  current_state_s3 <= (NOT(current_state(3)) AND current_state(1) AND 
NOT(current_state(0)));
  next_state_s4 <= current_state_s3;
  current_state_s4 <= (current_state(3) AND NOT(current_state(2)) AND 
NOT(current_state(1)) AND current_state(0));
  next_state_s5 <= (current_state_s4 OR current_state_s5);
  current_state_s5 <= (current_state(3) AND NOT(current_state(2)) AND 
current_state(1));
  next_state_s6 <= (current_state_s0 AND ((count(1) AND NOT(count(2)
)) OR ((NOT(count(1)) OR NOT(count(0))) AND 
count(2))) AND start);
  current_state_s6 <= (NOT(current_state(3)) AND NOT(current_state(2)) 
AND NOT(current_state(1)) AND NOT(current_state(0)));
  next_state_s7 <= current_state_s6;
  current_state_s7 <= (NOT(current_state(3)) AND current_state(1) AND 
current_state(0));
  next_state_s8 <= current_state_s7;
  current_state_s8 <= (current_state(3) AND current_state(2) AND NOT(
current_state(0)));
  next_state_s9 <= (current_state_s8 OR current_state_s9);
  current_state_s9 <= (current_state(2) AND current_state(1) AND 
current_state(0));
  next_state_s10 <= ((current_state_s0 AND count(1) AND count(0) AND 
count(2) AND start) OR current_state_s10);
  current_state_s10 <= (NOT(current_state(3)) AND NOT(current_state(1)) 
AND current_state(0));
  label0 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(0) <= GUARDED (next_state(0) AND NOT(rst));
  END BLOCK label0;
  label1 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(1) <= GUARDED (next_state(1) AND NOT(rst));
  END BLOCK label1;
  label2 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(2) <= GUARDED (next_state(2) AND NOT(rst));
  END BLOCK label2;
  label3 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(3) <= GUARDED (next_state(3) OR rst);
  END BLOCK label3;

en_out <= ((current_state_s0 AND NOT(count(1)) AND NOT(
count(0)) AND NOT(count(2)) AND NOT(rst) AND start) OR (
current_state_s3 AND NOT(rst)) OR (current_state_s7 AND NOT(rst))
);

finish <= ((current_state_s0 AND count(1) AND count(0) AND 
count(2) AND NOT(rst) AND start) OR (current_state_s10 
AND NOT(rst)));

c_count <= NOT(rst OR (current_state_s0 AND NOT(rst)) OR (
current_state_s3 AND NOT(rst)) OR (current_state_s6 AND NOT(rst))
 OR (current_state_s7 AND NOT(rst)) OR (
current_state_s10 AND NOT(rst)));

sel2 <= NOT(rst OR (current_state_s0 AND ((NOT(rst) AND 
NOT(start)) OR ((count(1) OR count(2)) AND NOT(rst))
)) OR (current_state_s10 AND NOT(rst)));

sel1 <= '0';

en_count <= NOT(rst OR (current_state_s0 AND ((NOT(rst) AND 
NOT(start)) OR ((count(1) OR count(2)) AND NOT(rst))
)) OR (current_state_s10 AND NOT(rst)));

en_shft <= ((current_state_s0 AND NOT(count(1)) AND count(0)
 AND NOT(count(2)) AND NOT(rst) AND start) OR (
current_state_s6 AND NOT(rst)));
END;