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--Nama file : dec16to288x.vbe
--Deskripsi : decoder (1 x 16bit) to (18 x 16bit)
--Author    : Mas Adit
--Tanggal  : 26 Agustus 2001

entity dec16to288x is
port (
        a : in bit_vector(15 downto 0);
        clr : in bit;
        en : in bit;
        sel : in bit_vector(4 downto 0);
        o1 : out bit_vector(15 downto 0);
        o2 : out bit_vector(15 downto 0);
        o3 : out bit_vector(15 downto 0);
        o4 : out bit_vector(15 downto 0);
        o5 : out bit_vector(15 downto 0);
        o6 : out bit_vector(15 downto 0);
        o7 : out bit_vector(15 downto 0);
        o8 : out bit_vector(15 downto 0);
        o9 : out bit_vector(15 downto 0);
        o10 : out bit_vector(15 downto 0);
        o11 : out bit_vector(15 downto 0);
        o12 : out bit_vector(15 downto 0);
        o13 : out bit_vector(15 downto 0);
        o14 : out bit_vector(15 downto 0);
        o15 : out bit_vector(15 downto 0);
        o16 : out bit_vector(15 downto 0);
        o17 : out bit_vector(15 downto 0);
        o18 : out bit_vector(15 downto 0);
        vdd : in bit;
        vss : in bit
);
end dec16to288x;

architecture vbe of dec16to288x is

constant nol : bit_vector(15 downto 0) := "0000000000000000";

signal temp1 : bit_vector(15 downto 0);
signal temp2 : bit_vector(15 downto 0);
signal temp3 : bit_vector(15 downto 0);
signal temp4 : bit_vector(15 downto 0);
signal temp5 : bit_vector(15 downto 0);
signal temp6 : bit_vector(15 downto 0);
signal temp7 : bit_vector(15 downto 0);
signal temp8 : bit_vector(15 downto 0);
signal temp9 : bit_vector(15 downto 0);
signal temp10 : bit_vector(15 downto 0);
signal temp11 : bit_vector(15 downto 0);
signal temp12 : bit_vector(15 downto 0);
signal temp13 : bit_vector(15 downto 0);
signal temp14 : bit_vector(15 downto 0);
signal temp15 : bit_vector(15 downto 0);
signal temp16 : bit_vector(15 downto 0);
signal temp17 : bit_vector(15 downto 0);
signal temp18 : bit_vector(15 downto 0);

signal tempx1 : bit_vector(15 downto 0);
signal tempx2 : bit_vector(15 downto 0);
signal tempx3 : bit_vector(15 downto 0);
signal tempx4 : bit_vector(15 downto 0);
signal tempx5 : bit_vector(15 downto 0);
signal tempx6 : bit_vector(15 downto 0);
signal tempx7 : bit_vector(15 downto 0);
signal tempx8 : bit_vector(15 downto 0);
signal tempx9 : bit_vector(15 downto 0);
signal tempx10 : bit_vector(15 downto 0);
signal tempx11 : bit_vector(15 downto 0);
signal tempx12 : bit_vector(15 downto 0);
signal tempx13 : bit_vector(15 downto 0);
signal tempx14 : bit_vector(15 downto 0);
signal tempx15 : bit_vector(15 downto 0);
signal tempx16 : bit_vector(15 downto 0);
signal tempx17 : bit_vector(15 downto 0);
signal tempx18 : bit_vector(15 downto 0);

signal reg1 : reg_vector(15 downto 0) register;
signal reg2 : reg_vector(15 downto 0) register;
signal reg3 : reg_vector(15 downto 0) register;
signal reg4 : reg_vector(15 downto 0) register;
signal reg5 : reg_vector(15 downto 0) register;
signal reg6 : reg_vector(15 downto 0) register;
signal reg7 : reg_vector(15 downto 0) register;
signal reg8 : reg_vector(15 downto 0) register;
signal reg9 : reg_vector(15 downto 0) register;
signal reg10 : reg_vector(15 downto 0) register;
signal reg11 : reg_vector(15 downto 0) register;
signal reg12 : reg_vector(15 downto 0) register;
signal reg13 : reg_vector(15 downto 0) register;
signal reg14 : reg_vector(15 downto 0) register;
signal reg15 : reg_vector(15 downto 0) register;
signal reg16 : reg_vector(15 downto 0) register;
signal reg17 : reg_vector(15 downto 0) register;
signal reg18 : reg_vector(15 downto 0) register;

begin

--proses o1
with sel select
temp1 <= a when "00000",
              nol when others;
flip_flop1 : block ((en = '1') and not(en'STABLE))
begin
        reg1 <= guarded temp1;
end block;
tempx1 <= nol when (clr = '1')
               else reg1;
o1 <= tempx1;

--proses o2
with sel select
temp2 <= a when "00001",
              nol when others;
flip_flop2 : block ((en = '1') and not(en'STABLE))
begin
        reg2 <= guarded temp2;
end block;
tempx2 <= nol when (clr = '1')
               else reg2;
o2 <= tempx2;

--proses o3
with sel select
temp3 <= a when "00010",
              nol when others;
flip_flop3 : block ((en = '1') and not(en'STABLE))
begin
        reg3 <= guarded temp3;
end block;
tempx3 <= nol when (clr = '1')
               else reg3;
o3 <= tempx3;

--proses o4
with sel select
temp4 <= a when "00011",
              nol when others;
flip_flop4 : block ((en = '1') and not(en'STABLE))
begin
        reg4 <= guarded temp4;
end block;
tempx4 <= nol when (clr = '1')
               else reg4;
o4 <= tempx4;

--proses o5
with sel select
temp5 <= a when "00100",
              nol when others;
flip_flop5 : block ((en = '1') and not(en'STABLE))
begin
        reg5 <= guarded temp5;
end block;
tempx5 <= nol when (clr = '1')
               else reg5;
o5 <= tempx5;

--proses o6
with sel select
temp6 <= a when "00101",
              nol when others;
flip_flop6 : block ((en = '1') and not(en'STABLE))
begin
        reg6 <= guarded temp6;
end block;
tempx6 <= nol when (clr = '1')
               else reg6;
o6 <= tempx6;

--proses o7
with sel select
temp7 <= a when "00110",
              nol when others;
flip_flop7 : block ((en = '1') and not(en'STABLE))
begin
        reg7 <= guarded temp7;
end block;
tempx7 <= nol when (clr = '1')
               else reg7;
o7 <= tempx7;

--proses o8
with sel select
temp8 <= a when "00111",
              nol when others;
flip_flop8 : block ((en = '1') and not(en'STABLE))
begin
        reg8 <= guarded temp8;
end block;
tempx8 <= nol when (clr = '1')
               else reg8;
o8 <= tempx8;

--proses o9
with sel select
temp9 <= a when "01000",
              nol when others;
flip_flop9 : block ((en = '1') and not(en'STABLE))
begin
        reg9 <= guarded temp9;
end block;
tempx9 <= nol when (clr = '1')
               else reg9;
o9 <= tempx9;

--proses o10
with sel select
temp10 <= a when "01001",
              nol when others;
flip_flop10 : block ((en = '1') and not(en'STABLE))
begin
        reg10 <= guarded temp10;
end block;
tempx10 <= nol when (clr = '1')
               else reg10;
o10 <= tempx10;

--proses o11
with sel select
temp11 <= a when "01010",
              nol when others;
flip_flop11 : block ((en = '1') and not(en'STABLE))
begin
        reg11 <= guarded temp11;
end block;
tempx11 <= nol when (clr = '1')
               else reg11;
o11 <= tempx11;

--proses o12
with sel select
temp12 <= a when "01011",
              nol when others;
flip_flop12 : block ((en = '1') and not(en'STABLE))
begin
        reg12 <= guarded temp12;
end block;
tempx12 <= nol when (clr = '1')
               else reg12;
o12 <= tempx12;

--proses o13
with sel select
temp13 <= a when "01100",
              nol when others;
flip_flop13 : block ((en = '1') and not(en'STABLE))
begin
        reg13 <= guarded temp13;
end block;
tempx13 <= nol when (clr = '1')
               else reg13;
o13 <= tempx13;

--proses o14
with sel select
temp14 <= a when "01101",
              nol when others;
flip_flop14 : block ((en = '1') and not(en'STABLE))
begin
        reg14 <= guarded temp14;
end block;
tempx14 <= nol when (clr = '1')
               else reg14;
o14 <= tempx14;

--proses o15
with sel select
temp15 <= a when "01110",
              nol when others;
flip_flop15 : block ((en = '1') and not(en'STABLE))
begin
        reg15 <= guarded temp15;
end block;
tempx15 <= nol when (clr = '1')
               else reg15;
o15 <= tempx15;

--proses o16
with sel select
temp16 <= a when "01111",
              nol when others;
flip_flop16 : block ((en = '1') and not(en'STABLE))
begin
        reg16 <= guarded temp16;
end block;
tempx16 <= nol when (clr = '1')
               else reg16;
o16 <= tempx16;

--proses o17
with sel select
temp17 <= a when "10000",
              nol when others;
flip_flop17 : block ((en = '1') and not(en'STABLE))
begin
        reg17 <= guarded temp17;
end block;
tempx17 <= nol when (clr = '1')
               else reg17;
o17 <= tempx17;

--proses o18
with sel select
temp18 <= a when "10001",
              nol when others;
flip_flop18 : block ((en = '1') and not(en'STABLE))
begin
        reg18 <= guarded temp18;
end block;
tempx18 <= nol when (clr = '1')
               else reg18;
o18 <= tempx18;

--check power supply
assert ((vdd = '1') and (vss = '0'))
report "power supply is missing on dec16to288x"
severity warning;

end vbe;