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[/] [idea/] [trunk/] [behavioral/] [key_regulator/] [fulladdercout.vbe] - Rev 10

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-- File Name    : fulladdercout.vbe
-- Description  : Full Adder without carry out
-- Author       : Mas Adit
-- Date         : 29 Agustus 2001

ENTITY fulladdercout IS
PORT(
  a     : IN BIT;
  b     : IN BIT;
  cin   : IN BIT;
  sum   : OUT BIT;
  vdd   : in  BIT;
  vss   : in  BIT
);
END fulladdercout;

ARCHITECTURE VBE OF fulladdercout IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
  REPORT "power supply is missing on fulladdercout"
  SEVERITY WARNING;

  sum <= ((a XOR b) XOR cin);
END VBE;



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