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-- VHDL data flow description generated from `kontrol_kuncix`
--              date : Sat Jul 28 17:00:37 2001


-- Entity Declaration

ENTITY kontrol_kuncix IS
  PORT (
  clk : in BIT; -- clk
  start : in BIT;       -- start
  rst : in BIT; -- rst
  f_enkey : in BIT;     -- f_enkey
  f_invmul : in BIT;    -- f_invmul
  f_invadd : in BIT;    -- f_invadd
  rst_all : out BIT;    -- rst_all
  key_ready : out BIT;  -- key_ready
  s_enkey : out BIT;    -- s_enkey
  s_invmul : out BIT;   -- s_invmul
  s_invadd : out BIT;   -- s_invadd
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END kontrol_kuncix;


-- Architecture Declaration

ARCHITECTURE VBE OF kontrol_kuncix IS
  SIGNAL current_state : REG_VECTOR(3 DOWNTO 0) REGISTER;       -- current_state
  SIGNAL current_state_s9 : BIT;                -- current_state_s9
  SIGNAL next_state_s9 : BIT;           -- next_state_s9
  SIGNAL current_state_s8 : BIT;                -- current_state_s8
  SIGNAL next_state_s8 : BIT;           -- next_state_s8
  SIGNAL current_state_s7 : BIT;                -- current_state_s7
  SIGNAL next_state_s7 : BIT;           -- next_state_s7
  SIGNAL current_state_s6 : BIT;                -- current_state_s6
  SIGNAL next_state_s6 : BIT;           -- next_state_s6
  SIGNAL current_state_s5 : BIT;                -- current_state_s5
  SIGNAL next_state_s5 : BIT;           -- next_state_s5
  SIGNAL current_state_s4 : BIT;                -- current_state_s4
  SIGNAL next_state_s4 : BIT;           -- next_state_s4
  SIGNAL current_state_s3 : BIT;                -- current_state_s3
  SIGNAL next_state_s3 : BIT;           -- next_state_s3
  SIGNAL current_state_s2 : BIT;                -- current_state_s2
  SIGNAL next_state_s2 : BIT;           -- next_state_s2
  SIGNAL current_state_s0 : BIT;                -- current_state_s0
  SIGNAL next_state_s0 : BIT;           -- next_state_s0
  SIGNAL next_state : BIT_VECTOR(3 DOWNTO 0);   -- next_state

BEGIN
  next_state(0) <= (next_state_s3 OR next_state_s5 OR next_state_s8 
OR next_state_s9);
  next_state(1) <= (next_state_s0 OR next_state_s4 OR next_state_s5 
OR next_state_s8);
  next_state(2) <= (next_state_s4 OR next_state_s5 OR next_state_s7 
OR next_state_s9);
  next_state(3) <= (next_state_s4 OR next_state_s5 OR next_state_s6 
OR next_state_s8 OR next_state_s9);
  next_state_s0 <= ((current_state_s0 AND NOT(start)) OR 
current_state_s3);
  current_state_s0 <= (NOT(current_state(3)) AND NOT(current_state(2)) 
AND current_state(1));
  next_state_s2 <= (current_state_s0 AND f_enkey AND start);
  current_state_s2 <= (NOT(current_state(3)) AND NOT(current_state(2)) 
AND NOT(current_state(1)) AND NOT(current_state(0)));
  next_state_s3 <= (current_state_s0 AND NOT(f_enkey) AND start);
  current_state_s3 <= (NOT(current_state(3)) AND NOT(current_state(2)) 
AND current_state(0));
  next_state_s4 <= (current_state_s2 AND NOT(f_invmul));
  current_state_s4 <= (current_state(3) AND current_state(2) AND NOT(
current_state(0)));
  next_state_s5 <= (current_state_s2 AND f_invmul);
  current_state_s5 <= (current_state(2) AND current_state(1) AND 
current_state(0));
  next_state_s6 <= ((current_state_s4 AND NOT(f_invadd)) OR 
current_state_s6);
  current_state_s6 <= (current_state(3) AND NOT(current_state(2)) AND 
NOT(current_state(1)));
  next_state_s7 <= ((current_state_s4 AND f_invadd) OR 
current_state_s7);
  current_state_s7 <= (NOT(current_state(3)) AND current_state(2) AND 
NOT(current_state(1)));
  next_state_s8 <= ((current_state_s5 AND NOT(f_invadd)) OR 
current_state_s8);
  current_state_s8 <= (current_state(3) AND NOT(current_state(2)) AND 
current_state(1));
  next_state_s9 <= ((current_state_s5 AND f_invadd) OR 
current_state_s9);
  current_state_s9 <= (current_state(3) AND current_state(2) AND NOT(
current_state(1)));
  label0 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(0) <= GUARDED (next_state(0) AND NOT(rst));
  END BLOCK label0;
  label1 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(1) <= GUARDED (next_state(1) OR rst);
  END BLOCK label1;
  label2 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(2) <= GUARDED (next_state(2) AND NOT(rst));
  END BLOCK label2;
  label3 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(3) <= GUARDED (next_state(3) AND NOT(rst));
  END BLOCK label3;

s_invadd <= ((current_state_s4 AND NOT(rst) AND NOT(f_invadd)
) OR (current_state_s5 AND NOT(rst) AND NOT(
f_invadd)) OR (current_state_s6 AND NOT(rst)) OR (
current_state_s8 AND NOT(rst)));

s_invmul <= ((current_state_s2 AND NOT(rst) AND NOT(f_invmul)
) OR (current_state_s4 AND NOT(rst)) OR (
current_state_s6 AND NOT(rst)) OR (current_state_s7 AND NOT(rst))
);

s_enkey <= (current_state_s0 AND NOT(rst) AND NOT(f_enkey) 
AND start);

key_ready <= ((current_state_s5 AND NOT(rst) AND f_invadd) OR 
(current_state_s9 AND NOT(rst)));

rst_all <= (rst OR (current_state_s0 AND NOT(rst) AND NOT(
start)) OR (current_state_s3 AND NOT(rst)));
END;