Subversion Repositories idea

-- VHDL data flow description generated from `kontrol_utama_invaddx`
--              date : Sun Jul 29 23:45:16 2001


-- Entity Declaration

ENTITY kontrol_utama_invaddx IS
  PORT (
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  start : in BIT;       -- start
  n_dtin : in bit_vector(4 DOWNTO 0) ;  -- n_dtin
  n_dtout : in bit_vector(4 DOWNTO 0) ; -- n_dtout
  c_cdtin : out BIT;    -- c_cdtin
  en_cdtin : out BIT;   -- en_cdtin
  c_cdtout : out BIT;   -- c_cdtout
  en_cdtout : out BIT;  -- en_cdtout
  en_out : out BIT;     -- en_out
  en_in : out BIT;      -- en_in
  finish : out BIT;     -- finish
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END kontrol_utama_invaddx;


-- Architecture Declaration

ARCHITECTURE VBE OF kontrol_utama_invaddx IS
  SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER;       -- current_state
  SIGNAL current_state_s4 : BIT;                -- current_state_s4
  SIGNAL next_state_s4 : BIT;           -- next_state_s4
  SIGNAL current_state_s3 : BIT;                -- current_state_s3
  SIGNAL next_state_s3 : BIT;           -- next_state_s3
  SIGNAL current_state_s2 : BIT;                -- current_state_s2
  SIGNAL next_state_s2 : BIT;           -- next_state_s2
  SIGNAL current_state_s1 : BIT;                -- current_state_s1
  SIGNAL next_state_s1 : BIT;           -- next_state_s1
  SIGNAL current_state_s0 : BIT;                -- current_state_s0
  SIGNAL next_state_s0 : BIT;           -- next_state_s0
  SIGNAL next_state : BIT_VECTOR(2 DOWNTO 0);   -- next_state

BEGIN
  next_state(0) <= (next_state_s1 OR next_state_s3);
  next_state(1) <= (next_state_s3 OR next_state_s4);
  next_state(2) <= (next_state_s0 OR next_state_s3);
  next_state_s0 <= (current_state_s0 AND NOT(start));
  current_state_s0 <= (current_state(2) AND NOT(current_state(1)));
  next_state_s1 <= (current_state_s0 AND (n_dtout(0) OR NOT(
n_dtout(1)) OR n_dtout(2) OR n_dtout(3) OR NOT(n_dtout(4)))
 AND NOT(n_dtin(0)) AND NOT(n_dtin(1)) AND NOT(
n_dtin(2)) AND NOT(n_dtin(3)) AND NOT(n_dtin(4)) AND start
);
  current_state_s1 <= (NOT(current_state(2)) AND current_state(0));
  next_state_s2 <= (current_state_s0 AND (n_dtout(0) OR NOT(
n_dtout(1)) OR n_dtout(2) OR n_dtout(3) OR NOT(n_dtout(4)))
 AND (n_dtin(0) OR n_dtin(1) OR n_dtin(2) OR 
n_dtin(3) OR n_dtin(4)) AND start);
  current_state_s2 <= (NOT(current_state(2)) AND NOT(current_state(1)) 
AND NOT(current_state(0)));
  next_state_s3 <= (current_state_s1 OR current_state_s2 OR 
current_state_s3);
  current_state_s3 <= (current_state(2) AND current_state(1));
  next_state_s4 <= ((current_state_s0 AND NOT(n_dtout(0)) AND 
n_dtout(1) AND NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND 
n_dtout(4) AND start) OR current_state_s4);
  current_state_s4 <= (NOT(current_state(2)) AND current_state(1));
  label0 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(0) <= GUARDED (next_state(0) AND NOT(rst));
  END BLOCK label0;
  label1 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(1) <= GUARDED (next_state(1) AND NOT(rst));
  END BLOCK label1;
  label2 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(2) <= GUARDED (next_state(2) OR rst);
  END BLOCK label2;

finish <= ((current_state_s0 AND NOT(n_dtout(0)) AND 
n_dtout(1) AND NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND 
n_dtout(4) AND NOT(rst) AND start) OR (current_state_s4 AND
 NOT(rst)));

en_in <= (current_state_s0 AND (n_dtout(0) OR NOT(
n_dtout(1)) OR n_dtout(2) OR n_dtout(3) OR NOT(n_dtout(4)))
 AND NOT(rst) AND start);

en_out <= NOT(rst OR (current_state_s0 AND NOT(rst)) OR (
current_state_s4 AND NOT(rst)));

en_cdtout <= NOT(rst OR (current_state_s0 AND ((NOT(rst) AND 
NOT(start)) OR (((NOT(n_dtout(0)) AND n_dtout(1) AND
 NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND 
n_dtout(4)) OR n_dtin(0) OR n_dtin(1) OR n_dtin(2) OR 
n_dtin(3) OR n_dtin(4)) AND NOT(rst)))) OR (
current_state_s4 AND NOT(rst)));

c_cdtout <= (current_state_s0 AND (n_dtout(0) OR NOT(
n_dtout(1)) OR n_dtout(2) OR n_dtout(3) OR NOT(n_dtout(4)))
 AND (n_dtin(0) OR n_dtin(1) OR n_dtin(2) OR 
n_dtin(3) OR n_dtin(4)) AND NOT(rst) AND start);

en_cdtin <= NOT(rst OR (current_state_s0 AND ((NOT(rst) AND 
NOT(start)) OR (((NOT(n_dtout(0)) AND n_dtout(1) AND
 NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND 
n_dtout(4)) OR n_dtin(0) OR n_dtin(1) OR n_dtin(2) OR 
n_dtin(3) OR n_dtin(4)) AND NOT(rst)))) OR (
current_state_s4 AND NOT(rst)));

c_cdtin <= NOT(rst OR (current_state_s0 AND NOT(rst)) OR (
current_state_s4 AND NOT(rst)));
END;