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-- VHDL data flow description generated from `kontrol_utama_invmulx`
--              date : Tue Jul 31 22:47:40 2001


-- Entity Declaration

ENTITY kontrol_utama_invmulx IS
  PORT (
  start : in BIT;       -- start
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  n_stage : in bit_vector(1 DOWNTO 0) ; -- n_stage
  n_iterasi : in bit_vector(3 DOWNTO 0) ;       -- n_iterasi
  n_dtin : in bit_vector(4 DOWNTO 0) ;  -- n_dtin
  n_dtout : in bit_vector(4 DOWNTO 0) ; -- n_dtout
  en_cstage : out BIT;  -- en_cstage
  c_cstage : out BIT;   -- c_cstage
  en_cite : out BIT;    -- en_cite
  c_cite : out BIT;     -- c_cite
  en_cdtin : out BIT;   -- en_cdtin
  c_cdtin : out BIT;    -- c_cdtin
  en_cdtout : out BIT;  -- en_cdtout
  c_cdtout : out BIT;   -- c_cdtout
  en_in : out BIT;      -- en_in
  en_out : out BIT;     -- en_out
  en_pipe : out BIT;    -- en_pipe
  sel : out BIT;        -- sel
  finish : out BIT;     -- finish
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END kontrol_utama_invmulx;


-- Architecture Declaration

ARCHITECTURE VBE OF kontrol_utama_invmulx IS
  SIGNAL current_state : REG_VECTOR(4 DOWNTO 0) REGISTER;       -- current_state
  SIGNAL current_state_s21 : BIT;               -- current_state_s21
  SIGNAL next_state_s21 : BIT;          -- next_state_s21
  SIGNAL current_state_s20 : BIT;               -- current_state_s20
  SIGNAL next_state_s20 : BIT;          -- next_state_s20
  SIGNAL current_state_s19 : BIT;               -- current_state_s19
  SIGNAL next_state_s19 : BIT;          -- next_state_s19
  SIGNAL current_state_s18 : BIT;               -- current_state_s18
  SIGNAL next_state_s18 : BIT;          -- next_state_s18
  SIGNAL current_state_s17 : BIT;               -- current_state_s17
  SIGNAL next_state_s17 : BIT;          -- next_state_s17
  SIGNAL current_state_s16 : BIT;               -- current_state_s16
  SIGNAL next_state_s16 : BIT;          -- next_state_s16
  SIGNAL current_state_s15 : BIT;               -- current_state_s15
  SIGNAL next_state_s15 : BIT;          -- next_state_s15
  SIGNAL current_state_s14 : BIT;               -- current_state_s14
  SIGNAL next_state_s14 : BIT;          -- next_state_s14
  SIGNAL current_state_s13 : BIT;               -- current_state_s13
  SIGNAL next_state_s13 : BIT;          -- next_state_s13
  SIGNAL current_state_s12 : BIT;               -- current_state_s12
  SIGNAL next_state_s12 : BIT;          -- next_state_s12
  SIGNAL current_state_s11 : BIT;               -- current_state_s11
  SIGNAL next_state_s11 : BIT;          -- next_state_s11
  SIGNAL current_state_s10 : BIT;               -- current_state_s10
  SIGNAL next_state_s10 : BIT;          -- next_state_s10
  SIGNAL current_state_s9 : BIT;                -- current_state_s9
  SIGNAL next_state_s9 : BIT;           -- next_state_s9
  SIGNAL current_state_s8 : BIT;                -- current_state_s8
  SIGNAL next_state_s8 : BIT;           -- next_state_s8
  SIGNAL current_state_s7 : BIT;                -- current_state_s7
  SIGNAL next_state_s7 : BIT;           -- next_state_s7
  SIGNAL current_state_s6 : BIT;                -- current_state_s6
  SIGNAL next_state_s6 : BIT;           -- next_state_s6
  SIGNAL current_state_s5 : BIT;                -- current_state_s5
  SIGNAL next_state_s5 : BIT;           -- next_state_s5
  SIGNAL current_state_s4 : BIT;                -- current_state_s4
  SIGNAL next_state_s4 : BIT;           -- next_state_s4
  SIGNAL current_state_s3 : BIT;                -- current_state_s3
  SIGNAL next_state_s3 : BIT;           -- next_state_s3
  SIGNAL current_state_s2 : BIT;                -- current_state_s2
  SIGNAL next_state_s2 : BIT;           -- next_state_s2
  SIGNAL current_state_s1 : BIT;                -- current_state_s1
  SIGNAL next_state_s1 : BIT;           -- next_state_s1
  SIGNAL current_state_s0 : BIT;                -- current_state_s0
  SIGNAL next_state_s0 : BIT;           -- next_state_s0
  SIGNAL next_state : BIT_VECTOR(4 DOWNTO 0);   -- next_state

BEGIN
  next_state(0) <= (next_state_s4 OR next_state_s6 OR next_state_s8 
OR next_state_s9 OR next_state_s11 OR 
next_state_s13 OR next_state_s14 OR next_state_s15 OR 
next_state_s18 OR next_state_s19 OR next_state_s20 OR 
next_state_s21);
  next_state(1) <= (next_state_s2 OR next_state_s3 OR next_state_s6 
OR next_state_s7 OR next_state_s8 OR next_state_s9 
OR next_state_s19);
  next_state(2) <= (next_state_s3 OR next_state_s7 OR next_state_s8 
OR next_state_s9 OR next_state_s11 OR 
next_state_s12 OR next_state_s14 OR next_state_s15 OR 
next_state_s16 OR next_state_s17 OR next_state_s18);
  next_state(3) <= (next_state_s1 OR next_state_s5 OR next_state_s7 
OR next_state_s9 OR next_state_s13 OR 
next_state_s14 OR next_state_s15 OR next_state_s17 OR 
next_state_s20);
  next_state(4) <= (next_state_s0 OR next_state_s5 OR next_state_s7 
OR next_state_s9 OR next_state_s11 OR 
next_state_s12 OR next_state_s15 OR next_state_s19 OR 
next_state_s20 OR next_state_s21);
  next_state_s0 <= (current_state_s0 AND NOT(start));
  current_state_s0 <= (current_state(4) AND NOT(current_state(3)) AND 
NOT(current_state(2)) AND NOT(current_state(0)));
  next_state_s1 <= ((current_state_s0 AND (n_dtout(0) OR NOT(
n_dtout(1)) OR n_dtout(2) OR n_dtout(3) OR NOT(n_dtout(4)))
 AND start) OR current_state_s1);
  current_state_s1 <= (NOT(current_state(4)) AND current_state(3) AND 
NOT(current_state(2)) AND NOT(current_state(0)));
  next_state_s2 <= (current_state_s0 AND NOT(n_dtout(0)) AND 
n_dtout(1) AND NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND 
n_dtout(4) AND NOT(n_iterasi(0)) AND NOT(n_iterasi(1)) AND 
NOT(n_iterasi(2)) AND NOT(n_iterasi(3)) AND NOT(
n_stage(0)) AND NOT(n_stage(1)) AND start);
  current_state_s2 <= (NOT(current_state(2)) AND current_state(1) AND 
NOT(current_state(0)));
  next_state_s3 <= current_state_s2;
  current_state_s3 <= (NOT(current_state(4)) AND current_state(2) AND 
current_state(1) AND NOT(current_state(0)));
  next_state_s4 <= ((current_state_s0 AND NOT(n_dtout(0)) AND 
n_dtout(1) AND NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND 
n_dtout(4) AND NOT(n_iterasi(0)) AND NOT(n_iterasi(1)) AND 
NOT(n_iterasi(2)) AND NOT(n_iterasi(3)) AND (
n_stage(0) OR n_stage(1)) AND start) OR current_state_s3);
  current_state_s4 <= (NOT(current_state(4)) AND NOT(current_state(3)) 
AND NOT(current_state(2)) AND NOT(current_state(1)) 
AND current_state(0));
  next_state_s5 <= (current_state_s4 AND NOT(n_stage(0)) AND 
n_stage(1));
  current_state_s5 <= (current_state(4) AND current_state(3) AND NOT(
current_state(2)) AND NOT(current_state(0)));
  next_state_s6 <= (current_state_s4 AND (n_stage(0) OR NOT(
n_stage(1))));
  current_state_s6 <= (NOT(current_state(4)) AND NOT(current_state(2)) 
AND current_state(1) AND current_state(0));
  next_state_s7 <= current_state_s5;
  current_state_s7 <= (current_state(4) AND current_state(3) AND 
current_state(2) AND NOT(current_state(0)));
  next_state_s8 <= current_state_s6;
  current_state_s8 <= (NOT(current_state(4)) AND current_state(2) AND 
current_state(1) AND current_state(0));
  next_state_s9 <= (current_state_s7 OR current_state_s8 OR 
current_state_s9);
  current_state_s9 <= (current_state(4) AND current_state(3) AND 
current_state(1) AND current_state(0));
  next_state_s10 <= (current_state_s0 AND ((NOT(n_dtout(0)) AND 
n_dtout(1) AND NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND 
n_dtout(4) AND (n_iterasi(0) OR n_iterasi(1) OR 
n_iterasi(2)) AND NOT(n_iterasi(3))) OR (NOT(n_dtout(0)) AND 
n_dtout(1) AND NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND 
n_dtout(4) AND NOT(n_iterasi(0) AND n_iterasi(1) AND 
n_iterasi(2)) AND n_iterasi(3))) AND start);
  current_state_s10 <= (NOT(current_state(4)) AND NOT(current_state(3)) 
AND NOT(current_state(2)) AND NOT(current_state(1)) 
AND NOT(current_state(0)));
  next_state_s11 <= (current_state_s10 AND NOT(n_stage(0)) AND 
n_stage(1));
  current_state_s11 <= (current_state(4) AND NOT(current_state(3)) AND 
current_state(2) AND current_state(0));
  next_state_s12 <= (current_state_s10 AND (n_stage(0) OR NOT(
n_stage(1))));
  current_state_s12 <= (current_state(4) AND NOT(current_state(3)) AND 
current_state(2) AND NOT(current_state(0)));
  next_state_s13 <= current_state_s11;
  current_state_s13 <= (NOT(current_state(4)) AND current_state(3) AND 
NOT(current_state(2)) AND current_state(0));
  next_state_s14 <= current_state_s12;
  current_state_s14 <= (NOT(current_state(4)) AND current_state(3) AND 
current_state(2) AND current_state(0));
  next_state_s15 <= (current_state_s13 OR current_state_s14 OR 
current_state_s15);
  current_state_s15 <= (current_state(4) AND current_state(3) AND 
current_state(2) AND NOT(current_state(1)));
  next_state_s16 <= (current_state_s0 AND NOT(n_dtout(0)) AND 
n_dtout(1) AND NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND 
n_dtout(4) AND n_iterasi(0) AND n_iterasi(1) AND 
n_iterasi(2) AND n_iterasi(3) AND start);
  current_state_s16 <= (NOT(current_state(4)) AND NOT(current_state(3)) 
AND current_state(2) AND NOT(current_state(1)) AND 
NOT(current_state(0)));
  next_state_s17 <= (current_state_s16 AND NOT(n_stage(0)) AND 
n_stage(1));
  current_state_s17 <= (NOT(current_state(4)) AND current_state(3) AND 
current_state(2) AND NOT(current_state(0)));
  next_state_s18 <= (current_state_s16 AND (n_stage(0) OR NOT(
n_stage(1))));
  current_state_s18 <= (NOT(current_state(4)) AND NOT(current_state(3)) 
AND current_state(2) AND NOT(current_state(1)) AND 
current_state(0));
  next_state_s19 <= current_state_s17;
  current_state_s19 <= (current_state(4) AND NOT(current_state(3)) AND 
NOT(current_state(2)) AND current_state(1));
  next_state_s20 <= current_state_s18;
  current_state_s20 <= (current_state(4) AND current_state(3) AND NOT(
current_state(2)) AND current_state(0));
  next_state_s21 <= (current_state_s19 OR current_state_s20 OR 
current_state_s21);
  current_state_s21 <= (current_state(4) AND NOT(current_state(3)) AND 
NOT(current_state(2)) AND NOT(current_state(1)) AND 
current_state(0));
  label0 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(0) <= GUARDED (next_state(0) AND NOT(rst));
  END BLOCK label0;
  label1 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(1) <= GUARDED (next_state(1) AND NOT(rst));
  END BLOCK label1;
  label2 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(2) <= GUARDED (next_state(2) AND NOT(rst));
  END BLOCK label2;
  label3 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(3) <= GUARDED (next_state(3) AND NOT(rst));
  END BLOCK label3;
  label4 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(4) <= GUARDED (next_state(4) OR rst);
  END BLOCK label4;

finish <= ((current_state_s0 AND (n_dtout(0) OR NOT(
n_dtout(1)) OR n_dtout(2) OR n_dtout(3) OR NOT(n_dtout(4)))
 AND NOT(rst) AND start) OR (current_state_s1 AND 
NOT(rst)));

sel <= ((current_state_s0 AND NOT(n_dtout(0)) AND 
n_dtout(1) AND NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND 
n_dtout(4) AND NOT(n_iterasi(0)) AND NOT(n_iterasi(1)) AND 
NOT(n_iterasi(2)) AND NOT(n_iterasi(3)) AND (
n_stage(0) OR n_stage(1)) AND NOT(rst) AND start) OR (
current_state_s2 AND NOT(rst)) OR (current_state_s3 AND NOT(rst))
 OR (current_state_s4 AND NOT(rst)) OR (
current_state_s6 AND NOT(rst)));

en_pipe <= ((current_state_s0 AND NOT(n_dtout(0)) AND 
n_dtout(1) AND NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND 
n_dtout(4) AND (n_iterasi(0) OR n_iterasi(1) OR 
n_iterasi(2) OR n_iterasi(3) OR n_stage(0) OR n_stage(1)) AND
 NOT(rst) AND start) OR (current_state_s3 AND NOT(
rst)) OR (current_state_s4 AND NOT(rst)) OR (
current_state_s5 AND NOT(rst)) OR (current_state_s6 AND NOT(rst))
 OR (current_state_s10 AND NOT(rst)) OR (
current_state_s11 AND NOT(rst)) OR (current_state_s12 AND NOT(rst)
) OR (current_state_s16 AND NOT(rst)) OR (
current_state_s17 AND NOT(rst)) OR (current_state_s18 AND NOT(rst)
));

en_out <= ((current_state_s0 AND NOT(n_dtout(0)) AND 
n_dtout(1) AND NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND 
n_dtout(4) AND n_iterasi(0) AND n_iterasi(1) AND 
n_iterasi(2) AND n_iterasi(3) AND NOT(rst) AND start) OR (
current_state_s16 AND NOT(rst)) OR (current_state_s17 AND NOT(rst)
) OR (current_state_s18 AND NOT(rst)));

en_in <= ((current_state_s0 AND NOT(n_dtout(0)) AND 
n_dtout(1) AND NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND 
n_dtout(4) AND NOT(n_iterasi(0)) AND NOT(n_iterasi(1)) AND 
NOT(n_iterasi(2)) AND NOT(n_iterasi(3)) AND NOT(
n_stage(0)) AND NOT(n_stage(1)) AND NOT(rst) AND start) OR 
(current_state_s4 AND (n_stage(0) OR NOT(
n_stage(1))) AND NOT(rst)) OR (current_state_s6 AND NOT(rst
)));

c_cdtout <= ((current_state_s19 AND NOT(rst)) OR (
current_state_s20 AND NOT(rst)) OR (current_state_s21 AND NOT(rst)
));

en_cdtout <= ((current_state_s11 AND NOT(rst)) OR (
current_state_s13 AND NOT(rst)) OR (current_state_s14 AND NOT(rst)
) OR (current_state_s15 AND NOT(rst)));

c_cdtin <= ((current_state_s0 AND NOT(n_dtout(0)) AND 
n_dtout(1) AND NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND 
n_dtout(4) AND NOT(n_iterasi(0)) AND NOT(n_iterasi(1)) AND 
NOT(n_iterasi(2)) AND NOT(n_iterasi(3)) AND (
n_stage(0) OR n_stage(1)) AND NOT(rst) AND start) OR (
current_state_s2 AND NOT(rst)) OR (current_state_s3 AND NOT(rst))
 OR (current_state_s4 AND NOT(rst)) OR (
current_state_s5 AND NOT(rst)) OR (current_state_s6 AND NOT(rst))
 OR (current_state_s7 AND NOT(rst)) OR (
current_state_s8 AND NOT(rst)) OR (current_state_s9 AND NOT(rst))
);

en_cdtin <= ((current_state_s0 AND NOT(n_dtout(0)) AND 
n_dtout(1) AND NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND 
n_dtout(4) AND NOT(n_iterasi(0)) AND NOT(n_iterasi(1)) AND 
NOT(n_iterasi(2)) AND NOT(n_iterasi(3)) AND NOT(rst)
 AND start) OR (current_state_s2 AND NOT(rst)) OR 
(current_state_s3 AND NOT(rst)) OR (
current_state_s4 AND NOT(rst)) OR (current_state_s5 AND NOT(rst))
 OR (current_state_s6 AND NOT(rst)) OR (
current_state_s7 AND NOT(rst)) OR (current_state_s8 AND NOT(rst))
 OR (current_state_s9 AND NOT(rst)));

c_cite <= NOT(rst OR (current_state_s0 AND NOT(rst)) OR (
current_state_s1 AND NOT(rst)) OR (current_state_s2 AND NOT(rst))
 OR (current_state_s3 AND NOT(rst)) OR (
current_state_s4 AND NOT(rst)) OR (current_state_s6 AND NOT(rst))
 OR (current_state_s10 AND NOT(rst)) OR (
current_state_s12 AND NOT(rst)) OR (current_state_s16 AND NOT(rst)
) OR (current_state_s18 AND NOT(rst)));

en_cite <= NOT(rst OR (current_state_s0 AND ((NOT(rst) AND 
NOT(start)) OR ((n_dtout(0) OR NOT(n_dtout(1)) OR 
n_dtout(2) OR n_dtout(3) OR NOT(n_dtout(4)) OR NOT(
n_iterasi(0) OR n_iterasi(1) OR n_iterasi(2) OR n_iterasi(3) 
OR n_stage(0) OR n_stage(1))) AND NOT(rst)))) OR (
current_state_s1 AND NOT(rst)) OR (current_state_s2 AND NOT(rst))
 OR (current_state_s16 AND NOT(n_stage(0)) AND 
n_stage(1) AND NOT(rst)) OR (current_state_s17 AND NOT(rst)
) OR (current_state_s19 AND NOT(rst)) OR (
current_state_s20 AND NOT(rst)) OR (current_state_s21 AND NOT(rst)
));

c_cstage <= ((current_state_s7 AND NOT(rst)) OR (
current_state_s8 AND NOT(rst)) OR (current_state_s9 AND NOT(rst))
 OR (current_state_s13 AND NOT(rst)) OR (
current_state_s14 AND NOT(rst)) OR (current_state_s15 AND NOT(rst)
) OR (current_state_s19 AND NOT(rst)) OR (
current_state_s20 AND NOT(rst)) OR (current_state_s21 AND NOT(rst)
));

en_cstage <= ((current_state_s4 AND (n_stage(0) OR NOT(
n_stage(1))) AND NOT(rst)) OR (current_state_s6 AND NOT(rst
)) OR (current_state_s10 AND (n_stage(0) OR NOT(
n_stage(1))) AND NOT(rst)) OR (current_state_s12 AND NOT(
rst)) OR (current_state_s16 AND (n_stage(0) OR NOT(
n_stage(1))) AND NOT(rst)) OR (current_state_s18 AND NOT(
rst)));
END;