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-- VHDL data flow description generated from `mux16`
--              date : Fri Jul 27 02:23:26 2001


-- Entity Declaration

ENTITY mux16 IS
  PORT (
  a : in bit_vector(15 DOWNTO 0) ;      -- a
  b : in bit_vector(15 DOWNTO 0) ;      -- b
  sel : in BIT; -- sel
  c : out bit_vector(15 DOWNTO 0) ;     -- c
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END mux16;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF mux16 IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT " power supply is missing on mux02x"
    SEVERITY WARNING;


c (0) <= ((not (sel) and a (0)) or (b (0) and sel));

c (1) <= ((not (sel) and a (1)) or (b (1) and sel));

c (2) <= ((not (sel) and a (2)) or (b (2) and sel));

c (3) <= ((not (sel) and a (3)) or (b (3) and sel));

c (4) <= ((not (sel) and a (4)) or (b (4) and sel));

c (5) <= ((not (sel) and a (5)) or (b (5) and sel));

c (6) <= ((not (sel) and a (6)) or (b (6) and sel));

c (7) <= ((not (sel) and a (7)) or (b (7) and sel));

c (8) <= ((not (sel) and a (8)) or (b (8) and sel));

c (9) <= ((not (sel) and a (9)) or (b (9) and sel));

c (10) <= ((not (sel) and a (10)) or (b (10) and sel));

c (11) <= ((not (sel) and a (11)) or (b (11) and sel));

c (12) <= ((not (sel) and a (12)) or (b (12) and sel));

c (13) <= ((not (sel) and a (13)) or (b (13) and sel));

c (14) <= ((not (sel) and a (14)) or (b (14) and sel));

c (15) <= ((not (sel) and a (15)) or (b (15) and sel));
END;