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-- VHDL data flow description generated from `reg16`
--              date : Tue Jul 31 11:00:32 2001


-- Entity Declaration

ENTITY reg16 IS
  PORT (
  a : in bit_vector(15 DOWNTO 0) ;      -- a
  en : in BIT;  -- en
  clr : in BIT; -- clr
  b : out bit_vector(15 DOWNTO 0) ;     -- b
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END reg16;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF reg16 IS
  SIGNAL reg : REG_VECTOR(15 DOWNTO 0) REGISTER;        -- reg

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on reg15x"
    SEVERITY WARNING;

  label0 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (0) <= GUARDED a (0);
  END BLOCK label0;
  label1 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (1) <= GUARDED a (1);
  END BLOCK label1;
  label2 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (2) <= GUARDED a (2);
  END BLOCK label2;
  label3 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (3) <= GUARDED a (3);
  END BLOCK label3;
  label4 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (4) <= GUARDED a (4);
  END BLOCK label4;
  label5 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (5) <= GUARDED a (5);
  END BLOCK label5;
  label6 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (6) <= GUARDED a (6);
  END BLOCK label6;
  label7 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (7) <= GUARDED a (7);
  END BLOCK label7;
  label8 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (8) <= GUARDED a (8);
  END BLOCK label8;
  label9 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (9) <= GUARDED a (9);
  END BLOCK label9;
  label10 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (10) <= GUARDED a (10);
  END BLOCK label10;
  label11 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (11) <= GUARDED a (11);
  END BLOCK label11;
  label12 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (12) <= GUARDED a (12);
  END BLOCK label12;
  label13 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (13) <= GUARDED a (13);
  END BLOCK label13;
  label14 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (14) <= GUARDED a (14);
  END BLOCK label14;
  label15 : BLOCK ((en and not (en'STABLE)) = '1')
  BEGIN
    reg (15) <= GUARDED a (15);
  END BLOCK label15;

b (0) <= (not (clr) and reg (0));

b (1) <= (not (clr) and reg (1));

b (2) <= (not (clr) and reg (2));

b (3) <= (not (clr) and reg (3));

b (4) <= (not (clr) and reg (4));

b (5) <= (not (clr) and reg (5));

b (6) <= (not (clr) and reg (6));

b (7) <= (not (clr) and reg (7));

b (8) <= (not (clr) and reg (8));

b (9) <= (not (clr) and reg (9));

b (10) <= (not (clr) and reg (10));

b (11) <= (not (clr) and reg (11));

b (12) <= (not (clr) and reg (12));

b (13) <= (not (clr) and reg (13));

b (14) <= (not (clr) and reg (14));

b (15) <= (not (clr) and reg (15));
END;